3–4
3.4
TCM4300 to Microcontroller Interface Timing Requirements (Intel Read
Cycle) (see Figure 3–4 and Note 3)
PARAMETER
ALTERNATE
SYMBOL
MIN
MAX
UNIT
tsu(RA)
Setup time, read address MCA stable before falling edge of
strobe MCDS
TRA(SU)
0
ns
th(RA)
Hold time, read address MCA stable after rising edge of
strobe MCDS
TRA(HO)
10
ns
ten(RD)
Enable time, read data on falling edge of strobe MCDS to
TCM4300 driving data bus MCD
TRD(EN)
10
ns
tv(RD)
Valid time, read data on falling edge of strobe MCDS to
valid data MCD
TRD(DV)
50
ns
tinv
Data MCD invalid after rising edge of strobe MCDS
TRD(INV)
10
ns
tdis(RD)
Disable time, read data. TCM4300 releases MCD data bus
after rising edge of strobe MCDS
TRD(DIS)
28
ns
tsu(CS)
Setup time, chip select MCCSH and MCCSL stable before
falling edge of strobe MCDS
TCS(SU)
0
ns
th(CS)
Hold time, chip select MCCSH and MCCSL stable before
rising edge of strobe MCDS
TCS(HO)
0
ns
NOTE 3: Timings are based upon Intel 80C186 (16 MHz).
MCA4–MCA0
MCD7–MCD0
MCDS
(see Note A)
MCRW
ÏÏ
ÏÏ
ÏÏ
Ï
Ï
Ï
tsu(RA)
10%
90%
90%
10%
th(RA)
tv(RD)
ten(RD)
tdis(RD)
tinv
tsu(CS)
th(CS)
MCCSH
MCCSL
90%
90%
10%
10%
NOTE A: Chip selection is defined as both MCCS and MCDS active.
Figure 3–4. Microcontroller Interface Timing Requirements
(Intel Configuration Read Cycle, MTS [1:0] = 00)
Summary of Contents for TCM4300
Page 1: ...Data Manual 1996 Mixed Signal Products...
Page 2: ...Printed in U S A 10 96 SLWS010F...
Page 23: ...2 8...
Page 35: ...3 12...
Page 67: ...4 32...
