GND
1.8V
IRQZ
CONTROL
SDZ
I2C
SCL
SDA
VBAT
VBAT
GND
1.8V
GND
DF2SE
>>>
SDZIRQZSDOUTSCLSDAFSYNCSBCLKSDIN
><>><
GND
SDIN
SBCLK
FSYNC
SDOUT
ASI
VSENSE2-
VSENSE1-
1
2
3
J10AD0
1
2
3
J11AD1
1
2
3
J12AD0
1
2
3
J13AD1
1.8V
10.0kR6
AD0-2
AD1-2
AD0-1
AD1-1
IRQ2Z
IRQZ
CHANNEL 2
CHANNEL 1ASI
1
3
5
6
4
2
7
9
10
8
12
11
14
13
16
15
18
17
20
19
22
21
24
23
26
25
28
27
30
29
32
31
34
33
36
35
38
37
40
39
J1Power/Analog
1
3
5
6
4
2
7
9
10
8
12
11
14
13
16
15
18
17
20
19
22
21
24
23
26
25
28
27
30
29
32
31
34
33
36
35
38
37
40
39
J2ASI/I2C/CONTROLVSENSE2-VSENSE1-
IOVDD
VBAT
Over Voltage Protection
GND
GND
SCL
SDA
GND
0.1µFC11
GND
10.0kR3
IOVDD
IOVDD
IOVDD
A01
A12
A23
VSS4
SDA5
SCL6
WP7
VCC8
U324FC512-I/ST
GND
TP4GND
J9WP
TP5GND
TP3GND
5.6V
D1
0R7
SDZA1
SBCLKA2
FSYNCA3
SCLA4
SDAA5
DREGA6
SDOUTB1
SDINB2
AD1B3
AD0B4
IRQZB5
VDDB6
VBATC1
VBATC2
VSNS_N1C3
GREGC4
VSNS_P1_N2C5
VSNS_P2C6
BGNDD1
BGNDD2
BGNDD3
GNDD4
PGNDD5
PGNDD6
SWE1
SWE2
SWE3
GNDE4
OUT_PE5
OUT_NE6
VBSTF1
VBSTF2
VBSTF3
PVDDF4
PVDDF5
PVDDF6
TAS2564YBGU2OUT-P2OUT-N2
0R1
0R2
IRQ2Z
VSNS2_P2VSNS1OUT2-
DF2SE
VSENSE2-
OUT2+
OUT2-
OUT2-
OUT2+
0R5
0R4
0R14
0R15VS1P-VS2N2
VS-2
0R18
4
1
2
3
J14OUT2
VS-2VS-OUT2-
GND
GND
OUT2-
OUT2+
SPKR CONFIG
SHUNT3 Wire = 3-42 Wire = 2-3
1µF50VC25
1µF50VC26
1
2
3
J5OUT2
O
U
T
2
+
VS
-2
VS
-P
2
O
U
T
2
-
OUT2-
SDIN
SBCLK
FSYNC
SDOUT
SDZ
SCL
SDA
AD0-2
AD1-2
GND
GND
GND
25V0.1
µ
FC12GREG2DREG2PVDD2
25V0.01uFC8
1µ
F50VC9SW2
1µHL1
VBAT
VBAT2
0R10
Bypass Option
GND
25V0.1
µFC3
GND
GND
1
2
3
4
J3VBAT2
25V10
µFC1
25V10
µFC2
GND
J16VBAT2-SNS
Sensing Only
VDD2
GND
1.8V
GND
25V0.01uFC5
10V4.7uFC4
J4VDD2
GND
GND
GND
PVDD2
TP1PVDD2
25V1uFC7 25V10
µFC6
25V10
µFC10
GND
330pFC23
2.0R20
SDZA1
SBCLKA2
FSYNCA3
SCLA4
SDAA5
DREGA6
SDOUTB1
SDINB2
AD1B3
AD0B4
IRQZB5
VDDB6
VBATC1
VBATC2
VSNS_N1C3
GREGC4
VSNS_P1_N2C5
VSNS_P2C6
BGNDD1
BGNDD2
BGNDD3
GNDD4
PGNDD5
PGNDD6
SWE1
SWE2
SWE3
GNDE4
OUT_PE5
OUT_NE6
VBSTF1
VBSTF2
VBSTF3
PVDDF4
PVDDF5
PVDDF6
TAS2564YBGU1
IRQZ
SDIN
SBCLK
FSYNC
SDOUT
SDZ
SCL
SDA
GND
SW1
VBAT
VBAT1
Bypass Option
GND
GND
GND
GND
Sensing Only
VDD1
GND
1.8V
GND
GND
GND
GND
PVDD1
GND
GND
GND
OUT1-
OUT1+
1µF50VC27
1µF50VC28
DF2SE
OUT1-
OUT1+
VSENSE1-
0R12
0R11
OUT1+
OUT1-
OUT-P1OUT-N1
0R8
0R9
VSNS2_P1VSNS1_N1
0R16
0R17VS1P-VS2N1VS-1
0R19
4
1
2
3
J15OUT1VS-1VS-OUT1-
OUT1+OUT1-
1
2
3
J8OUT1OUT1-
SPKR CONFIG
SHUNT3 Wire = 3-42 Wire = 2-3
VS
-P
1
O
U
T
1
+
VS
-1
O
U
T
1
-
25V0.1
µ
FC24GREG1DREG1
25V0.01uFC20
1µF50VC21
GND
GND
AD0-1
AD1-1
TP2PVDD1
25V0.01uFC17
10V4.7uFC16
25V10
µFC18
25V10
µFC22
J7VDD1
25V1uFC19
PVDD1
0R13
25V0.1
µFC15
25V10
µFC13
25V10
µFC14
1
2
3
4
J6VBAT1
J17VBAT1-SNS
330pFC29
2.0R21
1µHL2
TP6GND
EVM Schematics
11
SLAU812 – July 2019
Copyright © 2019, Texas Instruments Incorporated
TAS2564YBGEVM-DC User's Guide
•
I
2
C Clock (SCLK)
•
I
2
C Data (SDA) The selection between USB (internal) and external inputs is set using the control
header on PPC3-EVM-MB.
Please refer to for detailed configuration settings.
8
EVM Schematics
Figure 14. EVM Schematic