January 6, 2010
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Hardware Description
In addition to a microcontroller, the Stellaris LM3S2965 evaluation board includes a range of useful
peripherals and an integrated ICDI. This chapter describes how these peripherals operate and
interface to the microcontroller.
LM3S2965 Evaluation Board
LM3S2965 Microcontroller Overview
The heart of the EVB is a Stellaris LM3S2965 ARM Cortex-M3-based microcontroller. The
LM3S2965 offers 256-KB flash memory, 50-MHz operation, a CAN module, and a wide range of
peripherals. Refer to the LM3S2965 data sheet (order number DS-LM3S2965) for complete device
details.
The LM3S2965 microcontroller is factory programmed with a quickstart demo program. The
quickstart program resides in the LM3S2965 on-chip flash memory and runs each time power is
applied, unless the quickstart has been replaced with a user program.
CAN Module
A key feature of the LM3S2965 is its CAN module that enables highly reliable communications at
up to 1 Mbits/s. The LM3S2965 evaluation board includes a standard CAN transceiver and a
10-pin CAN connector whose signal assignments follow a commonly used CAN standard. A
simple adaptor (not included in the kit) can be used to allow the use of standard DB-9 CAN cables.
An on-board 120-ohm resistor provides bus termination. This resistor can be removed if the board
is not a network endpoint.
The CAN transceiver is configured in hardware to support speeds up to 1 Mbits/s. A resistor can
be added to reduce the transceiver's drive slew-rate for slower data rates over longer distances.
Clocking
The LM3S2965 microcontroller has three on-chip oscillators, two are implemented on the EVB. A
8.0-MHz crystal completes the LM3S2965’s main internal clock circuit. An internal PLL, configured
in software, multiples this clock to 50-MHz for core and peripheral timing. At initial power on, the
microcontroller operates directly from a 12-MHz internal oscillator.
Reset
The LM3S2965 microcontroller shares its external reset input with the OLED display. In the EVB,
reset sources are gated through the CPLD, though in a typical application a simple wired-OR
arrangement is sufficient.
Reset is asserted (active low) under any one of three conditions:
Power-on reset
Reset push switch SW1 held down
Internal debug mode—By the USB device controller (U5 FT2232) when instructed by
debugger
C H A P T E R 2