Table 7-2. Signal Descriptions (continued)
FUNCTION
SIGNAL NAME
PIN
NO.
PIN
TYPE
SIGNAL
DIRECTION
DESCRIPTION
HOST SPI
HOST_SPI_CLK
5
I/O
I
Host SPI clock input
HOST_SPI_MOSI
6
I/O
I
Data from Host
HOST_SPI_MISO
7
I/O
O
Data to Host
HOST_SPI_nCS
8
I/O
I
Device select (active low)
FLASH SPI
FLASH_SPI_MISO
13
O
I
External serial Flash interface: SPI data out
FLASH_SPI_CS
14
I
O
External serial Flash interface: SPI chip select (active
low)
FLASH_SPI_CLK
15
I
O
External serial Flash interface: SPI clock
FLASH_SPI_MOSI
17
I
O
External serial Flash interface: SPI data in
UART
UART1_nRTS
44
I/O
O
UART1 request-to-send (active low)
UART1_TX
46
I/O
I
UART TX data
UART1_RX
47
I/O
O
UART RX data
UART1_nCTS
51
I/O
I
UART1 clear-to-send (active low)
Sense-On-Power
SOP2
23
O
I
Sense-on-power 2
SOP1
24
I
I
Configuration sense-on-power 1
SOP0
34
I
I
Configuration sense-on-power 0
Power
VBAT1
37
-
-
Power supply for the module
VBAT2
40
-
-
Power supply for the module
nHIB
nHIB
4
I
I
Hibernate signal input to the NWP subsystem (active
low)
RF
RF_ABG
31
I/O
I/O
WLAN analog RF 802.11 a/b/g/n bands
Test Port
TEST_58
48
O
O
Test Signal
TEST_59
49
I
I
Test Signal
TEST_60
50
O
O
Test Signal
TEST_62
52
O
O
Test Signal
(1)
LPDS retention unavailable.
(2)
The CC3135MOD modules are compatible with TI BLE modules using an external RF switch.
(3)
This pin has dual functions: as a SOP[2] (device operation mode), and as an external TCXO enable. As a TXCO enable, the pin is an
output on power up and driven logic high. During hibernate low-power mode, the pin is in a Hi-Z state but is pulled down for SOP mode
to disable TCXO. Because of the SOP functionality, the pin must be used as an output only.
SWRS225D – FEBRUARY 2019 – REVISED MAY 2021
Copyright © 2021 Texas Instruments Incorporated
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