DISABLED
pwr down
DISABLED
Mode 2
If switch to enabled is needed, the
following sequence is required:
OFF
SPLIT
INIT
ENABLED
INIT
TAG
memory is
corrupted
ROM
7.2.2.2
Mode 2
Mode 2 is intended for systems where cache is in GPRAM mode. VIMS is retained with retention power to
the GPRAM.
NOTE:
If software tries to put VIMS into enabled mode after retention, the system fails because the
TAG memory is corrupted.
The correct procedure is to put VIMS into off mode; then put VIMS into disabled mode (see
for
more details).
Figure 7-8. GPRAM Retention
7.3
ROM
The ROM contains a serial bootloader with SPI and UART support (see
Bootloader
chapter),
as well as a Driver Library and an RF stack support. See ,
Memory Map
chapter for details.
7.4
FLASH
The flash memory is organized as a set of 4-KB blocks that can be individually erased. An individual 32-bit
word can be programmed to change bits from 1 to 0. In addition, a write buffer provides the ability to
program 32 continuous words in flash memory in half the time of programming the words individually.
Erasing a block causes the entire contents of the block to be reset to all 1s. The 4-KB blocks are paired
with sets of 8-KB blocks that can be individually protected. The protection allows blocks to be marked as
read-only or execute-only, thus providing different levels of code protection. Read-only blocks cannot be
erased or programmed, which protects the contents of those blocks from being modified. Execute-only
blocks cannot be erased or programmed and can only be read by the controller instruction fetch
mechanism, which protects the contents of those blocks from being read by either the controller or a
debugger.
The Flash block is mainly clocked by the 48-MHz system clock.
7.4.1 FLASH Memory Protection
The FLASH memory can be read/write protected in 4-KB sectors by configuring the CCFG.
539
SWCU117C – February 2015 – Revised September 2015
Versatile Instruction Memory System (VIMS)
Copyright © 2015, Texas Instruments Incorporated