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Control Registers and Control Packets

563

SPNU503C – March 2018

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Direct Memory Access Controller (DMA) Module

Table 16-8. DMA Control Registers (continued)

Offset

Acronym

Register Description

Section

154h

HBCAOFFSET

HBCA Interrupt Channel Offset Register

Section 16.3.1.38

158h

BTCAOFFSET

BTCA Interrupt Channel Offset Register

Section 16.3.1.39

160h

FTCBOFFSET

FTCB Interrupt Channel Offset Register

Section 16.3.1.40

164h

LFSBOFFSET

LFSB Interrupt Channel Offset Register

Section 16.3.1.41

168h

HBCBOFFSET

HBCB Interrupt Channel Offset Register

Section 16.3.1.42

16Ch

BTCBOFFSET

BTCB Interrupt Channel Offset Register

Section 16.3.1.43

178h

PTCRL

Port Control Register

Section 16.3.1.44

17Ch

RTCTRL

RAM Test Control Register

Section 16.3.1.45

180h

DCTRL

Debug Control Register

Section 16.3.1.46

184h

WPR

Watch Point Register

Section 16.3.1.47

188h

WMR

Watch Mask Register

Section 16.3.1.48

198h

PBACSADDR

Port B Active Channel Source Address Register

Section 16.3.1.49

19Ch

PBACDADDR

Port B Active Channel Destination Address Register

Section 16.3.1.50

1A0h

PBACTC

Port B Active Channel Transfer Count Register

Section 16.3.1.51

1A8h

DMAPCR

Parity Control Register

Section 16.3.1.52

1ACh

DMAPAR

DMA Parity Error Address Register

Section 16.3.1.53

1B0h

DMAMPCTRL

DMA Memory Protection Control Register

Section 16.3.1.54

1B4h

DMAMPST

DMA Memory Protection Status Register

Section 16.3.1.55

1B8h

DMAMPR0S

DMA Memory Protection Region 0 Start Address Register

Section 16.3.1.56

1BCh

DMAMPR0E

DMA Memory Protection Region 0 End Address Register

Section 16.3.1.57

1C0h

DMAMPR1S

DMA Memory Protection Region 1 Start Address Register

Section 16.3.1.58

1C4h

DMAMPR1E

DMA Memory Protection Region 1 End Address Register

Section 16.3.1.59

1C8h

DMAMPR2S

DMA Memory Protection Region 2 Start Address Register

Section 16.3.1.60

1CCh

DMAMPR2E

DMA Memory Protection Region 2 End Address Register

Section 16.3.1.61

1D0h

DMAMPR3S

DMA Memory Protection Region 3 Start Address Register

Section 16.3.1.62

1D4h

DMAMPR3E

DMA Memory Protection Region 3 End Address Register

Section 16.3.1.63

Table 16-9. Control Packet Memory Map

Offset

Acronym

Register Description

Section

Primary Control Packet 0

00h

ISADDR

Initial Source Address Register

Section 16.3.2.1

04h

IDADDR

Initial Destination Address Register

Section 16.3.2.2

08h

ITCOUNT

Initial Transfer Count Register

Section 16.3.2.3

10h

CHCTRL

Channel Control Register

Section 16.3.2.4

14h

EIOFF

Element Index Offset Register

Section 16.3.2.5

18h

FIOFF

Frame Index Offset Register

Section 16.3.2.6

Working Control Packet 0

800h

CSADDR

Current Source Address Register

Section 16.3.2.7

804h

CDADDR

Current Destination Address Register

Section 16.3.2.8

808h

CTCOUNT

Current Transfer Count Register

Section 16.3.2.9

Summary of Contents for RM48 series

Page 1: ...RM48x 16 32 Bit RISC Flash Microcontroller Technical Reference Manual Literature Number SPNU503C March 2018...

Page 2: ...114 2 4 1 Clock Sources 114 2 4 2 Clock Domains 115 2 4 3 Low Power Modes 117 2 4 4 Clock Test Mode 119 2 4 5 Embedded Trace Macrocell ETM R4 120 2 4 6 Safety Considerations for Clocks 121 2 5 System...

Page 3: ...N Diagnostic Compare Status Register 1 MPDDCSTAT1 224 3 4 19 Memory PD PSCON Diagnostic Compare Status Register 2 MPDDCSTAT2 225 3 4 20 Isolation Diagnostic Status Register ISODIAGSTAT 226 4 I O Multi...

Page 4: ...IM_ADD_TAG 276 5 7 11 Duplicate Address Tag Register FDUP_ADD_TAG 276 5 7 12 Flash Bank Protection Register FBPROT 277 5 7 13 Flash Bank Sector Enable Register FBSE 277 5 7 14 Flash Bank Busy Register...

Page 5: ...ntrol Register RAMINTCTRL 313 6 7 5 TCRAM Module Error Status Register RAMERRSTATUS 314 6 7 6 TCRAM Module Single Bit Error Address Register RAMSERRADDR 315 6 7 7 TCRAM Module Uncorrectable Error Addr...

Page 6: ...TCGSTAT 352 8 4 7 Self Test Fail Status Register STCFSTAT 353 8 4 8 CPU1 Current MISR Register CPU1_CURMISR 3 0 354 8 4 9 CPU2_CURMISR 3 0 CPU2 Current MISR Register 355 8 4 10 STCSCSCR Signature Comp...

Page 7: ...11 4 DCC Control Registers 399 11 4 1 DCC Global Control Register DCCGCTRL 400 11 4 2 DCC Revision Id Register DCCREV 401 11 4 3 DCC Counter0 Seed Register DCCCNT0SEED 401 11 4 4 DCC Valid0 Seed Regis...

Page 8: ...s 434 13 2 3 RTI Clocking 435 13 2 4 Synchronizing Timer Events to Network Time NTU 435 13 2 5 Digital Watchdog DWD 438 13 2 6 Low Power Modes 441 13 2 7 Halting Debug Mode Behaviour 441 13 3 RTI Cont...

Page 9: ...475 14 2 1 General Operation 475 14 2 2 CRC Modes of Operation 475 14 2 3 PSA Signature Register 476 14 2 4 PSA Sector Signature Register 477 14 2 5 CRC Value Register 478 14 2 6 Raw Data Register 478...

Page 10: ...egister PSA_SECSIGREGH2 508 14 4 33 Channel 2 Raw Data Low Register RAW_DATAREGL2 509 14 4 34 Channel 2 Raw Data High Register RAW_DATAREGH2 509 14 4 35 Data Bus Selection Register CRC_TRACE_BUS_SEL 5...

Page 11: ...ng 557 16 2 11 Power Management 557 16 2 12 FIFO Buffer 557 16 2 13 Channel Chaining 558 16 2 14 Memory Protection 559 16 2 15 Parity Checking 560 16 2 16 Parity Testing 561 16 2 17 Initializing RAM w...

Page 12: ...8 3 3 POM Clock Gate Control Register POMCLKCTRL 677 18 3 4 POM Status Register POMFLG 678 18 3 5 POM Program Region Start Address Register x POMPROGSTARTx 679 18 3 6 POM Overlay Region Start Address...

Page 13: ...ory Overrun Option 704 19 4 5 Response on Writing Non Zero Value to Conversion Group s Channel Select Register 704 19 4 6 Conversion Result Size on Reading 8 bit 10 bit or 12 bit 705 19 4 7 Option to...

Page 14: ...753 19 11 25 ADC Event Group Sampling Time Configuration Register ADEVSAMP 754 19 11 26 ADC Group1 Sampling Time Configuration Register ADG1SAMP 754 19 11 27 ADC Group2 Sampling Time Configuration Reg...

Page 15: ...verview 788 20 1 1 Features 788 20 1 2 Major Advantages 788 20 1 3 Block Diagram 789 20 1 4 Timer Module Structure and Execution 790 20 1 5 Performance 791 20 1 6 N2HET Compared to NHET 791 20 1 7 NHE...

Page 16: ...0 880 20 5 3 HWAG Global Control Register 1 HWAGCR1 880 20 5 4 HWAG Global Control Register 2 HWAGCR2 881 20 5 5 HWAG Interrupt Enable Set Register HWAENASET 882 20 5 6 HWAG Interrupt Enable Clear Reg...

Page 17: ...BER Interrupt Flag Register HTU BERINTFL 997 21 4 18 Memory Protection 1 Start Address Register HTU MP1S 998 21 4 19 Memory Protection 1 End Address Register HTU MP1E 998 21 4 20 Debug Control Registe...

Page 18: ...DR A B 1041 22 5 17 GIO Pull Disable Registers GIOPULDIS A B 1042 22 5 18 GIO Pull Select Registers GIOPSL A B 1042 22 6 I O Control Summary 1043 23 Controller Area Network DCAN Module 1044 23 1 Overv...

Page 19: ...ission 1068 23 9 2 Auto Bus On 1069 23 10 Interrupt Functionality 1069 23 10 1 Message Object Interrupts 1069 23 10 2 Status Change Interrupts 1070 23 10 3 Error Interrupts 1070 23 11 Global Power Dow...

Page 20: ...F3 Update Enable Registers DCAN IF3UPD12 to IF3UPD78 1113 23 17 30 CAN TX IO Control Register DCAN TIOC 1114 23 17 31 CAN RX IO Control Register DCAN RIOC 1115 24 Multi Buffered Serial Peripheral Inte...

Page 21: ...24 9 24 SPI Pin Control Register 9 SPIPC9 1185 24 9 25 Parallel Modulo Mode Control Register SPIPMCTRL 1186 24 9 26 Multi buffer Mode Enable Register MIBSPIE 1189 24 9 27 TG Interrupt Enable Set Regi...

Page 22: ...ffered Mode 1240 25 3 SCI Interrupts 1242 25 3 1 Transmit Interrupt 1243 25 3 2 Receive Interrupt 1243 25 3 3 WakeUp Interrupt 1243 25 3 4 Error Interrupts 1244 25 4 SCI DMA Interface 1245 25 4 1 Rece...

Page 23: ...er 3 SCIPIO3 1309 25 13 18 SCI Pin I O Control Register 4 SCIPIO4 1310 25 13 19 SCI Pin I O Control Register 5 SCIPIO5 1311 25 13 20 SCI Pin I O Control Register 6 SCIPIO6 1312 25 13 21 SCI Pin I O Co...

Page 24: ...12 SCI Data Buffers SCIED SCIRD SCITD 1358 26 7 13 SCI Pin I O Control Register 0 SCIPIO0 1359 26 7 14 SCI Pin I O Control Register 1 SCIPIO1 1360 26 7 15 SCI Pin I O Control Register 2 SCIPIO2 1361...

Page 25: ...CCNT 1394 27 6 7 I2C Data Receive Register I2CDRR 1394 27 6 8 I2C Slave Address Register I2CSAR 1395 27 6 9 I2C Data Transmit Register I2CDXR 1395 27 6 10 I2C Mode Register I2CMDR 1396 27 6 11 I2C Int...

Page 26: ...ters C0RXTHRESHSTAT 1466 28 3 9 EMAC Control Module Receive Interrupt Status Registers C0RXSTAT 1467 28 3 10 EMAC Control Module Transmit Interrupt Status Registers C0TXSTAT 1468 28 3 11 EMAC Control...

Page 27: ...HRESH 1507 28 5 27 Receive Channel Flow Control Threshold Registers RX0FLOWTHRESH RX7FLOWTHRESH 1508 28 5 28 Receive Channel Free Buffer Count Registers RX0FREEBUFFER RX7FREEBUFFER 1508 28 5 29 MAC Co...

Page 28: ...evice Interrupt 1617 29 3 13 Setup Interrupt Handler 1618 29 3 14 Endpoint 0 RX Interrupt Handler 1621 29 3 15 Endpoint 0 TX Interrupt Handler 1622 29 3 16 Device States Changed Handler 1625 29 3 17 D...

Page 29: ...3 DMMPC3 1696 30 3 20 DMM Pin Control 4 DMMPC4 1697 30 3 21 DMM Pin Control 5 DMMPC5 1699 30 3 22 DMM Pin Control 6 DMMPC6 1700 30 3 23 DMM Pin Control 7 DMMPC7 1702 30 3 24 DMM Pin Control 8 DMMPC8 1...

Page 30: ...3 eFuse Controller Testing 1735 32 3 1 eFuse Controller Connections to ESM 1735 32 3 2 Checking for eFuse Errors After Power Up 1735 32 4 eFuse Controller Registers 1738 32 4 1 EFC Boundary Control R...

Page 31: ...pheral Asynchronous Clock Source Register VCLKASRC offset 4Ch 139 2 23 RTI Clock Source Register RCLKSRC offset 50h 140 2 24 Clock Source Valid Status Register CSVSTAT offset 54h 141 2 25 Memory Self...

Page 32: ...Set Register 0 PMPROTSET0 offset 00 186 2 70 Peripheral Memory Protection Set Register 1 PMPROTSET1 offset 04h 186 2 71 Peripheral Memory Protection Clear Register 0 PMPROTCLR0 offset 10h 187 2 72 Per...

Page 33: ...ddress FFFF EB38h 228 4 2 Output Multiplexing Example 229 4 3 Input Multiplexing Example 231 4 4 REVISION_REG Revision Register Address FFFFEA00h 233 4 5 ENDIAN_REG Device Endianness Register Address...

Page 34: ...sable Register FEDACSDIS2 offset C0h 294 5 39 FSM Register Write Enable FSM_WR_ENA offset 288h 295 5 40 FSM Sector Register FSM_SECTOR offset 2A4h 295 5 41 EEPROM Emulation Configuration Register EEPR...

Page 35: ...ster STCTPR offset 08h 350 8 6 STC Current ROM Address Register STC_CADDR offset 0Ch 350 8 7 STC Current Interval Count Register STCCICR offset 10h 351 8 8 Self Test Global Status Register STCGSTAT of...

Page 36: ...R Pin Timing Example 5 413 12 9 ERROR Pin Timing Example 7 414 12 10 ESM Initialization 415 12 11 ESM Enable ERROR Pin Action Response Register 1 ESMEEPAPR1 address FFFF F500h 417 12 12 ESM Disable ER...

Page 37: ...ounter 1 Register RTICPUC1 offset 38h 451 13 24 RTI Capture Free Running Counter 1 Register RTICAFRC1 offset 40h 452 13 25 RTI Capture Up Counter 1 Register RTICAUC1 offset 44h 452 13 26 RTI Compare 0...

Page 38: ...A Signature Low Register PSA_SIGREGL1 offset 60h 502 14 23 Channel 1 PSA Signature High Register PSA_SIGREGH1 offset 64h 502 14 24 Channel 1 CRC Value Low Register CRC_REGL1 offset 68h 502 14 25 Chann...

Page 39: ...ter 1 REQENASET1 offset 34h 533 15 25 Interrupt Enable Set Register 2 REQENASET2 offset 38h 533 15 26 Interrupt Enable Clear Register 0 REQENACLR0 offset 40h 534 15 27 Interrupt Enable Clear Register...

Page 40: ...ffset BCh 577 16 37 HBC Interrupt Mapping Register HBCMAP offset C4h 578 16 38 BTC Interrupt Mapping Register BTCMAP offset CCh 578 16 39 FTC Interrupt Enable Set FTCINTENAS offset DCh 579 16 40 FTC I...

Page 41: ...0 16 83 Channel Control Register CHCTRL offset 10h 610 16 84 Element Index Offset Register EIOFF offset 14h 612 16 85 Frame Index Offset Register FIOFF offset 18h 612 16 86 Current Source Address Regi...

Page 42: ...682 18 13 POM Lock Access Register POMLOCKACCESS address FFA0 4FB0h 683 18 14 POM Lock Status Register POMLOCKSTATUS address FFA0 4FB4h 683 18 15 POM Authentication Status Register POMAUTHSTATUS addr...

Page 43: ...ADG1INTENA offset 2Ch 739 19 33 ADC Group2 Interrupt Enable Control Register ADG2INTENA offset 30h 740 19 34 ADC Event Group Interrupt Flag Register ADEVINTFLG offset 34h 741 19 35 ADC Group1 Interrup...

Page 44: ...EVSAMPDISEN offset 11Ch 774 19 79 ADC Group1 Sample Cap Discharge Control Register ADG1SAMPDISEN offset 120h 775 19 80 ADC Group2 Sample Cap Discharge Control Register ADG2SAMPDISEN offset 124h 776 19...

Page 45: ...Operation 825 20 32 ACNT Period Variation Compensations 826 20 33 N2HET Timings Associated with the Gap Flag ACNT Deceleration 827 20 34 N2HET Timings Associated with the Gap Flag ACNT Acceleration 82...

Page 46: ...ster HETPSL 870 20 81 Parity Control Register HETPCR 871 20 82 Parity Address Register HETPAR 872 20 83 Parity Pin Register HETPPR 873 20 84 Suppression Filter Preload Register HETSFPRLD 874 20 85 Sup...

Page 47: ...r IM REGTOREG Case 00 914 20 127 ADM32 Add and Move Operation for REM REGTOREG Case 01 914 20 128 APCNT Program Field P31 P0 915 20 129 APCNT Control Field C31 C0 915 20 130 APCNT Data Field D31 D0 91...

Page 48: ...1 P0 954 20 178 SCMP Control Field C31 C0 954 20 179 SCMP Data Field D31 D0 954 20 180 SCNT Program Field P31 P0 956 20 181 SCNT Control Field C31 C0 956 20 182 SCNT Data Field D31 D0 956 20 183 SHFT...

Page 49: ...h Mask Register HTU WMR offset 5Ch 1000 21 36 Module Identification Register HTU ID offset 60h 1001 21 37 Parity Control Register HTU PCR offset 64h 1002 21 38 Parity Address Register HTU PAR offset 6...

Page 50: ...AN Interrupt Topology 1 1070 23 13 CAN Interrupt Topology 2 1071 23 14 Local Power Down Mode Flow Diagram 1073 23 15 CAN Core in Silent Mode 1074 23 16 CAN Core in Loop Back Mode 1075 23 17 CAN Core i...

Page 51: ...TB offset 114h 1106 23 62 IF2 Data A Register DCAN IF2DATA offset 130h 1106 23 63 IF2 Data B Register DCAN IF2DATB offset 134h 1106 23 64 IF3 Observation Register DCAN IF3OBS offset 140h 1107 23 65 IF...

Page 52: ...Pin Control Register 6 SPIPC6 offset 2Ch 1165 24 38 SPI Pin Control Register 7 SPIPC7 offset 30h 1167 24 39 SPI Pin Control Register 8 SPIPC8 offset 34h 1168 24 40 SPI Transmit Data Register 0 SPIDAT0...

Page 53: ...bSPI Pins During Master Mode 3 pin Configuration 1224 24 82 SPI MibSPI Pins During Master Mode 4 pin with SPICS Configuation 1224 24 83 SPI MibSPI Pins During Master Mode 4 pin with SPIENA Configurati...

Page 54: ...ffset 40h 1307 25 44 SCI Pin I O Control Register 2 SCIPIO2 offset 44h 1308 25 45 SCI Pin I O Control Register 3 SCIPIO3 offset 48h 1309 25 46 SCI Pin I O Control Register 4 SCIPIO4 offset 4Ch 1310 25...

Page 55: ...offset 90h 1367 26 32 GPIO Functionality 1369 27 1 Multiple I2C Modules Connection Diagram 1372 27 2 Simple I2C Block Diagram 1374 27 3 Clocking Diagram for the I2C Module 1375 27 4 Bit Transfer on th...

Page 56: ...Control Module Revision ID Register REVID 1460 28 16 EMAC Control Module Software Reset Register SOFTRESET 1460 28 17 EMAC Control Module Interrupt Control Register INTCONTROL 1461 28 18 EMAC Control...

Page 57: ...sked Register MACINTSTATMASKED 1501 28 60 MAC Interrupt Mask Set Register MACINTMASKSET 1502 28 61 MAC Interrupt Mask Clear Register MACINTMASKCLEAR 1502 28 62 Receive Multicast Broadcast Promiscuous...

Page 58: ...18 HC Low Speed Threshold Register HCLSTHRESHOLD address FCF78B44h 1549 29 19 HC Root Hub A Register HCRHDESCRIPTORA address FCF78B48h 1549 29 20 HC Root Hub B Register HCRHDESCRIPTORB address FCF78B4...

Page 59: ...Command Routine Setup Stage Control Transfer Request 1620 29 65 Endpoint 0 RX Interrupt Handler 1621 29 66 Prepare for Control Write Status Stage Routine 1622 29 67 Endpoint 0 TX Interrupt Handler 162...

Page 60: ...nation x Blocksize 1 DMMDESTxBL1 offset 30h 40h 50h 60h 1689 30 20 DMM Destination x Region 2 DMMDESTxREG2 offset 34h 44h 54h 64h 1690 30 21 DMM Destination x Blocksize 2 DMMDESTxBL2 offset 38h 48h 58...

Page 61: ...28 31 21 RTP Pin Control 5 Register RTPPC5 offset 48h 1729 31 22 RTP Pin Control 6 Register RTPPC6 offset 4Ch 1730 31 23 RTP Pin Control 7 Register RTPPC7 offset 50h 1732 31 24 RTP Pin Control 8 Regis...

Page 62: ...escriptions 128 2 27 SYS Pin Control Register 9 SYSPC9 Field Descriptions 129 2 28 Clock Source Disable Register CSDIS Field Descriptions 130 2 29 Clock Sources Table 130 2 30 Clock Source Disable Set...

Page 63: ...rupt Vector Register SSIVEC Field Descriptions 174 2 72 System Software Interrupt Flag Register SSIF Field Descriptions 175 2 73 Secondary System Control Registers 176 2 74 PLL Control Register 3 PLLC...

Page 64: ...s 214 3 9 Logic Power Domain PD4 Power Status Register LOGICPDPWRSTAT2 Field Descriptions 215 3 10 Logic Power Domain PD5 Power Status Register LOGICPDPWRSTAT3 Field Descriptions 216 3 11 Memory Power...

Page 65: ...d Descriptions 277 5 25 Flash Bank Sector Enable Register FBSE Field Descriptions 277 5 26 Flash Bank Busy Register FBBUSY Field Descriptions 278 5 27 Flash Bank Access Control Register FBAC Field Des...

Page 66: ...eld Descriptions 328 7 3 Datalogger Register DLR Field Descriptions 329 7 4 PBIST Activate ROM Clock Enable Register PACT Field Descriptions 330 7 5 PBIST ID Register Field Descriptions 331 7 6 Overri...

Page 67: ...odule Registers 416 12 3 ESM Enable ERROR Pin Action Response Register 1 ESMEEPAPR1 Field Descriptions 417 12 4 ESM Disable ERROR Pin Action Response Register 1 ESMDEPAPR1 Field Descriptions 417 12 5...

Page 68: ...mebase Low Compare Register RTITBLCOMP Field Descriptions 457 13 25 RTI Timebase High Compare Register RTITBHCOMP Field Descriptions 457 13 26 RTI Set Interrupt Control Register RTISETINTENA Field Des...

Page 69: ...B CRC_BCTOPLD2 Field Descriptions 506 14 31 Channel 2 PSA Signature Low Register PSA_SIGREGL2 Field Descriptions 507 14 32 Channel 2 PSA Signature High Register PSA_SIGREGH2 Field Descriptions 507 14...

Page 70: ...nment Register 3 DREQASI3 Field Descriptions 574 16 25 Port Assignment Register 0 PAR0 Field Descriptions 575 16 26 Port Assignment Register 1 PAR1 Field Descriptions 576 16 27 FTC Interrupt Mapping R...

Page 71: ...scriptions 607 16 70 DMA Memory Protection Region 3 Start Address Register DMAMPR3S Field Descriptions 608 16 71 DMA Memory Protection Region 3 End Address Register DMAMPR3E Field Descriptions 608 16...

Page 72: ...he EMIF to K4S641632H TC L 70 Interface 667 17 42 AC Characteristics for a Read Access 668 17 43 AC Characteristics for a Write Access 668 18 1 POM Registers 675 18 2 POM Global Control Register POMGL...

Page 73: ...G1INTFLG Field Descriptions 742 19 21 ADC Group2 Interrupt Flag Register ADG2INTFLG Field Descriptions 743 19 22 ADC Event Group Threshold Interrupt Control Register ADEVTHRINTCR Field Descriptions 74...

Page 74: ...fset Register ADMAGINTOFF Field Descriptions 781 19 65 ADC Event Group FIFO Reset Control Register ADEVFIFORESETCR Field Descriptions 782 19 66 ADC Group1 FIFO Reset Control Register ADG1FIFORESETCR F...

Page 75: ...44 Parity Pin Register HETPPR Field Descriptions 873 20 45 Known State on Parity Error 873 20 46 Suppression Filter Preload Register HETSFPRLD Field Descriptions 874 20 47 Suppression Filter Enable Re...

Page 76: ...ODE Encoding Format 959 20 95 SHIFT Condition Encoding 959 20 96 Event Encoding Format for WCAP 962 20 97 Event Encoding Format for WCAPE 964 21 1 CPENA TMBx Priority Rules 973 21 2 Triggered Control...

Page 77: ...ial N2HET Address and Control Register HTU IHADDRCT Field Descriptions 1010 21 46 Initial Transfer Count Register HTU ITCOUNT Field Descriptions 1011 21 47 Current Full Address A Register HTU CFADDRA...

Page 78: ...100 23 22 IF1 IF2 Mask Register Field Descriptions 1102 23 23 IF1 IF2 Arbitration Register Field Descriptions 1103 23 24 IF1 IF2 Message Control Register Field Descriptions 1105 23 25 IF3 Observation...

Page 79: ...TICKCNT Field Descriptions 1195 24 41 Last TG End Pointer LTGPEND Field Descriptions 1196 24 42 TG Control Registers TGxCTRL Field Descriptions 1197 24 43 DMA Channel Control Register DMAxCTRL Field D...

Page 80: ...2 SCIPIO2 Field Descriptions 1308 25 33 SCI Pin I O Control Register 3 SCIPIO3 Field Descriptions 1309 25 34 SCI Pin I O Control Register 4 SCIPIO4 Field Descriptions 1310 25 35 SCI Pin I O Control R...

Page 81: ...32 Input Output Error Enable Register IODFTCTRL Field Descriptions 1367 26 33 Input Buffer Output Buffer and Pull Control Behavior as GPIO Pins 1370 27 1 Ways to Generate a NACK Bit 1379 27 2 Interru...

Page 82: ...it Interrupt Enable Register C0TXEN 1464 28 17 EMAC Control Module Miscellaneous Interrupt Enable Register C0MISCEN 1465 28 18 EMAC Control Module Receive Threshold Interrupt Status Register C0RXTHRES...

Page 83: ...el Enable Register RXMBPENABLE Field Descriptions 1503 28 61 Receive Unicast Enable Set Register RXUNICASTSET Field Descriptions 1505 28 62 Receive Unicast Clear Register RXUNICASTCLEAR Field Descript...

Page 84: ...20 HC Low Speed Threshold Register HCLSTHRESHOLD Bit Field Descriptions 1549 29 21 HC Root Hub A Register HCRHDESCRIPTORA Field Descriptions 1549 29 22 HC Root Hub B Register HCRHDESCRIPTORB Bit Fiel...

Page 85: ...0 12 DMM Interrupt Offset 1 Register DMMOFF1 Field Descriptions 1684 30 13 DMM Interrupt Offset 2 Register DMMOFF1 Field Descriptions 1685 30 14 DMM Direct Data Mode Destination Register DMMDDMDEST Fi...

Page 86: ...er RTPPC1 Field Descriptions 1725 31 18 RTP Pin Control 2 Register RTPPC2 Field Descriptions 1726 31 19 RTP Pin Control 3 Register RTPPC3 Field Descriptions 1727 31 20 RTP Pin Control 4 Register RTPPC...

Page 87: ...e shows a rectangle divided into fields that represent the fields of the register Each field is labeled with its bit name its beginning and ending bit numbers above and its read write properties with...

Page 88: ...al microcontroller product family The product family utilizes a common safety architecture that is implemented in multiple application focused products Community Resources The following links connect...

Page 89: ...cumentation Feedback Copyright 2018 Texas Instruments Incorporated Introduction Chapter 1 SPNU503C March 2018 Introduction Topic Page 1 1 Designed for Safety Applications 90 1 2 Family Description 90...

Page 90: ...or shorts on I O HW self test and diagnostics on the ADC module to check integrity of both analog inputs and the ADC core conversion function A DMA driven hardware engine for the background calculatio...

Page 91: ...ock source inputs to the global clock module GCM The GCM module manages the mapping between the available clock sources and the device clock domains The device also has an external clock prescaler ECP...

Page 92: ...CV USB1 VM USB1 VP USB1 PortPower USB1 SPEED USB1 SUSPEND USB1 TXDAT USB1 TXEN USB1 TXSE0 USB2 OverCurrent USB2 RCV USB2 VM USB2 VP USB2 PortPower USB2 SPEED USB2 SUSPEND USB2 TXDAT USB2 TXEN USB2 TXS...

Page 93: ...C2EDELAY 7 0 Byte 1 0xFFF7F449 Byte 0 0xFFF7F448 32 bit accesses to this register should use the lowest address that is 0xFFF7F448 Writing 0x11223344 to address 0xFFF7F448 shows the following when vie...

Page 94: ...e architecture The second section describes the clocking structure of the microcontrollers The third section gives an overview of the device memory organization The fourth section details exceptions o...

Page 95: ...es www ti com Introduction 95 SPNU503C March 2018 Submit Documentation Feedback Copyright 2018 Texas Instruments Incorporated Architecture 2 1 Introduction The RM48x family of microcontrollers is base...

Page 96: ...Electrically programmable fuses eFuses are used to configure the device after Fuse controller deassertion of PORRST The eFuse values are read and loaded into internal registers as part of the power o...

Page 97: ...ly enable or disable the clock for each peripheral individually The PCR also manages the accesses to the system module registers required to configure the device s clocks interrupts and so on The syst...

Page 98: ...U Accesses to CPU Flash and RAM CRC Module EMAC EMIF and USB Slaves PCR Modules CPU Read 0 User Privilege Allowed Allowed Allowed Allowed Allowed CPU Write 1 User Privilege Not allowed Allowed Allowed...

Page 99: ...t 2018 Texas Instruments Incorporated Architecture 2 2 Memory Organization 2 2 1 Memory Map Overview The Cortex R4F CPU uses a 32 bit address bus giving it access to a memory space of 4GB This space i...

Page 100: ...0BFF_FFFF 64MB 256KB Mirrored Flash Flash mirror frame 0x2000_0000 0x20FF_FFFF 16MB 3MB External Memory Accesses EMIF Chip Select 2 asynchronous EMIF select 2 0x6000_0000 0x63FF_FFFF 64MB 16MB Access...

Page 101: ...256B 256B Abort Cyclic Redundancy Checker CRC Module Register Frame CRC CRC frame 0xFE00_0000 0xFEFF_FFFF 16MB 512B Accesses above 0x200 generate abort Peripheral Memories MIBSPI5 RAM PCS 5 0xFF0A_000...

Page 102: ...CSCS1 0xFFA0_1000 0xFFA0_1FFF 4KB 4KB Reads return zeros writes have no effect ETM R4 CSCS2 0xFFA0_2000 0xFFA0_2FFF 4KB 4KB Reads return zeros writes have no effect CoreSight TPIU CSCS3 0xFFA0_3000 0x...

Page 103: ...0 0xFFF8_3FFF 4KB 4KB Abort Flash Wrapper PPCS7 0xFFF8_7000 0xFFF8_7FFF 4KB 4KB Abort eFuse Farm Controller PPCS12 0xFFF8_C000 0xFFF8_CFFF 4KB 4KB Abort Power Management Module PMM PPSE0 0xFFFF_0000 0...

Page 104: ...ash bank for use as emulated EEPROM 2 2 3 1 Flash Bank Sectoring Configuration Each bank is divided into multiple sectors A flash sector is the smallest region in the flash bank that must be erased Th...

Page 105: ...to the EEPROM emulation flash bank bank 7 are protected by dedicated SECDED logic inside the digital interface to the flash banks Both the SECDED logic implementations use Error Correction Codes ECC f...

Page 106: ...d before these modules are used for safety critical functions These microcontrollers support a Programmable Built In Self Test PBIST mechanism that is used to test each on chip SRAM module for faults...

Page 107: ...15 18 19 20 23 24 26 0x02CE7FDC 4 0x00000008 march13n Single port 0x00000000 0x96699669 0x0F0F0F0F 0xAA55AA55 0xC3C3C3C3 6 21 22 25 27 28 0x0D300020 5 0x00000010 down1A_red Dual port 0xFFFFFFFF 0xAAAA...

Page 108: ...dq Dual port 0xFFFFFFFF 3 4 5 7 8 9 10 11 12 13 14 15 18 19 20 23 24 26 0x02CE7FDC 24 0x00800000 iddq Single port 0xFFFFFFFF 6 21 22 25 27 28 0x0D300020 25 0x01000000 retention Dual port 0xFFFFFFFF 3...

Page 109: ...s of the CPU data RAM after power on reset is unknown A hardware auto initialization can be started to that there is no ECC error NOTE Effect of ECC or Parity on Memory Auto Initialization The ECC or...

Page 110: ...ers before starting auto initialization on their respective RAMs Table 2 7 Memory Initialization Select Mapping 1 2 Memory Address Range MSINENA Register Bit Start End RAM 0x08000000 0x08013FFF 0 RAM...

Page 111: ...eset is also flagged by the PORST bit in the SYSESR register SYSESR 15 Note The voltage monitor is not an alternative for an external voltage supervisor Driving nRST pin low externally Warm reset This...

Page 112: ...olds the data until the memory system has sufficient bandwidth to perform the write access This gives read accesses higher priority The write data can be held in the buffer for a long period during wh...

Page 113: ...ames If the CPU attempts to write to a peripheral register for which it does not have the correct permissions a protection violation is detected and an Abort occurs Some modules also enforce register...

Page 114: ...cy output of the internal reference oscillator This is typically a 10 MHz signal CLK10M that is used by the clock monitor module as a reference clock to monitor the main oscillator frequency 6 PLL2 Th...

Page 115: ...e with HCLK Is disabled separately from HCLK via the CDDISx registers bit 0 Can be divided by 1 up to 8 when running CPU selftest LBIST using the CLKDIV field of the STCCLKDIV register at address 0xFF...

Page 116: ...ess 0xFFFFE140 Frequency can be VCLKA3 1 VCLKA3 2 or VCLKA3 8 Default frequency is VCLKA3 2 and needs to be changed to VCLKA3 4 to generate the 12MHz clock from the 48MHz VCLKA3 clock Is disabled sepa...

Page 117: ...efault source for the domain is VCLK Selecting clock source for VCLKA3 domain The clock source for VCLKA3 domain is selected via the VCLKACON1 register The default source for the VCLKA3 domain is VCLK...

Page 118: ...d AGP parameter configured for the banks See Chapter 5 for more details 2 Disable the clock sources that are not required to be kept active A clock source does not get disabled until all clock domains...

Page 119: ...lso be brought out on to the NHET1 12 terminal in this clock test mode The clock test mode is controlled by the CLKTEST register in the system module register frame Figure 2 4 Clock Test Register CLKT...

Page 120: ...nt and follows the ETM v3 specification For more details on the ETM R4 specification refer to the Embedded Trace Macrocell Architecture Specification The ETM clock source is selected as either VCLK or...

Page 121: ...ference clock The device also includes optional filters that can be enabled before a slip indication from the PLL is actually logged in the system module Global Status Register GLBSTAT Also once a PLL...

Page 122: ...values Any value N2HET1 31 As can be seen the main oscillator OSCIN can be used for counter 0 as a known good reference clock The clock for counter 1 can be selected from among 8 options See Chapter 1...

Page 123: ...k Source Disable Set Register Section 2 5 1 11 38h CSDISCLR Clock Source Disable Clear Register Section 2 5 1 12 3Ch CDDIS Clock Domain Disable Register Section 2 5 1 13 40h CDDISSET Clock Domain Disa...

Page 124: ...ter Section 2 5 1 40 C0h RAMGCR RAM Control Register Section 2 5 1 41 C4h BMMCR1 Bus Matrix Module Control Register 1 Section 2 5 1 42 C8h Reserved Reserved CCh CPURSTCR CPU Reset Control Register Sec...

Page 125: ...tput Note Proper ECLK duty cycle is not assured until 1 ECLK cycle has elapsed after switching into functional mode 2 5 1 2 SYS Pin Control Register 2 SYSPC2 The SYSPC2 register shown in Figure 2 7 an...

Page 126: ...SPC4 The SYSPC4 register shown in Figure 2 9 and described in Table 2 22 controls the logic level output function of the ECLK pin when when it is configured as an output in GIO mode Figure 2 9 SYS Pin...

Page 127: ...pin is placed into GIO mode by setting the ECPCLKFUN bit to 0 in the SYSPC1 register The ECLK pin is placed in output mode by setting the ECPCLKDIR bit to 1 in the SYSPC2 register 2 5 1 6 SYS Pin Con...

Page 128: ...riven low ECPCLKDOUT 1 The ECLK output buffer is tristated Note The ECLK pin is placed into GIO mode by setting the ECPCLKFUN bit to 0 in the SYSPC1 register 2 5 1 8 SYS Pin Control Register 8 SYSPC8...

Page 129: ...set Table 2 27 SYS Pin Control Register 9 SYSPC9 Field Descriptions Bit Field Value Description 31 1 Reserved 0 Reads return 0 Writes have no effect 0 ECPCLKPS ECLK pull up pull down select This bit i...

Page 130: ...sable Register CSDIS Field Descriptions Bit Field Value Description 31 8 Reserved 0 Reads return 0 Writes have no effect 7 3 CLKSR 7 3 OFF Clock source 7 3 off 0 Clock source 7 3 is enabled 1 Clock so...

Page 131: ...e no effect 7 3 SETCLKSR 7 3 OFF Set clock source 7 3 to the disabled state 0 Read Clock source 7 3 is enabled Write Clock source 7 3 is unchanged 1 Read Clock source 7 3 is disabled Write Clock sourc...

Page 132: ...ads return 0 Writes have no effect 7 3 CLRCLKSR 7 3 OFF Enables clock source 7 3 0 Read Clock source 7 3 is enabled Write Clock source 7 3 is unchanged 1 Read Clock source 7 3 is enabled Write Clock s...

Page 133: ...VCLK3OFF R 0 R WP 0 R WP 0 R WP 0 R WP 0 7 6 5 4 3 2 1 0 Reserved RTICLK1OFF Reserved VCLKA1OFF VCLK2OFF VCLKPOFF HCLKOFF GCLKOFF R WP 0 R WP 0 R WP 0 R WP 0 R WP 0 R WP 0 R WP 0 R WP 0 LEGEND R W Rea...

Page 134: ...orporated Architecture Table 2 32 Clock Domain Disable Register CDDIS Field Descriptions continued Bit Field Value Description 1 HCLKOFF HCLK and VCLK_sys domains off 0 The HCLK and VCLK_sys domains a...

Page 135: ...VCLKA 4 3 domain 0 Read The VCLKA 4 3 domain is enabled Write The VCLKA 4 3 domain is unchanged 1 Read The VCLKA 4 3 domain is disabled Write The VCLKA 4 3 domain is set to the enabled state 9 Reserve...

Page 136: ...et to the enabled state 2 5 1 15 Clock Domain Disable Clear Register CDDISCLR The CDDISCLR register shown in Figure 2 20 and described in Table 2 34 clears clock domains to the enabled state Figure 2...

Page 137: ...KA1 domain 0 Read The VCLKA1 domain is enabled Write The VCLKA1 domain is unchanged 1 Read The VCLKA1 domain is disabled Write The VCLKA1 domain is cleared to the enabled state 3 CLRVCLK2OFF Clear VCL...

Page 138: ...e6 is the source for GCLK HCLK VCLK VCLK2 on wakeup 7h Clock source7 is the source for GCLK HCLK VCLK VCLK2 on wakeup 8h Fh Reserved 23 20 Reserved 0 Reads return 0 Writes have no effect 19 16 HVLPM H...

Page 139: ...rivileged mode only n value after reset Table 2 36 Peripheral Asynchronous Clock Source Register VCLKASRC Field Descriptions Bit Field Value Description 31 4 Reserved 0 Reads return 0 Writes have no e...

Page 140: ...Read only WP Write in privileged mode only n value after reset Table 2 37 RTI Clock Source Register RCLKSRC Field Descriptions Bit Field Value Description 31 26 Reserved 0 Reads return 0 Writes have...

Page 141: ...lock Source Valid Register CSVSTAT Field Descriptions Bit Field Value Description 31 8 Reserved 0 Reads return 0 Writes have no effect 7 3 CLKSR 7 3 V Clock source 7 3 valid 0 Clock source 7 3 is not...

Page 142: ...Reserved 0 Reads return 0 Writes have no effect 9 8 ROM_DIV Prescaler divider bits for ROM clock source 0 ROM clock source is HCLK divided by 1 PBIST will reset for 16 VBUS cycles 1h ROM clock source...

Page 143: ...0 Reserved MINITGENA R 0 R WP 5h LEGEND R W Read Write R Read only WP Write in privileged mode only n value after reset Table 2 40 Memory Hardware Initialization Global Control Register MINITGCR Field...

Page 144: ...de all the corresponding bits of the memories to be tested should be set before enabling the global memory self test controller key MSTGENA in the MSTGCR register offset 58h The reason for this is tha...

Page 145: ...ions Bit Field Value Description 31 9 Reserved 0 Reads return 0 Writes have no effect 8 MINIDONE Memory hardware initialization complete status Note Disabling the MINITGENA key by writing from Ah to a...

Page 146: ...tialization status bit 0 Read Memory module 31 0 hardware initialization is not completed Write A write of 0 has no effect 1 Read Memory module 31 0 hardware initialization is completed Write The bit...

Page 147: ...evice clock Note If ROS Bit 31 is set to 1 the device will be reset if a PLL Slip and the PLL will be bypassed after the reset occurs 28 24 PLLDIV PLL Output Clock Divider R PLLDIV 1 f PLL CLK f post_...

Page 148: ...DINGRATE NS SPREADINGRATE 1 f mod f s f INT CLK 2 NS 0 f mod f s f INT CLK 2 1 1h f mod f s f INT CLK 2 2 1FFh f mod f s f INT CLK 2 512 21 Reserved 0 Value has no effect on PLL operation 20 12 MULMOD...

Page 149: ...e 2 32 SYS Pin Control Register 10 SYSPC10 offset 78h 31 16 Reserved R 0 15 1 0 Reserved ECPCLK_SLEW R 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 2 46 SYS Pin Control Register...

Page 150: ...the device 11 0 X WAFER COORDINATE These read only bits contain the X wafer coordinate of the device NOTE Die Identification Information The die identification information will vary from unit to unit...

Page 151: ...15 13 12 8 7 5 4 0 Reserved HFTRIM Reserved LFTRIM R 0 R WP 10h R 0 R WP 10h LEGEND R W Read Write R Read only WP Write in privileged mode only n value after reset Table 2 49 LPO Clock Monitor Control...

Page 152: ...Caution This value should only be changed when the HF oscillator is not the source for a clock domain otherwise a system failure could result The following values are the ratio f fo in the F021 proce...

Page 153: ...LF oscillator s frequency Caution This value should only be changed when the LF oscillator is not the source for a clock domain otherwise a system failure could result The following values are the ra...

Page 154: ...onitor phase frequency detect PFD 0 The 10 MHz LPO fast clock is the compare clock for the clock detect PFD circuit and the source to limp clock on a clock fail 1 The ALTLIMPCLOCK driven on the GIOB 0...

Page 155: ...id status 7h Reserved 8h Low frequency LPO Low Power Oscillator clock valid status 9h Fh Reserved 7 4 Reserved 0 Reads return 0 Writes have no effect 3 0 SEL_ECP_PIN ECLK pin clock source select Note...

Page 156: ...1 configured in fast mode DFTWRITE 0 1 and DFTREAD 0 1 configured in slow mode DFTWRITE 1 0 and DFTREAD 1 0 configured in slow mode DFTWRITE 0 1 and DFTREAD 0 1 configured in screen mode DFTWRITE 1 1...

Page 157: ...TEST_MODE_KEY R WP 0 R WP 5h LEGEND R W Read Write R Read only WP Write in privileged mode only n value after reset Table 2 52 DFT Control Register 2 DFTCTRLREG2 Field Descriptions Bit Field Value De...

Page 158: ...OUNT FBSLIP down counter programmed value Configures the system response when a FBSLIP is indicated by the PLL macro When PLL1_FBSLIP_FILTER_KEY is not Ah the down counter counts from the programmed v...

Page 159: ...ignals bit 0 controls MiBSPI1 bit 1 controls SPI2 bit 2 controls MiBSPI3 bit 3 controls SPI4 bit 4 controls MiBSPI5 bit 5 Reserved bit 6 controls EMIF bit 7 controls ETM bit 8 controls signal TMS bit...

Page 160: ...bort was generated writing into the EMIF Notes This bit is only updated when an imprecise abort occurs This bit is cleared to 0 only on power on reset The value of this register remains unchanged afte...

Page 161: ...nce ATYPE is set the IMPFAWADD and IMPFASTS bits are not updated by subsequent ABORT signals NOTE The DMA DMM and the peripheral master port will also generate an imprecise abort to the CPU when writi...

Page 162: ...not be written into unless the write data into the SSKEY1 field matches the key 75h therefore byte writes cannot be performed on the SSDATA1 field NOTE This register is mirrored at offset FCh for comp...

Page 163: ...rrupt routine The SSDATA3 field cannot be written into unless the write data into the SSKEY3 field matches the key 93h therefore byte writes cannot be performed on the SSDATA3 field 2 5 1 40 System So...

Page 164: ...ontrol Register RAMGCR Field Descriptions Bit Field Value Description 31 20 Reserved 0 Reads return 0 Writes have no effect 19 16 RAM_DFT_EN Functional mode RAM DFT Design For Test port enable key Not...

Page 165: ...Read only WP Write in privileged mode only n value after reset Table 2 61 Bus Matrix Module Control Register 1 BMMCR Field Descriptions Bit Field Value Description 31 4 Reserved 0 Reads return 0 Writ...

Page 166: ...ad and written as a single bit is actually a multi bit key with error correction capability As such single bit flips within the key can be corrected allowing protection of the system as a whole An err...

Page 167: ...NA Reserved R 0 R WP 0 R 0 LEGEND R W Read Write R Read only WP Write in privileged mode only n value after reset Table 2 63 Clock Control Register CLKCNTL Field Descriptions Bit Field Value Descripti...

Page 168: ...Field Value Description 31 25 Reserved 0 Reads return 0 Writes have no effect 24 ECPSSEL This bit allows the selection between VCLK and OSCIN as the clock source for ECLK Note Other ECLK clock sources...

Page 169: ...vice parity is odd 2 5 1 47 System Exception Control Register SYSECR The SYSECR register shown in Figure 2 52 and described in Table 2 66 is used to generate a software reset NOTE The register bits in...

Page 170: ...as caused by a power on reset This bit should be cleared after being read so that subsequent resets can be properly identified as not being power on resets 14 OSCRST Reset caused by an oscillator fail...

Page 171: ...r SYSTASR Field Descriptions Bit Field Value Description 31 5 Reserved 0 Reads return 0 Writes have no effect 4 0 EFUSE_Abort Test Abort status flag These bits are set when test abort occurred 0 Read...

Page 172: ...er GLBSTAT Field Descriptions Bit Field Value Description 31 10 Reserved 0 Reads return 0 Writes have no effect 9 FBSLIP PLL over cycle slip detection cleared by nPORRST maintains its previous value f...

Page 173: ...que by device configuration 16 13 TECH These bits define the process technology by which the device was manufactured 0 Device manufactured in the C05 process technology 1h Device manufactured in the F...

Page 174: ...key value of the source for the system software interrupt which is indicated by the vector in the SSIVEC 7 0 field 7 0 SSIVECT These bits contain the source for the system software interrupt Note A r...

Page 175: ...R WC 0 R WC 0 R WC 0 R WC 0 LEGEND R W Read Write R Read only C Clear n value after reset Table 2 72 System Software Interrupt Flag Register SSIF Field Descriptions Bit Field Value Description 31 4 R...

Page 176: ...5 2 1 04h Reserved Reserved 08h STCCLKDIV CPU Logic BIST Clock Divider Section 2 5 2 2 0Ch 20h Reserved Reserved 24h ECPCNTL ECP Control Register Section 2 5 1 45 28h 38h Reserved Reserved 3Ch CLK2CN...

Page 177: ...ut_CLK2 OD2 0 fpost_ODCLK2 foutput_CLK2 1 1h fpost_ODCLK2 foutput_CLK2 2 7h fpost_ODCLK2 foutput_CLK2 8 Note PLL output clock is gated off if ODPLL2 is changed while the PLL2 is active 28 24 PLLDIV2 P...

Page 178: ...effect 26 24 CLKDIV 0 Clock divider prescaler for CPU clock during logic BIST 23 0 Reserved 0 Reads return 0 Writes have no effect 2 5 2 3 Clock 2 Control Register CLK2CNTRL This register is shown in...

Page 179: ...ter and VCLKA4_DIV_CDDIS bit It can be inferred that VCLKA4_DIV clock is disabled when VCLKA4 clock is disabled 0 The ratio is VCLKA4 divided by 1 7h The ratio is VCLKA4 divided by 8 23 21 Reserved 0...

Page 180: ...VCLKA3 domain will be enabled by writing to the CDDIS register 0 Enable the prescaled VCLKA3 clock on VCLKA3_DIVR 1 Disable the prescaled VCLKA3 clock on VCLKA3_DIVR 3 0 VCLKA3S Peripheral asynchrono...

Page 181: ...ER_COUNT PLL RFSLIP down counter programmed value Count is on 10M clock On reset counter value is 0 Counter must be programmed to a non zero value and enabled for the filtering to be enabled 0 Filteri...

Page 182: ...rs Writing of instructions Program ProgramCRA RunAutoload and LoadFuseScanchain in EFC registers is blocked 2 5 2 7 Die Identification Register Lower Word DIEIDL_REG0 The DIEIDL_REG0 is a duplicate of...

Page 183: ...ield Description 31 24 Reserved Reserved for TI use Writes have no effect 23 0 LOT This read only register contains the device lot number NOTE Die Identification Information The die identification inf...

Page 184: ...68 and described in Table 2 83 Figure 2 68 Die Identification Register Upper Word DIEIDH_REG3 offset FCh 31 0 DIEIDH2 R X LEGEND R Read only n value after reset X value is unchanged after reset Table...

Page 185: ...7 2Ch PPROTSET3 Peripheral Protection Set Register 3 Section 2 5 3 8 30h 3Ch Reserved Reserved 40h PPROTCLR0 Peripheral Protection Clear Register 0 Section 2 5 3 9 44h PPROTCLR1 Peripheral Protection...

Page 186: ...framen can be written to only in privileged mode but it can be read in both user and privileged modes Write The corresponding bit in PMPROTSET0 and PMPROTCLR0 registers is set to 1 2 5 3 2 Peripheral...

Page 187: ...en can be written to only in privileged mode but it can be read in both user and privileged modes Write The corresponding bit in PMPROTSET0 and PMPROTCLR0 registers is cleared to 0 2 5 3 4 Peripheral...

Page 188: ...The slave uses only one quadrant In this case the bit as specified in Table 2 89 protects the slave The above arrangement is true for all the peripheral select PS0 to PS31 presented in Section 2 5 3 6...

Page 189: ...quadrant can be written to only in privileged mode but it can be read in both user and privileged modes Write The corresponding bit in PPROTSET1 and PPROTCLR1 registers is set to 1 2 5 3 7 Peripheral...

Page 190: ...adrant can be written to only in privileged mode but it can be read in both user and privileged modes Write The corresponding bit in PPROTSET3 and PPROTCLR3 registers is set to 1 2 5 3 9 Peripheral Pr...

Page 191: ...rant can be written to only in privileged mode but it can be read in both user and privileged modes Write The corresponding bit in PPROTSET1 and PPROTCLR1 registers is cleared to 0 2 5 3 11 Peripheral...

Page 192: ...and reads are 0 Figure 2 80 Peripheral Protection Clear Register 3 PPROTCLR3 offset 4Ch 31 0 PS 31 24 QUAD 3 0 PROTCLR R WP 0 LEGEND R W Read Write WP Write in privileged mode only n value after reset...

Page 193: ...clock power down set 0 Read The peripheral memory clock 31 0 is active Write The bit is unchanged 1 Read The peripheral memory clock 31 0 is inactive Write The corresponding bit in the PCSPWRDWNSET0...

Page 194: ...active Write The bit is unchanged 1 Read The peripheral memory clock 31 0 is inactive Write The corresponding bit in the PCSPWRDWNSET0 and PCSPWRDWNCLR0 registers is cleared to 0 2 5 3 16 Peripheral...

Page 195: ...in a frame are identical to what is described under PPROTSET0 Section 2 5 3 5 This arrangement is the same for bits of PS8 to PS31 presented in Section 2 5 3 18 Section 2 5 3 24 This register holds bi...

Page 196: ...active Write The bit is unchanged 1 Read The clock to the peripheral select quadrant is inactive Write The corresponding bit in PSPWRDWNSET1 and PSPWRDWNCLR1 registers is set to 1 2 5 3 19 Peripheral...

Page 197: ...ctive Write The bit is unchanged 1 Read The clock to the peripheral select quadrant is inactive Write The corresponding bit in PSPWRDWNSET3 and PSPWRDWNCLR3 registers is set to 1 2 5 3 21 Peripheral P...

Page 198: ...ive Write The bit is unchanged 1 Read The clock to the peripheral select quadrant is inactive Write The corresponding bit in PSPWRDWNSET1 and PSPWRDWNCLR1 registers is cleared to 0 2 5 3 23 Peripheral...

Page 199: ...ed Writes to nonimplemented bits have no effect and reads are 0 Figure 2 92 Peripheral Power Down Clear Register 3 PSPWRDWNCLR offset ACh 31 0 PS 31 24 QUAD 3 0 PWRDWNCLR R WP 1 LEGEND R W Read Write...

Page 200: ...8 Texas Instruments Incorporated Power Management Module PMM Chapter 3 SPNU503C March 2018 Power Management Module PMM This chapter describes the power management module PMM Topic Page 3 1 Overview 20...

Page 201: ...rrent for a core domain that has modules that are not being used by the application This chapter describes the Power Management Module PMM The PMM provides memory mapped registers that control the sta...

Page 202: ...er This device has 8 separate core power domains PD1 is an always ON domain and is not controlled by PMM It contains the CPU as well as other principal modules and the interconnect required for operat...

Page 203: ...USB1 VM USB1 VP USB1 PortPower USB1 SPEED USB1 SUSPEND USB1 TXDAT USB1 TXEN USB1 TXSE0 USB2 OverCurrent USB2 RCV USB2 VM USB2 VP USB2 PortPower USB2 SPEED USB2 SUSPEND USB2 TXDAT USB2 TXEN USB2 TXSE0...

Page 204: ...for PD1 This is also controlled by programmation of individual bits within the reset configuration word in the TI OTP sector of flash bank 0 3 3 5 Changing Power Domain State A domain can only change...

Page 205: ...er domain to ensure that all logic begins in its default reset state PMM generates nPORRST power on reset nRST system reset nPRST peripheral reset and nTRST test debug logic reset for each domain 3 3...

Page 206: ...c compare block s primary input port and the same input is also applied to the secondary input port but with one bit flipped starting from bit position 0 The unequal vectors should cause the PSCON dia...

Page 207: ...ved 40h LOGICPDPWRSTAT0 Logic Power Domain PD2 Power Status Register Section 3 4 6 44h LOGICPDPWRSTAT1 Logic Power Domain PD3 Power Status Register Section 3 4 7 48h LOGICPDPWRSTAT2 Logic Power Domain...

Page 208: ...9h Reserved Any other value Read Power domain PD2 is in Active state Write Power domain PD2 is commanded to switch to Active state 23 20 Reserved 0 Read returns 0 Writes have no effect 19 16 LOGICPDON...

Page 209: ...ivileged Mode only Ah Read Power domain RAM_PD1 is in OFF state Write Power domain RAM_PD1 is commanded to switch to OFF state 9h Reserved Any other value Read Power domain RAM_PD1 is in Active state...

Page 210: ...ns Bit Field Value Description 31 4 Reserved 0 Read returns 0 Writes have no effect 3 PDCLK_DIS 3 Read in User and Privileged Mode returns the current value of PDCLK_DIS 3 Write in Privileged Mode onl...

Page 211: ...Value Description 31 4 Reserved 0 Read returns 0 Writes have no effect 3 PDCLK_DISSET 3 Read in User and Privileged Mode returns the current value of PDCLK_DISSET 3 Write in Privileged Mode only 0 No...

Page 212: ...Bit Field Value Description 31 4 Reserved 0 Read returns 0 Writes have no effect 3 PDCLK_DISCLR 3 Read in User and Privileged Mode returns the current value of PDCLK_DIS 3 Write in Privileged Mode on...

Page 213: ...returns 0 Writes have no effect 24 LOGIC IN TRANS0 Logic in transition status for power domain PD2 Read in User and Privileged Mode 0 Logic in power domain PD2 is in the steady Active or OFF state 1 L...

Page 214: ...returns 0 Writes have no effect 24 LOGIC IN TRANS1 Logic in transition status for power domain PD3 Read in User and Privileged Mode 0 Logic in power domain PD3 is in the steady Active or OFF state 1 L...

Page 215: ...returns 0 Writes have no effect 24 LOGIC IN TRANS2 Logic in transition status for power domain PD4 Read in User and Privileged Mode 0 Logic in power domain PD4 is in the steady Active or OFF state 1...

Page 216: ...returns 0 Writes have no effect 24 LOGIC IN TRANS3 Logic in transition status for power domain PD5 Read in User and Privileged Mode 0 Logic in power domain PD5 is in the steady Active or OFF state 1...

Page 217: ...AM_PD1 This power domain only contains SRAM macros However an SRAM macro also has some digital logic controlled by the PSCON Therefore a memory power domain also contains a logic status indicator Read...

Page 218: ...AM_PD2 This power domain only contains SRAM macros However an SRAM macro also has some digital logic controlled by the PSCON Therefore a memory power domain also contains a logic status indicator Read...

Page 219: ...AM_PD3 This power domain only contains SRAM macros However an SRAM macro also has some digital logic controlled by the PSCON Therefore a memory power domain also contains a logic status indicator Read...

Page 220: ...scription 31 9 Reserved 0 Read returns 0 Writes have no effect 8 PMCTRL PWRDN PMC PSCON Power Down Read in User and Privileged Mode returns current value of PMCTRL PWRDN Write in Privileged mode only...

Page 221: ...te transition control sequence for logic and or SRAM 1 PMC and PSCONs for all power domains have completed generating power state transition control sequence triggered by PMC input control signals 3 4...

Page 222: ...atus Register 1 LPDDCSTAT1 Field Descriptions Bit Field Value Description 31 20 Reserved 0 Read returns 0 Writes have no effect 19 16 LCMPE 3 0 Logic Power Domain Compare Error Each of these bits corr...

Page 223: ...Diagnostic Compare Status Register 2 LPDDCSTAT2 Field Descriptions Bit Field Value Description 31 20 Reserved 0 Read returns 0 Writes have no effect 19 16 LSTET 3 0 Logic Power Domain Self test Error...

Page 224: ...emory PD PSCON Diagnostic Compare Status Register 1 MPDDCSTAT1 Field Descriptions Bit Field Value Description 31 19 Reserved 0 Read returns 0 Writes have no effect 18 16 MCMPE 2 0 Memory Power Domain...

Page 225: ...Compare Status Register 2 MPDDCSTAT2 Field Descriptions Bit Field Value Description 31 19 Reserved 0 Read returns 0 Writes have no effect 18 16 MSTET 2 0 Memory Power Domain Self test Error Type Each...

Page 226: ...iagnostic register to make sure that a domain that has been commanded to turn off has actually received the command Figure 3 22 Isolation Diagnostic Status Register ISODIAGSTAT offset C0h 31 8 Reserve...

Page 227: ...ter 4 SPNU503C March 2018 I O Multiplexing and Control Module IOMM This chapter describes the I O Multiplexing and Control Module IOMM Topic Page 4 1 Overview 228 4 2 Main Features of I O Multiplexing...

Page 228: ...ddress FFFF EB38h 31 26 25 24 Reserved EMIF DATA 2 ETM DATA 18 RWP 0 R WP 0 R WP 1 23 18 17 16 Reserved RTP DATA 15 EMIF nCS 0 RWP 0 R WP 0 R WP 1 15 10 9 8 Reserved EMIF DATA 3 ETM DATA 19 RWP 0 R WP...

Page 229: ...the N15 ball This terminal uses an 8mA low EMI output buffer Figure 4 2 Output Multiplexing Example Notes on Figure 4 2 ETM_DATA 19 is an output only signal Therefore the GZ is tied to zero when the E...

Page 230: ...cated Input Ball 337BGA Multiplexed Input Ball Control Register Bit A Control Register Bit B SPI4SIMO W5 PINMMR5 9 PINMMR23 16 SPI4SOMI V6 PINMMR5 17 PINMMR23 24 SPI4CLK K18 PINMMR5 1 PINMMR23 8 SPI4N...

Page 231: ...en the PINMMR29 24 must be cleared ADC Trigger Control The microcontrollers contain two Analog to Digital Converter ADC modules The ADC conversions can be started using a rising or falling or both edg...

Page 232: ...er followed by a write of 0x95a4f1e0 to the kick1 register Disabling Write Access to the IOMM Registers It is recommended to disable write access to the IOMM registers once the I O multiplexing config...

Page 233: ...gnaling Enable Clear Register Section 4 5 8 F4h FAULT_ADDRESS_REG Fault Address Register Section 4 5 9 F8h FAULT_STATUS_REG Fault Status Register Section 4 5 10 FCh FAULT_CLEAR_REG Fault Clear Registe...

Page 234: ...ess Figure 4 5 ENDIAN_REG Device Endianness Register Address FFFFEA20h 31 16 Reserved R 0 15 1 0 Reserved ENDIAN R 0 R D LEGEND R W Read Write R Read only n value after reset R D Value read is determi...

Page 235: ...Field Value Description 31 0 KICK0 0 Kicker 0 Register The value 83E7 0B13h must be written to KICK0 as part of the process to unlock the CPU write access to the PINMMRnn registers 4 5 4 KICK_REG1 Kic...

Page 236: ...n mechanism Figure 4 8 ERR_RAW_STATUS_REG Error Raw Status Set Register Address FFFFEAE0h 31 8 Reserved R 0 7 2 1 0 Reserved ADDR_ERR PROT_ERR R 0 R WP 0 R WP 0 LEGEND R W Read Write R Read only WP Wr...

Page 237: ...END R W Read Write R Read only WP Write in privileged mode only n value after reset Table 4 9 Error Signaling Enabled Status Clear Register Field Descriptions Bit Field Value Description 31 2 Reserved...

Page 238: ...WP 0 LEGEND R W Read Write R Read only WP Write in privileged mode only n value after reset Table 4 10 Error Enable Register Field Descriptions Bit Field Value Description 31 2 Reserved 0 Read returns...

Page 239: ...ble Clear 0 Read Addressing Error signaling is disabled Write Writing 0 has no effect 1 Read Addressing Error signaling is enabled Write Addressing Error signaling is disabled 0 PROT_ERR_EN_CLR Protec...

Page 240: ...PE R 0 R 0 R 0 R 0 R 0 R 0 LEGEND R W Read Write R Read only C Clear n value after reset Table 4 13 Fault Status Register Field Descriptions Bit Field Value Description 31 28 Reserved 0 Reads return z...

Page 241: ...lexing Control Registers These registers control the multiplexing of the functionality available on each pad There are 31 such registers PINMMR0 through PINMMR31 Each 8 bit field of a PINMMR register...

Page 242: ...PINMMR2 26 RESERVED PINMMR2 27 RESERVED PINMMR2 28 FFFF EB1Ch ETMDATA 23 PINMMR3 0 EMIF_DATA 7 PINMMR3 1 RESERVED PINMMR3 2 RESERVED PINMMR3 3 RESERVED PINMMR3 4 N2HET1 22 PINMMR3 8 USB2 TXSE0 PINMMR...

Page 243: ...PINMMR11 26 RMII_RXD 0 PINMMR11 27 RESERVED PINMMR11 28 FFFF EB40h N2HET1 26 PINMMR12 0 MII_RXD 1 PINMMR12 1 RMII_RXD 1 PINMMR12 2 RESERVED PINMMR12 3 RESERVED PINMMR12 4 ETMDATA 16 PINMMR12 8 EMIF_D...

Page 244: ...0 20 EMIF_ADDR 11 PINMMR20 24 RTP_DATA 8 PINMMR20 25 RESERVED PINMMR20 26 RESERVED PINMMR20 27 RESERVED PINMMR20 28 FFFF EB64h EMIF_ADDR 1 PINMMR21 0 N2HET2 3 PINMMR21 1 RESERVED PINMMR21 2 RESERVED P...

Page 245: ...MO 2 PINMMR27 24 DMM_DATA 10 PINMMR27 25 RESERVED PINMMR27 26 RESERVED PINMMR27 27 RESERVED PINMMR27 28 FFFF EB80h MIBSPI5SIMO 3 PINMMR28 0 DMM_DATA 11 PINMMR28 1 RESERVED PINMMR28 2 RESERVED PINMMR28...

Page 246: ...ble read only memory module is a type of nonvolatile memory that has fast read access times and is able to be reprogrammed in the field or in the application This chapter describes the F021 Flash modu...

Page 247: ...r the actual size of the Flash memory for the device see the device specific data sheet 5 1 2 Definition of Terms Terms used in this document have the following meaning ATCM Port A tightly coupled mem...

Page 248: ...Margin 1 mode More stringent read mode designed for early detection of marginally erased bits Read Margin 0 mode More stringent read mode designed for early detection of marginally programmed bits 5 1...

Page 249: ...all of the ATCM program memory space Flash banks 0 through 6 must be programmed into the Flash before SECDED is enabled This can be done by generating the correct values of the ECC with an external to...

Page 250: ...BAD1_15571557_15571557 1 x x x x x x x x x 554EA_B4D1B4D1_4B2E4B2E 0 x x x x x x x x x x Participating Data Bits 6 3 6 2 6 1 6 0 5 9 5 8 5 7 5 6 5 5 5 4 5 3 5 2 5 1 5 0 4 9 4 8 4 7 4 6 4 5 4 4 4 3 4 2...

Page 251: ...3 3 3 2 3 1 3 0 2 9 2 8 2 7 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0...

Page 252: ...D57 D D D51 D41 D M D D D31 x5 D D19 D09 D M D D D63 A08 D D D47 D D03 D25 D x6 D D20 D10 D M D D A14 A07 D D M D D04 D26 D x7 M D D M D D36 D58 D D D52 D42 D M D D M x8 E03 D D M D D37 D59 D D D53 D4...

Page 253: ...r erased The TI OTP sectors contain settings used by the Flash API to setup the Flash state machine for erase and program operations All of these OTP regions are memory mapped to facilitate ease of ac...

Page 254: ...Descriptions Bit Field Value Description 31 24 Reserved 0 Reserved All bits will be read as 0 23 16 BX_NUM_Sectors 1 32 Number of sectors in this bank 15 B7 1 1 Bank 7 is present 14 B6 0 0 Bank 6 is...

Page 255: ...SIZE R LEGEND R Read only Table 5 6 TI OTP Bank 0 Package and Memory Size Information Field Descriptions Bit Field Description 31 28 Reserved Reserved 27 16 PACKAGE Count of pins in the package 15 0 M...

Page 256: ...nerate a double bit error Figure 5 6 TI OTP Bank 0 Deliberate ECC Error Information F008 03F0h F008 03FFh 0x00 0x04 0x08 0x0C 0x12345678 0x9ABCDEF1 0x12345678 0x9ABCDEF3 R R R R LEGEND R Read only ECC...

Page 257: ...operation for the FSM 5 6 2 Diagnostic Mode The Flash wrapper can be put in diagnostic mode to verify various logic There are multiple diagnostic modes supported by the wrapper A specific diagnostic m...

Page 258: ...applying a new diagnostic data It takes multiple CPU transactions to preload the registers with diagnostic values During this time the result of the diagnostic logic such as comparator can change User...

Page 259: ...Raw ECC checkbit register FRAW_ECC then the malfunction logic should detect it as an error and set the ECC_B2_MAL_ERR bit ECC malfunction error There is one ECC_B2_MAL_ERR bit for each SECDED block a...

Page 260: ...e memory mapped to one address and likewise all duplicate tag registers are mapped to another single address During diagnostic mode each individual set can be selected by the DIAG_BUF_SEL Diagnostic B...

Page 261: ...FDIAGCTRL register is 5 and the access is a slave cycle This mode can set the FEDACSTATUS register status error bits B1_UNC_ERR or ERR_ZERO_FLG but it will not set the D_UNC_ERR nor D_COR_ERR bits Al...

Page 262: ...de FPRIM_ADD_TAG FUNC_ERR_ADD 1 ADD_TAG_ERR FDUP_ADD_TAG FRAW_DATAL 6 Reserved 7 ECC Data Correction Diagnostic test mode DAT_INV_PAR FUNC_ERR_ADD B1_UNC_ERR Slave access only FCOR_ERR_ADD ERR_ZERO_FL...

Page 263: ...p 1 Channel 35 1 ECC Data Correction test mode Bus 2 Yes Yes No No No EEPROM No No No Yes Yes 2 ECC Syndrome Reporting test mode Bus 2 No No No No No EEPROM No No No No No 3 ECC Malfunction test mode...

Page 264: ...nk Pump Ready Register Section 5 7 17 FFF8 7048h FPAC1 Flash Pump Access Control Register 1 Section 5 7 18 FFF8 704Ch FPAC2 Flash Pump Access Control Register 2 Section 5 7 19 FFF8 7050h FMAC Flash Mo...

Page 265: ...ield Value Description 31 12 Reserved 0 Reads return 0 Writes have no effect 11 8 RWAIT 0 Fh Random data Read Wait State The random read wait state bits indicate how many wait states are added to a Fl...

Page 266: ...rom setting the error bits in emulation mode and blocks the unfreezing of the bits and registers by reading the FUNC_ERR_ADD register 1 CPU suspend has no effect on error bit setting and unfreezing Th...

Page 267: ...1 when reading from the OTP or ECC memory locations Note When either the EOFEN or the EZFEN bit is set an error event will be generated on ESM group 1 channel 6 when any correctable error is generated...

Page 268: ...n occurrences before a correctable error event is generated ESM group 1 channel 6 A threshold of zero disables the threshold so that it does not generate an event 5 7 4 Flash Correctable Error Count R...

Page 269: ...the reset signal and contains unknown data at power up Figure 5 12 Flash Correctable Error Address Register FCOR_ERR_ADD offset 14h 31 16 COR_ERR_ADD R u 15 3 2 0 COR_ERR_ADD B_OFF R u R u LEGEND R Re...

Page 270: ...s detected This register is frozen while either the ERR_ZERO_FLG or the ERR_ONE_FLG bit is set in the FEDACSTATUS register During emulation mode this address is frozen even when read By setting the SU...

Page 271: ...r up Table 5 19 Flash Error Detection and Correction Status Register FEDACSTATUS Field Descriptions Bit Field Value Description 31 26 Reserved 0 Reads return 0 Writes have no effect 25 Reserved 0 Rese...

Page 272: ...and this would show up in the D_COR_ERR bit The ECC can always detect two bit errors Three or more bit errors may escape detection with the ECC This bit also may set during other uncorrectable errors...

Page 273: ...RR_ZERO_ FLG Error on Zero Fail Status Flag 0 No correctable errors on bus 1 nor any correctable errors on bus 2 where a 0 was read as a 1 1 A correctable error occurred on bus 1 or a correctable erro...

Page 274: ...r Address Register FUNC_ERR_ADD Field Descriptions Bit Field Value Description 31 3 UNC_ERR_ADD 0 1FFF FFFFh Uncorrectable Error Address UNC_ERR_ADD records the CPU logical address of which an uncorre...

Page 275: ...sector is disabled The only bank that supports sector disable is bank 7 7h If BankID1 7h and BankID1_inverse 0 then if a valid sector is selected by SectorID1 and SectorID1_inverse that sector will ha...

Page 276: ...not equal to 5h or DIAG_MODE is 0 or 7h Valid reads can occur in any mode The register will clear when an address tag error is found and when leaving DIAG_MODE 5 3 0 0 Always 0000 5 7 11 Duplicate Add...

Page 277: ...1 protection is disabled 5 7 13 Flash Bank Sector Enable Register FBSE FBSE provides one enable bit per sector for up to 16 sectors per bank Each bank in the Flash module has one FBSE register The ba...

Page 278: ...served R 0 15 8 7 0 BUSY 7 0 R WP 0 R 0 LEGEND R W Read Write R Read only WP Write in Privilege Mode n value after reset Table 5 26 Flash Bank Busy Register FBBUSY Field Descriptions Bit Field Value D...

Page 279: ...OTP sector is enabled 15 8 BAGP 0 FFh Bank Active Grace Period These bits contain the starting count value for the BAGP down counter Any access to a given bank causes its BAGP counter to reload the BA...

Page 280: ...W Read Write R Read only WP Write in Privilege Mode n value after reset Table 5 28 Flash Bank Fallback Power Register FBFALLBACK Field Descriptions Bit Field Value Description 31 16 Reserved 0505h Do...

Page 281: ...Descriptions Bit Field Value Description 31 24 Reserved 0 Reads return 0 Writes have no effect 23 16 BANKBUSY 7 0 Bank busy bits one bit for each bank 0 The bank is not busy 1 The bank is busy not re...

Page 282: ...Reserved 0 Reads return 0 Writes have no effect 26 16 PSLEEP Pump Sleep These bits contain the starting count value for the charge pump sleep down counter While the charge pump is in sleep mode the po...

Page 283: ...ter Note The PAGP down counter is clocked by the same prescaled clock as the BAGP down counter which is a divide by 16 of HCLK 5 7 20 Flash Module Access Control Register FMAC Figure 5 27 Flash Module...

Page 284: ..._EN in FSM_ST_MACHINE is not set 13 Reserved 0 Reads return 0 Writes have no effect 12 PGV Program Verify When set indicates that a word is not successfully programmed after the maximum allowed number...

Page 285: ...When set this bit indicates that the Flash module has received and processed an erase suspend operation This bit remains set until the erase resume command has been issued or until the Clear_More comm...

Page 286: ...re to be calculated should be programmed into this register This register is also used in diagnostic modes 1 and 2 where it supplies the upper data for checking the SECDED hardware 5 7 23 EEPROM Emula...

Page 287: ...Read only WP Write in Privilege mode n value after reset Table 5 36 EEPROM Emulation ECC Register FEMU_ECC Field Descriptions Bit Field Value Description 31 8 Reserved 0 Reserved 7 0 EMU_ECC 7 0 EEPRO...

Page 288: ...21 16 R 0 R WP 0 15 3 2 0 EMU_ADDR 15 3 Reserved R WP 0 R 0 LEGEND R W Read Write R Read only WP Write in Privilege mode n value after reset Table 5 37 EEPROM Emulation Address Register FEMU_ADDR Fie...

Page 289: ...ostic Control Register FDIAGCTRL Field Descriptions Bit Field Value Description 31 25 Reserved 0 Reserved 24 DIAG_TRIG Diagnostic Trigger Diagnostic trigger is the final qualifier for the diagnostic r...

Page 290: ...BUF_SEL The same occurs for the duplicate address see Section 5 7 11 Bit 0 selects a data buffer if high and an instruction buffer if low Bits 1 indicate the buffer number DIAG_BUF_SEL ENCODING Buffer...

Page 291: ...an be loaded with diagnostic values only in diagnostic modes 1 through 6 with DIAG_EN_KEY 0101 These modes must be set for at least one clock cycle before writing to any FRAW register 5 7 28 Uncorrect...

Page 292: ...Field Descriptions Bit Field Value Description 31 9 Reserved 0 Reserved 8 PIPE BUF Error came from pipeline buffer hit When this bit is a 1 latest error came from a pipeline buffer hit and the FRAW_D...

Page 293: ...is 101 the selected ADD_INV_PAR and DAT_INV_PAR fields will become active Any other value will cause the module to use the global system parity bit in the system register DEVCR1 8 ADD_INV_PAR Address...

Page 294: ...sector is disabled The only bank that supports sector disable is bank 7 7h If BankID3 7h and BankID3_inverse 0 then if a valid sector is selected by SectorID3 and SectorID3_inverse that sector will h...

Page 295: ...values the FSM registers cannot be written 5 7 33 FSM Sector Register FSM_SECTOR This is a banked register A separate register is implemented for each bank but they all occupy the same address The co...

Page 296: ...s that apply to RWAIT will apply to EWAIT in the EEPROM bank 15 9 Reserved 0 Reads return 0 Writes have no effect 8 AUTOSUSP_EN Auto Suspend Enable 0 Auto Suspend is disabled 1 Auto Suspend is enabled...

Page 297: ...corrected but will be treated as uncorrectable errors The single bit error flags and profiling mode are disabled Detection only mode has the advantage that a triple bit error will be detected and not...

Page 298: ...l 1s will NOT generate ECC errors The error counter for profiling will NOT increment if all 1s are detected 4 EE_ALL0_OK EEPROM Emulation All Zero Condition Valid 0 Zero condition valid is disabled Re...

Page 299: ...terrupt request is generated A threshold of zero disables the threshold so that it never triggers the profile interrupt 5 7 37 EEPROM Emulation Correctable Error Count Register EE_COR_ERR_CNT Figure 5...

Page 300: ...u unchanged value on internal reset cleared on power up Table 5 50 EEPROM Emulation Correctable Error Address Register EE_COR_ERR_ADD Field Descriptions Bit Field Value Description 31 3 COR_ERR_ADD 0...

Page 301: ...this address is frozen even when read By setting the SUSP_IGNR bit this register can be unfrozen in emulation mode This register is not changed with the reset signal and contains unknown data at power...

Page 302: ...ved EE_CMG Reserved EE_CME EE_D_COR_ ERR EE_ERR_ ONE_FLG EE_ERR_ ZERO_FLG EE_ERR_ PRF_FLG R 0 R 0 R 0 R 0 RCP u RCP u RCP u RCP u LEGEND R Read only RCP Read and Clear in Privilege Mode n value after...

Page 303: ...emulation mode This register is not changed with the reset signal and contains unknown data at power up Figure 5 48 EEPROM Emulation Uncorrectable Error Address Register EE_UNC_ERR_ADD offset 320h 31...

Page 304: ...e 5 54 Flash Bank Configuration Register FCFG_BANK Field Descriptions Bit Field Value Description 31 20 EE_BANK_WIDTH 90h Bank 7 width 144 bits wide This read only value indicates the maximum number o...

Page 305: ...hapter 6 SPNU503C March 2018 Tightly Coupled RAM TCRAM Module This chapter describes the tightly coupled RAM TCRAM module Topic Page 6 1 Overview 306 6 2 RAM Memory Map 307 6 3 Safety Features 308 6 4...

Page 306: ...nd B1TCM Connection Diagram The BTCM interface is further divided into two parts B0TCM and B1TCM which are both used to interface to actual RAM banks as shown in Figure 6 1 Figure 6 1 TCRAM Module Con...

Page 307: ...ct double bit errors within a 64 bit value The error correction codes ECC are stored in the RAM memory space as well The memory map for the TCRAM and the corresponding ECC space is shown in Figure 6 2...

Page 308: ...erfaces TCRAM Interface Module Features dedicated for SECDED Support Dedicated single bit error counter This counter is stored in a memory mapped register called RAMOCCUR RAMOCCUR is used to count the...

Page 309: ...6 3 3 Redundant Address Decode The TCRAM interface module generates the memory selects for each of the TCRAM banks as well as the ECC memory based on the CPU address The logic to generate these memory...

Page 310: ...PU before entering debug mode then it remains frozen during debug mode even if it is read The RAMPERRADDR register is not cleared by a read in debug mode 6 7 Control and Status Registers The TCRAM Mod...

Page 311: ...27 24 ADDR_PARITY_OVERRIDE Address Parity Override This field when set to Dh will invert the parity scheme selected by the device global parity selection The address parity checker would then work on...

Page 312: ...d Register RAMTHRESHOLD The RAMTHRESHOLD register shown in Figure 6 4 and described in Table 6 3 allows the application to configure the number of single bit error corrections by the SECDED logic insi...

Page 313: ...ication tries to clear the RAMOCCUR register at the same time as the TCRAM Module tried to update it then the TCRAM Module takes priority Note When the RAMTHRESHOLD register is set to 1 then the RAMOC...

Page 314: ...or subsequent failures This bit must be in a cleared state for generation of any new parity error interrupt 7 6 Reserved 0 Read returns 0 Writes have no effect 5 DERR This bit indicates a multi bit er...

Page 315: ...ister shown in Figure 6 8 and described in Table 6 7 captures the address for which the Cortex R4F CPU detected a single bit error NOTE The SERR bit in the RAMERRSTATUS register must be cleared by wri...

Page 316: ...uncorrectable error is indicated by the Cortex R4F CPU s SECDED logic For the SECDED multi bit or double bit uncorrectable error this register stores bits 17 3 of the TCM access address The lower 3 bi...

Page 317: ...d and fed into one channel and the non inverted vector is fed into the other channel If the XOR of these inputs is zero then the UERR interrupt is generated and ADDR_COMP_LOGIC_FAIL flag is set in RAM...

Page 318: ...s used to store the RAM chip select value for the redundant address decode and compare logic The stored value is passed as test stimulus for the built in test scheme 6 7 10 TCRAM Module Parity Error A...

Page 319: ...P Write in privileged mode only n value after reset Table 6 12 Auto Memory Initialization Enable Register INIT_DOMAIN Field Descriptions Bit Field Value Description 31 8 Reserved 0 Read returns 0 Writ...

Page 320: ...Built In Self Test PBIST Module This chapter describes the programmable built in self test PBIST controller module used for testing the on chip memories on the Hercules microcontrollers Topic Page 7...

Page 321: ...Software Based Testing The PBIST architecture consists of a small coprocessor with a dedicated instruction set targeted specifically toward testing memories This coprocessor executes test routines st...

Page 322: ...as required by the application s author 7 1 3 3 Memory Data Path This is the read and write data path logic between different system and peripheral memories tightly coupled to the PBIST memory interf...

Page 323: ...o Y es No Y es Wait for approximately N vbus clocks Reset the PBIST controller by writing MSTGCR 0x0A Disable PBIST Test Resume PBIST self test by writing 0x02 to the STR register by writing MSTGCR 0x...

Page 324: ...ster RINFOU must select only the single port RAM s The same applies for two port RAM s Check Architecture chapter for information on the memory types 8 Program OVER 1h to run PBIST self test without R...

Page 325: ...ic faults 2 Map Column The MAP COLUMN algorithm is used to identify bit line sensitivities in the memory array The memory array is loaded with a row stripe pattern of all 1s in the first row followed...

Page 326: ...erates as follows Load 1st half of the memory under test with one pattern Load 2nd half of the memory under test with the bit wise inverse of the pattern Alternate sequential reads sequences between o...

Page 327: ...ers Offset Acronym Register Description Section 000h 15Ch Reserved Reserved locations Do not write to these locations 160h RAMT RAM Configuration Register Section 7 5 1 164h DLR Datalogger Register Se...

Page 328: ...tion can read this register to identify the RGS RDS values for the memory that failed the self test Figure 7 3 RAM Configuration Register RAMT offset 0160h 31 24 23 16 RGS RDS R W X R W X 15 8 7 6 5 2...

Page 329: ...tting this bit allows the host processor to configure the PBIST controller registers 3 Reserved 1 Do not change this bit from its default value of 1 2 DLR2 ROM based testing setting this bit enables t...

Page 330: ...ing application self test Figure 7 5 PBIST Activate ROM Clock Enable Register PACT offset 0180h 31 16 Reserved R 0 15 1 0 Reserved PACT0 R 0 R W 0 LEGEND R W Read Write R Read only n value after reset...

Page 331: ...r is described in Figure 7 6 and Table 7 5 Figure 7 6 PBIST ID Register offset 184h 31 16 Reserved R 0 15 8 7 0 Reserved PBIST ID R 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table...

Page 332: ...d to select the memories for test 1 The memory information available from ROM will override the RAM selection from the RAM info registers RINFOL and RINFOU OVER0 While doing ROM based testing each alg...

Page 333: ...Functionality of the register is described in Figure 7 8 and Table 7 7 Figure 7 8 Fail Status Fail Register 0 FSRF0 offset 0190h 31 16 Reserved R 0 15 1 0 Reserved FSRF0 R 0 R 0 LEGEND R W Read Write...

Page 334: ...8 illustrate the FSRC0 register while Figure 7 10 and Table 7 9 illustrate the FSRC1 register Figure 7 9 Fail Status Count 0 Register FSRC0 offset 0198h 31 16 Reserved R 0 15 8 7 0 Reserved FSRC0 R 0...

Page 335: ...offset 01A0h 31 16 Reserved R 0 15 0 FSRA0 R 0 LEGEND R W Read Write R Read only n value after reset Table 7 10 Fail Status Address 0 Register FSRA0 Field Descriptions Bit Field Value Description 31 1...

Page 336: ...DL0 register while Figure 7 14 and Table 7 13 illustrate the FSRDL1 register Figure 7 13 Fail Status Data Register 0 FSRDL0 offset 01A8h 31 16 FSRDL0 R AAAAh 15 0 FSRDL0 R AAAAh LEGEND R W Read Write...

Page 337: ...OM 2h Only Algorithm information from ROM 3h Both Algorithm and RAM Group information from ROM This option should be selected for application self test 7 5 11 ROM Algorithm Mask Register ALGO This reg...

Page 338: ...eans all the RAM Groups are selected Figure 7 17 and Table 7 16 illustrate this register The information from this register is used only when bit 0 in OVER register is not set Figure 7 17 RAM Info Mas...

Page 339: ...s all 1s which means all the RAM Info Groups would be selected Figure 7 18 and Table 7 17 illustrate this register Figure 7 18 RAM Info Mask Upper Register RINFOU offset 01CCh 31 24 23 16 RINFOU3 RINF...

Page 340: ...sters for the memory self test OVER 0x0 7 Select the Algorithm refer to ALGO 0x00000054 Algo 3 March13N Algo 5 down1A_red Algo 7 Map column for two port RAM Group 3 8 Program the RAM group Info to sel...

Page 341: ...r to ALGO 0x000000FC select March13N Down1A and Map Column algorithms for single port and two port RAMs 8 Select both Algorithm and RAM information from on chip PBIST ROM ROM 0x3 9 Configure PBIST to...

Page 342: ...r 8 SPNU503C March 2018 CPU Self Test Controller STC Module This chapter describes the basics and configuration of the CPU self test controller present in the device Topic Page 8 1 General Description...

Page 343: ...afe feature Able to read the MISR data shifted from LBIST controller of the last executed interval of the self test run for debugging purposes STCCLK determines the self test execution speed STC clock...

Page 344: ...SPNU503C March 2018 Submit Documentation Feedback Copyright 2018 Texas Instruments Incorporated CPU Self Test Controller STC Module 8 1 2 3 STC Bypass ATE Interface This is a production test interface...

Page 345: ...4 or fewer intervals and run them during normal operation If STC is ran only on startup the user software need not save the CPU contents since the reset caused will go through all startup configuratio...

Page 346: ...om the DBIST controller is shifted into the STC This is compared with the golden MISR value stored in the ROM At the end of a CPU self test the STC controller updates the status flags in the Global St...

Page 347: ...45 50 4 77 28 5460 60 67 5 79 28 6825 75 83 6 80 90 8190 91 00 7 82 02 9555 106 17 8 83 10 10920 121 33 9 84 08 12285 136 50 10 84 87 13650 151 67 11 85 59 15015 166 83 12 86 11 16380 182 00 13 86 67...

Page 348: ...4 2 08h STCTPR Self Test Run Timeout Counter Preload Register Section 8 4 3 0Ch STC_CADDR STC Current ROM Address Register Section 8 4 4 10h STCCICR STC Current Interval Count Register Section 8 4 5 1...

Page 349: ...t specifies whether to continue the run from next interval onwards or to restart from interval 0 This bit gets reset after the completion of a self test run 0 Continue STC run from the previous interv...

Page 350: ...ature to prevent the device from hanging up due to a run away test during the self test The preload count value gets loaded into the self test time out down counter whenever a self test run is initiat...

Page 351: ...urrent Interval Count Register STCCICR offset 10h 31 16 Reserved R 0 15 0 N R 0 LEGEND R W Read Write R Read only n value after reset Table 8 8 STC Current Interval Count Register STCCICR Field Descri...

Page 352: ...ved 0 Read returns 0 Writes have no effect 1 TEST_FAIL Test Fail 0 Self test run has not failed 1 Self test run has failed 0 TEST_DONE Test Done 0 Not completed 1 Self test run completed The test done...

Page 353: ...tus Register STCFSTAT Field Descriptions Bit Field Value Description 31 3 Reserved 0 Read returns 0 Writes have no effect 2 TO_ERR Timeout Error 0 No time out error occurred 1 Self test run failed due...

Page 354: ...47 32 R 0 LEGEND R W Read Write R Read only n value after reset Figure 8 12 CPU1 Current MISR Register CPU1_CURMISR1 offset 24h 31 16 MISR 95 80 R 0 15 0 MISR 79 64 R 0 LEGEND R W Read Write R Read on...

Page 355: ...47 32 R 0 LEGEND R W Read Write R Read only n value after reset Figure 8 16 CPU2 Current MISR Register CPU2_CURMISR1 offset 34h 31 16 MISR 95 80 R 0 15 0 MISR 79 64 R 0 LEGEND R W Read Write R Read on...

Page 356: ...CR0 to 0 This register gets reset to its default value with any system reset assertion Figure 8 18 Signature Compare Self Check Register STCSCSCR offset 3Ch 31 16 Reserved R 0 15 5 4 3 0 Reserved FAUL...

Page 357: ...STCGCR0 31 16 24 4 Configure self test run time out counter preload register STCTPR 31 0 0xFFFFFFFF 5 Enable CPU self test STCGCR1 3 0 0xA 6 Perform a context save of CPU state and configuration regi...

Page 358: ...to detect faults which may result in unsafe operating conditions The CCM R4F detects faults and signals them to an error signaling module ESM NOTE In general R4F is used when referencing the Cortex CP...

Page 359: ...f test capability to allow for boot time checking of hardware faults within the CCM R4F itself The main features of the CCM R4F are run time detection of faults self test capability error forcing capa...

Page 360: ...ation software needs to ensure that the CPU registers of both CPUs are initialized with the same values before the registers are used including function calls where the register values are pushed onto...

Page 361: ...0xA 1 0 1 0 1 0 1 0 0xA 1 0 1 0 1 0 1 0 2 0x5 0 1 0 1 0 1 0 1 0x5 0 1 0 1 0 1 0 1 3 9 3 2 2 Compare Mismatch Test During the Compare Mismatch Test the number of test patterns is equal to twice the num...

Page 362: ...erted Error forcing mode is similar to the Compare Mismatch Test operation of self test mode in which an un equal vector is applied to the CCM R4F CPU signal ports The error forcing mode forces the co...

Page 363: ...M R4F will disable upon detection of halting debug requests Core compare error will not be generated and flags will not update A CPU reset is needed to ensure the CPUs are again in lockstep and will a...

Page 364: ...gnals are identical Write Leaves the bit unchanged 1 Read CPU signal compare mismatch Write Clears the bit 15 9 Reserved 0 Reads return zeros and writes have no effect 8 STC Self test Complete Note Th...

Page 365: ...R4F Key Register CCMKEYR Field Descriptions Bit Field Value Description 31 4 Reserved 0 Reads return to zeros and writes have no effect 3 0 MKEY Mode Key Read in User and Privileged mode Write in Pri...

Page 366: ...Oscillator and PLL This chapter describes the oscillator and PLL clock source paths for the device Topic Page 10 1 Introduction 367 10 2 Quick Start 368 10 3 Oscillator 369 10 4 Low Power Oscillator a...

Page 367: ...is useful for generating higher frequencies than can be conveniently achieved with an external crystal or resonator Additionally the PLL allows the flexibility to be able to synthesize one of multipl...

Page 368: ...lator has a wide frequency range which also creates a large valid window for the clock detect in order to refine the clock detect window the low power oscillator can be trimmed The initial trim value...

Page 369: ...orm The band pass functionality of the crystal resonator removes distortion from the OSCOUT waveform leaving a sinusoidal input waveform NOTE Vendor Validation of Resonators Crystals The crystal is a...

Page 370: ...ings at a high enough amplitude to pass an input clock into the core domain and nPORRST is released 1024 oscillator periods are counted before setting the CLKSR0V bit in the Clock Source Valid Status...

Page 371: ...omparator to independently trim the HF LPO and LF LPO frequencies BIAS ENABLE LPOMONCTL 24 enables disables the current source that drives the LPO 10 4 1 Clock Detect The LPO HF clock frequency is typ...

Page 372: ...rol Registers 3 Disable the oscillator by setting the appropriate bit in the Clock Source Disable Set Register CSDISSET This action resets the clock detect and allows the oscillator to propagate throu...

Page 373: ...CSDISCLR register allows the user to clear CSDIS bits without using a read modify write code construct 10 4 5 3 Disable LPO Current Bias The LPO current source may be disabled after the clock detect i...

Page 374: ...divides the reference input for a lower frequency input into the PLL fINTCLK fCLKIN NR The PLL multiplies this internal frequency by NF to get the VCO output clock frequency fOutput CLK fINTCLK NF Th...

Page 375: ...ield causes the PLL CLK to be gated these changes to ODPLL should be completed before configuring a clock domain for an asynchronous clock source Some clock domains for example RTICLK VCLK2 require a...

Page 376: ...modulation waveform is triangular and should be enabled after lock The modulation is digital and the spreading profile is triangular down spread which implies the modulation waveform is composed of a...

Page 377: ...D signal is dependent upon the PLL Slip signals so that VALID cannot be set if either slip signal is active PLL Clock The PLL output clock runs at the programmed frequency When enabled it takes some t...

Page 378: ...eld causes the PLL CLK to be gated these changes to ODPLL should be completed before configuring a clock domain for an asynchronous clock source Some clock domains for example RTICLK VCLK2 require a f...

Page 379: ...eased nPORRST 0 1 that release is delayed by 1024 OSCIN cycles so that it is released at the same time that the oscillator valid is asserted The system reset release is delayed by an additional 8 osci...

Page 380: ...the flexibility of the PLL s response to failure The slip filtering circuit samples the slip based on HF LPO The filter defines the number of consecutive HF LPO cycles for which the slip signal must...

Page 381: ...riting a 1 to the bit After this step the valid flag is unlocked and cleared if it was previously set 4 Re enable PLL1 with CSDISCLR 5 Switch the clock domains back to PLL1 If PLL2 fails the PLL s sli...

Page 382: ...n waveform The procedure for estimating the modulation depth is 1 While GCLK is sourced by the oscillator and the PLL is enabled with modulation configure SSWPLL1 as follows a CAPTURE_WINDOW_INDEX is...

Page 383: ...s 1 While the PLL is enabled set EXT_COUNTER_EN 2 Set COUNTER_EN This bit clears both SSW_CAPTURE_COUNT and SSW_CLKOUT_COUNT and then immediately enables for counting 3 Wait for some software delay lo...

Page 384: ...f the System and Peripheral Control Registers The following sections describe the PLL registers used in the system module These registers support 8 16 and 32 bit write accesses The reset values for th...

Page 385: ...hould be set equal to NR 7 Reserved 0 Read returns 0 Writes have no effect 6 COUNTER_READ_READY Counter read ready Indicates that SSW_CAPTURE_COUNT SSWPLL2 and SSW_CLKOUT_COUNT SSWPLL3 can be read 0 C...

Page 386: ...t 24 of CLKOUT counter is selected 5h Bit 26 of CLKOUT counter is selected 6h Bit 28 of CLKOUT counter is selected 7h Bit 30 of CLKOUT counter is selected 0 EXT_COUNTER_EN 0 Modulation Depth Measureme...

Page 387: ...plies to PLL1 but does not apply to PLL2 The SSWPLL3 register is shown in Figure 10 8 and described in Table 10 8 Figure 10 8 SSW PLL BIST Control Register 3 SSWPLL3 offset FF2Ch 31 16 SSW_CLKOUT_COUN...

Page 388: ...ustrates the sub blocks in a basic PLL circuit The VCO adjusts its frequency until the two signals into the PFD have the same phase and frequency The feedback path from VCO to PFD divides the frequenc...

Page 389: ...101 in equal proportions in this case the PLLMUL bit field would be programmed as 99 5 0x6380 This fractional multiplication is useful when trying to achieve final frequencies that are non integer to...

Page 390: ...f how to program the PLL For non modulation settings the PLLCTL1 and PLLCTL2 settings from 130nm process devices can be used without modification Suppose that using a 20MHz crystal the application req...

Page 391: ...r NF should be modified OR program the MULMOD bit field The modulation fields create a multiplier offset equal to 19 If using MULMOD 8 0 then 20 21 MULMOD will be set to 115 7 Convert the PLL paramete...

Page 392: ...al Clock Comparator DCC Module Chapter 11 SPNU503C March 2018 Dual Clock Comparator DCC Module This chapter describes the dual clock comparator DCC module Topic Page 11 1 Introduction 393 11 2 Module...

Page 393: ...e used to ensure the correct frequency range for several different device clock sources thereby enhancing the system safety metrics 11 1 1 Main Features The main features of each of the DCC modules ar...

Page 394: ...he actual frequencies of clock0 and clock1 are equal to their expected frequencies then the counter1 will reach zero either at the same time as counter0 or during the count down of the valid0 counter...

Page 395: ...window otherwise signal an error reload Count0 Count1 Error no error 0 0 Count1 Count0 Valid0 www ti com Module Operation 395 SPNU503C March 2018 Submit Documentation Feedback Copyright 2018 Texas In...

Page 396: ...k0 reload Count0 Counter1 reaches 0 before Clock1 Valid0 Error Counter0 reaches 0 Count1 0 0 Module Operation www ti com 396 SPNU503C March 2018 Submit Documentation Feedback Copyright 2018 Texas Inst...

Page 397: ...ource 5 using the main oscillator as a reference This measurement sequence would proceed as follows The application sets up the seed values for counter0 and valid0 for the duration of the measurement...

Page 398: ...an expected It includes the case when clock1 is stuck at 1 or 0 Any error freezes the counters from counting An application may then read out the counter values to help determine what caused the error...

Page 399: ...Table 11 1 DCC Control Registers Offset Acronym Register Description Section 00h DCCGCTRL DCC Global Control Register Section 11 4 1 04h DCCREV DCC Revision Id Register Section 11 4 2 08h DCCCNT0SEED...

Page 400: ...Others DONE interrupt is generated when the DONE flag is set in the DCC Status DCCSTAT register 11 8 SINGLE SHOT Single Shot Mode Enable Any operation mode read privileged mode write Ah DCC stops cou...

Page 401: ...fect 10 8 MAJOR 2h Major revision number Reads return 0x2 writes have no effect 7 6 CUSTOM 0 Custom version number Reads return 0x0 writes have no effect 5 0 MINOR 4h Minor revision number Reads retur...

Page 402: ...mode only sets the current seed value for Valid0 Writes in user mode are ignored NOTE Seed for Valid0 must be at least 0x4 The DCC must only be enabled after programming a value greater than or equal...

Page 403: ...only n value after reset Table 11 7 DCC Status Register DCCSTAT Field Descriptions Bit Field Value Description 31 2 Reserved 0 Reads return 0 Writes have no effect 1 DONE Single Shot Sequence Done fla...

Page 404: ...et 18h 31 20 19 16 Reserved COUNT0 R 0 R 0 15 0 COUNT0 R 0 LEGEND R Read only n value after reset Table 11 8 DCC Counter0 Value Register DCCCNT0 Field Descriptions Bit Field Value Description 31 20 Re...

Page 405: ...may not return exact current value of Valid0 Reading the Valid0 value while counting is enabled may not return the exact value of the Valid0 11 4 9 DCC Counter1 Value Register DCCCNT1 Figure 11 15 and...

Page 406: ...effect 15 12 KEY Key to enable clock source selection for counter1 Reads in any operating mode return the current value of the key Writes in privileged mode set the key value Ah Writing Ah as the key...

Page 407: ...0CLKSRC offset 28h 31 16 Reserved R 0 15 4 3 0 Reserved CNT0 CLKSRC R 0 R WP 5h LEGEND R W Read Write R Read only WP Write in privileged mode only n value after reset Table 11 12 DCC Counter0 Clock So...

Page 408: ...2018 Error Signaling Module ESM This chapter provides the details of the error signaling module ESM that aggregates device errors and provides the capability to define internal and external error resp...

Page 409: ...ation and predefined ERROR pin behavior 32 Group3 high severity channels with no interrupt generation and predefined ERROR pin behavior These channels have no interrupt response as they are reserved f...

Page 410: ...018 Texas Instruments Incorporated Error Signaling Module ESM Table 12 1 ESM Interrupt and ERROR Pin Behavior Error Group Interrupt to CPU Interrupt Priority ERROR Pin Response 1 Can be enabled or dis...

Page 411: ...MSR2 and ESMSR3 to debug the error If an RST is triggered or the error interrupt has been served the error flag of Group2 should be read from ESMSSR2 because the error flag in ESMSR2 will be cleared b...

Page 412: ...ated as 22 Once this period expires the ERROR pin is set to high in case the reset of the ERROR pin was requested This request is done by writing an appropriate key 5h to the key register ESMEKR durin...

Page 413: ...xample 5 The reset of the ERROR pin was requested by the software even before the failure occurs In this case the ERROR pin is set to high immediately after tERROR_low expires This case is not recomme...

Page 414: ...if a failure has already been detected in functional mode The application command to switch to error forcing mode is ignored 2 Write 5h to the ESM Error Key Register ESMEKR After that the ERROR pin sh...

Page 415: ...4 ESMIEPCR4 ESMIESR4 and ESMIECR4 ERROR www ti com Recommended Programming Procedure 415 SPNU503C March 2018 Submit Documentation Feedback Copyright 2018 Texas Instruments Incorporated Error Signaling...

Page 416: ...SR1 ESM Status Register 1 Section 12 4 7 FFFF F51Ch ESMSR2 ESM Status Register 2 Section 12 4 8 FFFF F520h ESMSR3 ESM Status Register 3 Section 12 4 9 FFFF F524h ESMEPSR ESM ERROR Pin Status Register...

Page 417: ...ter unchanged 1 Read Failure on channel x has influence on ERROR pin Write Enables failure influence on ERROR pin and sets the corresponding clear bit in the ESMIEPCR1 register 12 4 2 ESM Disable ERRO...

Page 418: ...e corresponding clear bit in the ESMIECR1 register unchanged 1 Read Interrupt is enabled Write Enables interrupt and sets the corresponding clear bit in the ESMIECR1 register 12 4 4 ESM Interrupt Enab...

Page 419: ...f channel x is mapped to high level interrupt line Write Maps interrupt of channel x to high level interrupt line and sets the corresponding clear bit in the ESMILCR1 register 12 4 6 ESM Interrupt Lev...

Page 420: ...es the bit unchanged 1 Read Error occurred interrupt is pending Write Clears the bit Note After RST if one of these flags are set and the corresponding interrupt are enabled the interrupt service rout...

Page 421: ...error occurred Write Leaves the bit unchanged 1 Read Error occurred Write Clears the bit 12 4 10 ESM ERROR Pin Status Register ESMEPSR Figure 12 20 ESM ERROR Pin Status Register ESMEPSR address FFFF...

Page 422: ...or the high level interrupt line Interrupts of error Group2 have higher priority than interrupts of error Group1 Inside a group channel 0 has highest priority and channel 31 has lowest priority User a...

Page 423: ...This vector gives the channel number of the highest pending interrupt request for the low level interrupt line Inside a group channel 0 has highest priority and channel 31 has lowest priority User an...

Page 424: ...ime counter is set to the default preload value of the ESMLTCPR in the following cases 1 Reset power on reset or warm reset 2 An error occurs 3 User forces an error 12 4 14 ESM Low Time Counter Preloa...

Page 425: ...ERROR pin set to high when the low time counter LTC has completed then the EKEY bit will switch back to normal mode EKEY 0000 Ah Forces error on ERROR pin All other values Activates normal mode 12 4 1...

Page 426: ...r unchanged 1 Read Failure on channel x has influence on ERROR pin Write Enables failure influence on ERROR pin and sets the corresponding clear bit in the ESMIEPCR4 register 12 4 18 ESM Influence ERR...

Page 427: ...e corresponding clear bit in the ESMIECR4 register unchanged 1 Read Interrupt is enabled Write Enables interrupt and sets the corresponding clear bit in the ESMIECR4 register 12 4 20 ESM Interrupt Ena...

Page 428: ...of channel x is mapped to high level interrupt line Write Maps interrupt of channel x to high level interrupt line and sets the corresponding clear bit in the ESMILCR4 register 12 4 22 ESM Interrupt...

Page 429: ...to clear in privilege mode only n value after reset PORRST X Value unchanged Table 12 25 ESM Status Register 4 ESMSR4 Field Descriptions Bit Field Value Description 63 32 ESF Error Status Flag Provide...

Page 430: ...as an operating system timer to support a real time operating system RTOS NOTE This chapter describes a superset implementation of the RTI module that includes features and functionality related to D...

Page 431: ...erence between the values 13 1 1 Features The RTI module has the following features Two independent 64 bit counter blocks Four configurable compares for generating operating system ticks or DMA reques...

Page 432: ...Figure 13 1 RTI Block Diagram 13 2 1 Counter Operation Each counter block consists of the following see Figure 13 2 One 32 bit prescale counter RTIUC0 or RTIUC1 One 32 bit free running counter RTIFRC0...

Page 433: ...l 31 0 Up Counter Register RTIUC0 31 0 31 0 RTICLK 31 0 31 0 31 0 OVLINT1 To Compare Unit Compare Up Counter RTICPUC1 Up Counter Capture Up Counter RTICAUC1 Free Running Counter RTIFRC1 Capture Free R...

Page 434: ...r register RTICAUCx which then holds the value captured at the time when reading the capture free running counter register RTICAFRCx NOTE The capture up counter registers are implemented as shadow reg...

Page 435: ...o avoid missing operating system ticks 13 2 4 Synchronizing Timer Events to Network Time NTU For applications which are participating on a time triggered communication bus it is often beneficial to sy...

Page 436: ...has to be set higher than 0 and lower than the timebase low compare value This effectively opens a window in which an edge of the NTUx signal is expected see Figure 13 5 Outside this window no edges...

Page 437: ...mebase high compare are programmed to a valid state before switching TBEXT to an external source This state is necessary to allow the timebase control circuit to operate correctly The following condit...

Page 438: ...Module Operation www ti com 438 SPNU503C March 2018 Submit Documentation Feedback Copyright 2018 Texas Instruments Incorporated Real Time Interrupt RTI Module Figure 13 7 Missing NTUx Signal Example 1...

Page 439: ...counter will be decremented with the RTICLK frequency Figure 13 9 DWD Operation The expiration time of the DWD down counter can be determined with the following equation texp DWDPRLD 1 213 RTICLK wher...

Page 440: ...igital Watchdog DWD preload register RTIDWDPRLD setting to define the end time of the window The start time of the window is defined by a window size configuration register RTIWWDSIZECTRL The default...

Page 441: ...g events while in Sleep mode is not supported as the clock to the RTI is not active When the device is put into low power mode the peripheral which is generating the external clock NTU is no longer ac...

Page 442: ...ounter 1 Register Section 13 3 14 50h RTICOMP0 RTI Compare 0 Register Section 13 3 15 54h RTIUDCP0 RTI Update Compare 0 Register Section 13 3 16 58h RTICOMP1 RTI Compare 1 Register Section 13 3 17 5Ch...

Page 443: ...USEL Select NTU signal These bits determine which NTU input signal is used as external timebase 0h NTU0 5h NTU1 Ah NTU2 Fh NTU3 All other values Tied to 0 15 COS Continue on suspend This bit determine...

Page 444: ...scriptions Bit Field Value Description 31 2 Reserved 0 Reads return 0 Writes have no effect 1 INC Increment free running counter 0 This bit determines whether the free running counter 0 RTIFRC0 is aut...

Page 445: ...Write in privileged mode only n value after reset Table 13 4 RTI Capture Control Register RTICAPCTRL Field Descriptions Bit Field Value Description 31 2 Reserved 0 Reads return 0 Writes have no effect...

Page 446: ...ffect 12 COMPSEL3 Compare select 3 This bit determines the counter with which the compare value held in compare register 3 RTICOMP3 is compared 0 Value will be compared with RTIFRC0 1 Value will be co...

Page 447: ...r RTIUC0 The up counter 0 register holds the current value of prescale counter This register is shown in Figure 13 17 and described in Table 13 7 Figure 13 17 RTI Up Counter 0 Register RTIUC0 offset 1...

Page 448: ...the RTI clock If CPUC0 0 then fFRC0 RTICLK 232 1 Setting CPUC0 equal to 0 is not recommended Doing so will hold the Up Counter at 0 for 2 RTICLK cycles after it overflows from FFFF FFFFh to 0 If CPUC...

Page 449: ...sures that the value of the RTICAUC0 register is the corresponding value to the RTICAFRC0 register even if another capture event happens in between the two reads A read of this register returns the va...

Page 450: ...register holds the current value of the up counter 1 and prescales the RTI clock It will be only updated by a previous read of free running counter 1 RTIFRC1 This method of updating effectively gives...

Page 451: ...are Up Counter 1 Register RTICPUC1 Field Descriptions Bit Field Value Description 31 0 CPUC1 0 FFFF FFFFh Compare up counter 1 This register holds the compare value which is compared with the up count...

Page 452: ...ure control block A read of this register returns the value of RTIFRC1 on a capture event 13 3 14 RTI Capture Up Counter 1 Register RTICAUC1 The capture up counter 1 register holds the current value o...

Page 453: ...e a DMA request A read of this register will return the current compare value A write to this register in privileged mode only will update the compare register with a new compare value 13 3 16 RTI Upd...

Page 454: ...ble to initiate a DMA request A read of this register will return the current compare value A write to this register will update the compare register with a new compare value 13 3 18 RTI Update Compar...

Page 455: ...to initiate a DMA request A read of this register will return the current compare value A write to this register in privileged mode only will provide a new compare value 13 3 20 RTI Update Compare 2...

Page 456: ...is possible to initiate a DMA request A read of this register will return the current compare value A write to this register will provide a new compare value 13 3 22 RTI Update Compare 3 Register RTI...

Page 457: ...value is updated If TBEXT 1 The compare value is not changed 13 3 24 RTI Timebase High Compare Register RTITBHCOMP The timebase high compare register holds the value to deactivate the edge detection...

Page 458: ...Control Register RTISETINTENA Field Descriptions Bit Field Value Description 31 19 Reserved 0 Reads return 0 Writes have no effect 18 SETOVL1INT Set free running counter 1 overflow interrupt 0 Read I...

Page 459: ...enabled 7 4 Reserved 0 Reads return 0 Writes have no effect 3 SETINT3 Set compare interrupt 3 0 Read Interrupt is disabled Write Corresponding bit is unchanged 1 Read or Write Interrupt is enabled 2...

Page 460: ...TI Clear Interrupt Control Register RTICLEARINTENA Field Descriptions Bit Field Value Description 31 19 Reserved 0 Reads return 0 Writes have no effect 18 CLEAROVL1INT Clear free running counter 1 ove...

Page 461: ...nged 1 Read DMA request is enabled Write DMA request is disabled 7 4 Reserved 0 Reads return 0 Writes have no effect 3 CLEARINT3 Clear compare interrupt 3 0 Read Interrupt is disabled Write Correspond...

Page 462: ...Interrupt is pending Write Bit is cleared to 0 17 OVL0INT Free running counter 0 overflow interrupt flag This bit determines if an interrupt is pending 0 Read No interrupt is pending Write Bit is unc...

Page 463: ...s disabling the watchdog This register is shown in Figure 13 38 and described in Table 13 28 Figure 13 39 Digital Watchdog Control Register RTIDWDCTRL offset 90h 31 16 DWDCTRL R WP 5312h 15 0 DWDCTRL...

Page 464: ...R W Read Write R Read only WP Write in privileged mode only n value after reset Table 13 30 Digital Watchdog Preload Register RTIDWDPRLD Field Descriptions Bit Field Value Description 31 12 Reserved...

Page 465: ...e CPU in this case Write Bit is cleared to 0 This will also clear all other status flags in the RTIWDSTATUS register Clearing of the status flags will deassert the non maskable interrupt generated due...

Page 466: ...31 16 Reserved 0 Reads return 0 and writes have no effect 15 0 WDKEY 0 FFFFh Watchdog key These bits provide the key sequence location Reads returns the current WDKEY value A write of E51Ah followed b...

Page 467: ...R 0 15 4 3 0 Reserved WWDRXN R 0 R WP 5h LEGEND R W Read Write R Read only WP Write in privileged mode only n value after reset Table 13 35 Digital Windowed Watchdog Reaction Control RTIWWDRXNCTRL Fie...

Page 468: ...reset Table 13 36 Digital Windowed Watchdog Window Size Control RTIWWDSIZECTRL Field Descriptions Bit Field Value Description 31 0 WWDSIZE 0 The DWWD window size 0000 0005h 100 The functionality is th...

Page 469: ...auto clear functionality on the compare 3 interrupt 5h Read Auto clear for compare 3 interrupt is disabled Privileged Write Auto clear for compare 3 interrupt becomes disabled All other values Read Au...

Page 470: ...e in the RTIUDCP0 register Section 13 3 16 is added to this register Reads return the current compare clear value A privileged write to this register updates the compare clear value 13 3 37 RTI Compar...

Page 471: ...e in the RTIUDCP2 register Section 13 3 20 is added to this register Reads return the current compare clear value A privileged write to this register updates the compare clear value 13 3 39 RTI Compar...

Page 472: ...he cyclic redundancy check CRC controller module NOTE This chapter describes a superset implementation of the CRC module that includes features and functionality that require DMA Since not all devices...

Page 473: ...fication on any memory sub system Data compression on 8 16 32 and 64 bit data size Maximum length PSA Parallel Signature Analysis register constructed based on 64 bit primitive polynomial Each channel...

Page 474: ...20 Bit Pattern Count Preload 20 Bit Pattern Counter CRC Status Bit 24 Bit Timeout Preload Register 24 Bit Time Out Counter 16 Bit Sector Count Preload 16 Bit Sector Counter CRC Interrupt Generation L...

Page 475: ...f sustained CRC signature calculation can be achieved without any CPU intervention CRC Controller also provides data trace capability Channel 1 can perform data trace on CPU data bus During data trace...

Page 476: ...o calculate the next value of each shift register bit after one cycle 2 The outer loop is to simulate 64 cycles of shifting The equation for each shift register bit is thus built before it is compress...

Page 477: ...sed value is always expressed in 64 bit There is a software reset per channel for PSA Signature Register When set the PSA Signature Register is reset to all zeros PSA Signature Register is reset to ze...

Page 478: ...rformed If the flag is not set then it means the CRC Value Register contains stale information A CRC underrun interrupt is generated When an underrun condition is detected signature verification is no...

Page 479: ...count register inside DMA module The DMA transfer count register is divided into two parts They are element count and frame count Note that an HW DMA request can be programmed to trigger either one f...

Page 480: ...tive Inactive Inactive 14 2 8 Pattern Count Register There is a 20 bit data pattern counter for every CRC channel The data pattern counter is a down counter and can be pre loaded with a programmable v...

Page 481: ...d in Full CPU mode Compression complete interrupt CRC fail interrupt Overrun interrupt Underrun interrupt Timeout interrupt Table 14 2 Modes in Which Interrupt Condition Can Occur AUTO Semi CPU Full C...

Page 482: ...prescaler clock which is permanently running at division 64 of HCLK clock First pattern of data must be transferred by the DMA before the timeout counter expires Watchdog timeout pre load register CRC...

Page 483: ...efore it can service the timer request Timer Time scale HW DMA req every 10 ms Data 10 9 8 7 6 5 4 3 4 3 2 1 0 10 9 8 7 6 4 3 2 1 0 10 9 8 7 6 4 3 2 1 0 10 9 8 7 6 0 ms 10 ms 20 ms 30 ms 6 ms 16 ms 26...

Page 484: ...r should perform the following steps in the ISR 1 Write to software reset bit in CRC_CTRL register to reset the respective PSA Signature Register 2 Reset the CHx_MODE bits to 00 in CRC_CTRL register a...

Page 485: ...red When CRC controller is in power down mode no data tracing alone will happen However if CRC registers are accessed then data trace happens from channel 1 14 2 13 Emulation A read access from a regi...

Page 486: ...3 1 2 Timer Setup The timer can be any general purpose timer that is capable of generating a time based DMA request Set up timer to generate DMA request associated with DMA channel 2 For example an O...

Page 487: ...Put the source address at post increment addressing mode and put the destination address at constant address mode Generate a software DMA request on channel 2 after CRC has completed its setup Enable...

Page 488: ...to generate DMA request associated with DMA channel 1 For example an OS can set up the timer to generate a DMA request every 10ms 14 3 3 3 CRC Setup Program the pattern count to 128 Program the secto...

Page 489: ...0 48h CRC_CURSEC_REG1 CRC Channel 1 Current Sector Register Section 14 4 11 4Ch CRC_WDTOPLD1 CRC Channel 1 Watchdog Timeout Preload Register Section 14 4 12 50h CRC_BCTOPLD1 CRC Channel 1 Block Comple...

Page 490: ...refore CPU is required to clear this bit by writing a 0 0 PSA Signature Register is not reset 1 PSA Signature Register is reset 7 1 Reserved 0 Reads return 0 Writes have no effect 0 CH1_PSA_SWREST Cha...

Page 491: ...ut any compression This mode can be used to plant seed value into the PSA register 1h AUTO Mode 2h Semi CPU Mode 3h Full CPU Mode 7 5 Reserved 0 Reads return 0 Writes have no effect 4 CH1_TRACEEN Chan...

Page 492: ...eld Value Description 31 13 Reserved 0 Reads return 0 Writes have no effect 12 CH2_TIMEOUTENS Channel 2 Timeout Interrupt Enable Bit User and Privileged mode read 0 Timeout Interrupt is disabled 1 Tim...

Page 493: ...rite 0 Has no effect 1 Timeout Interrupt is enabled 3 CH1_UNDERENS Channel 1 Underrun Interrupt Enable Bit User and Privileged mode read 0 Underrun Interrupt is disabled 1 Underrun Interrupt is enable...

Page 494: ...Description 31 13 Reserved 0 Reads return 0 Writes have no effect 12 CH2_TIMEOUTENR Channel 2 Timeout Interrupt Enable Reset Bit User and Privileged mode read 0 Timeout Interrupt is disabled 1 Timeou...

Page 495: ...Has no effect 1 Timeout Interrupt is disabled 3 CH1_UNDERENR Channel 1 Underrun Interrupt Enable Reset Bit User and Privileged mode read 0 Underrun Interrupt is disabled 1 Underrun Interrupt is enable...

Page 496: ...no effect 12 CH2_TIMEOUT Channel 2 CRC Timeout Interrupt Status Flag This bit is set in both AUTO and Semi CPU mode User and Privileged mode read 0 No timeout interrupt is active 1 Timeout interrupt...

Page 497: ...active Privileged mode write 0 Has no effect 1 Bit is cleared 3 CH1_UNDER Channel 1 Underrun Interrupt Status Flag User and Privileged mode read 0 No Underrun Interrupt is active 1 Underrun Interrupt...

Page 498: ...C_INT_OFFSET_REG Field Descriptions Bit Field Value Description 31 8 Reserved 0 Reads return 0 Writes have no effect 7 0 OFSTREG CRC Interrupt Offset This register indicates the highest priority pendi...

Page 499: ...t data pattern of the block is compressed 7 1 Reserved 0 Reads return 0 Writes have no effect 0 CH1_BUSY CH1_BUSY During AUTO or Semi CPU mode the busy flag is set when the first data pattern of the b...

Page 500: ...Reserved R 0 15 0 CRC_CURSEC1 R 0 LEGEND R W Read Write R Read only n value after reset Table 14 15 CRC Current Sector Register 1 CRC_CURSEC_REG1 Field Descriptions Bit Field Value Description 31 16 R...

Page 501: ...ntains the number of clock cycles within which the DMA must transfer the next block of data patterns In Semi CPU mode this register is used to indicate the sector number for which the compression comp...

Page 502: ...Signature High Register PSA_SIGREGH1 Figure 14 23 Channel 1 PSA Signature High Register PSA_SIGREGH1 offset 64h 31 0 PSASIG1 R W 0 LEGEND R W Read Write R Read only n value after reset Table 14 19 Cha...

Page 503: ...SA_SECSIGREGL1 Figure 14 26 Channel 1 PSA Sector Signature Low Register PSA_SECSIGREGL1 offset 70h 31 0 PSASECSIG1 R 0 LEGEND R Read only n value after reset Table 14 22 Channel 1 PSA Sector Signature...

Page 504: ...ffset 7Ch 31 0 RAW_DATA1 R 0 LEGEND R Read only n value after reset Table 14 25 Channel 1 Raw Data High Register RAW_DATAREGH1 Field Descriptions Bit Field Description 31 0 RAW_DATA1 Channel 1 Raw Dat...

Page 505: ...rved R 0 15 0 CRC_CURSEC2 R 0 LEGEND R W Read Write R Read only n value after reset Table 14 28 CRC Current Sector Register 2 CRC_CURSEC_REG2 Field Descriptions Bit Field Value Description 31 16 Reser...

Page 506: ...ntains the number of clock cycles within which the DMA must transfer the next block of data patterns In Semi CPU mode this register is used to indicate the sector number for which the compression comp...

Page 507: ...Signature High Register PSA_SIGREGH2 Figure 14 36 Channel 2 PSA Signature High Register PSA_SIGREGH2 offset A4h 31 0 PSASIG2 R W 0 LEGEND R W Read Write R Read only n value after reset Table 14 32 Cha...

Page 508: ...SA_SECSIGREGL2 Figure 14 39 Channel 2 PSA Sector Signature Low Register PSA_SECSIGREGL2 offset B0h 31 0 PSASECSIG2 R 0 LEGEND R Read only n value after reset Table 14 35 Channel 2 PSA Sector Signature...

Page 509: ...Raw Data Low Register RAW_DATAREGL2 Field Descriptions Bit Field Description 31 0 RAW_DATA2 Channel 2 Raw Data Low Register This register contains bits 31 0 of the uncompressed raw data 14 4 34 Chann...

Page 510: ...reset Table 14 39 Data Bus Selection Register Field Descriptions Bit Field Value Description 31 3 Reserved 0 Reads return 0 Writes have no effect 2 MEn Enable disables the tracing of Peripheral Bus M...

Page 511: ...pt Manager VIM Module This chapter describes the behavior of the vectored interrupt manager VIM module of the device family Topic Page 15 1 Overview 512 15 2 Device Level Interrupt Management 512 15 3...

Page 512: ...w to an interrupt service routine ISR The VIM module has the following features Supports 95 interrupt channels in both register vectored interrupt and hardware vectored interrupt mode Provides IRQ vec...

Page 513: ...interrupt requests FIQs and normal interrupt requests IRQs FIQs are higher priority than IRQs and FIQ interrupts may interrupt IRQ interrupts NOTE The FIQ implemented in Cortex R4F is Non Maskable Fas...

Page 514: ...After the interrupt is received by the CPU the CPU executes the instruction placed at 0x18 or 0x1C IRQ or FIQ vector to load the address of ISR interrupt vector from the interrupt vector register Exam...

Page 515: ...VECTOR IRQ VECTOR FIQVECREG IRQVECREG PROGRAMMABLE INTERRUPT VECTOR TABLE Phantom Vector Channel 0 Vector Channel 1 Vector Channel 94 Vector FIQINDEX IRQINDEX TO CPU VIC Port Register Register T o CPU...

Page 516: ...rrupt request With this scheme the same request can be mapped to multiple channels A lower numbered channel in each FIQ and IRQ has higher priority The programmability of the VIM allows software to co...

Page 517: ...al Peripheral 0 Channel 0 Vector 0xFFF82004 INT_REQ1 CHAN1 Peripheral 1 Channel 1 Vector 0xFFF82008 INT_REQ2 CHAN2 Peripheral 2 Channel 2 Vector 0xFFF8200C INT_REQ3 CHAN3 Peripheral 3 Channel 3 Vector...

Page 518: ...ror Signal Module high level interrupt and CHAN1 is reserved for other NMI For safety reasons these two channels are mapped to FIQ only and can NOT be disabled through ENABLE registers NOTE NMI Channe...

Page 519: ...rrupt line becomes active 15 4 Interrupt Vector Table VIM RAM Interrupt vector table stores the address of ISRs During register vectored interrupt and hardware vectored interrupt VIM accesses the inte...

Page 520: ...RR register will provide to the VIC port IRQVECREG and FIQVECREG a fall back address to an ISR that can restore the interrupt vector table content The FBPARERR register should be set before initializi...

Page 521: ...mented by the test bit in the PARCTL register Once the bit is set the parity bits are mapped to 0xFFF82400 After that user can force faults into the parity bits Finally the parity error can be trigger...

Page 522: ...15 5 VIM Wakeup Interrupt The wakeup interrupts are used to come out of low power mode LPM Any interrupt requests can be used to wake up the device After reset all interrupt requests are set to wake u...

Page 523: ...ng sections provide examples about the operation of the VIM 15 7 1 Examples Configure CPU To Receive Interrupts Example 15 1 shows how to set the vector enable VE bit in the CP15 R1 register to enable...

Page 524: ...e LDR PC PC 0x1B0 The pending ISR address is written into the corresponding vector register IRQVECREG for IRQ FIQVECREG for FIQ The CPU reads the content of the register and branches to the ISR Exampl...

Page 525: ...TERRUPT PROCESSING AREA 0000001Ch ldrb R8 PC 0x21d FIQ INTERRUPT ENTRY R8 used to get the FIQ index with address pointer to the first FIQ banked register 00000020h ldr PC PC R8 LSL 2 Branch to the ind...

Page 526: ...Section 15 8 8 14h FIRQPR1 FIQ IRQ Program Control Register 1 Section 15 8 8 18h FIRQPR2 FIQ IRQ Program Control Register 2 Section 15 8 8 20h INTREQ0 Pending Interrupt Read Location Register 0 Secti...

Page 527: ...ed Write A write to this bit has no effect 1 Read A parity error has occurred and the Interrupt Vector Table is bypassed Write The PARFLG is cleared and the interrupt vector can be read from the Inter...

Page 528: ...rrors will not update this register until the PARFLG register has been cleared Note This register is valid only when PARFLG is set see Section 15 8 1 1 0 Word offset Word offset Reads are always 0 wri...

Page 529: ...e index to the highest priority FIQ interrupt The index can be used to locate the interrupt routine in a dispatch table as shown in Table 15 6 Table 15 6 Interrupt Dispatch IRQINDEX FIQINDEX Register...

Page 530: ...ext highest priority pending IRQ interrupt In case there is no other interrupt pending the IRQINDEX will read 0x00 and the IRQVECREG register will read the phantom interrupt address 15 8 7 FIQ Index O...

Page 531: ...in privilege mode only n value after reset Figure 15 18 FIQ IRQ Program Control Register 1 FIRQPR1 offset 14h 31 16 FIRQPR1 63 48 R WP 0 15 0 FIRQPR1 47 32 R WP 0 LEGEND R W Read Write R Read only WP...

Page 532: ...to clear in privilege mode only n value after reset Figure 15 22 Pending Interrupt Read Location Register 2 INTREQ2 Register offset 28h 31 16 INTREQ2 95 80 R W1CP 0 15 0 INTREQ2 79 64 R W1CP 0 LEGEND...

Page 533: ...r reset Figure 15 24 Interrupt Enable Set Register 1 REQENASET1 offset 34h 31 16 REQENASET1 63 48 R WP 0 15 0 REQENASET1 47 32 R WP 0 LEGEND R W Read Write R Read only WP Write in privilege mode only...

Page 534: ...Interrupt Enable Clear Register 1 REQENACLR1 offset 44h 31 16 REQENACLR1 63 48 R WP 0 15 0 REQENACLR1 47 32 R WP 0 LEGEND R W Read Write R Read only WP Write in privilege mode only n value after rese...

Page 535: ...5 30 Wake Up Enable Set Register 1 WAKEENASET1 offset 54h 31 16 WAKEENASET1 63 48 R WP FFFFh 15 0 WAKEENASET1 47 32 R WP FFFFh LEGEND R W Read Write WP Write in privilege mode only n value after reset...

Page 536: ...Clear Register 1 WAKEENACLR1 offset 64h 31 16 WAKEENACLR1 63 48 R WP FFFFh 15 0 WAKEENACLR1 47 32 R WP FFFFh LEGEND R W Read Write WP Write in privilege mode only n value after reset Figure 15 34 Wake...

Page 537: ...xt highest priority pending IRQ interrupt In case there is no other interrupt pending the IRQINDEX will read 0x00 and the IRQVECREG register will read the phantom interrupt address 15 8 15 FIQ Interru...

Page 538: ...set Table 15 17 Capture Event Register CAPEVT Field Descriptions Bit Field Value Description 31 23 Reserved 0 Reads are indeterminate and writes have no effect 22 16 CAPEVTSRC1 Capture event source 1...

Page 539: ...hard wired to INT_REQ0 and INT_REQ1 Do NOT write any value other than 0x5F to CHANMAP95 Channel 95 is reserved because no interrupt vector table entry supports this channel Figure 15 38 Interrupt Con...

Page 540: ...annel CHANx2 maps to 0 Read Interrupt request 0 maps to channel priority CHANx2 Write The default value of this bit after reset is given in Table 15 18 The channel priority CHANx2 is set with the inte...

Page 541: ...rporated Direct Memory Access Controller DMA Module Chapter 16 SPNU503C March 2018 Direct Memory Access Controller DMA Module This chapter describes the direct memory access DMA controller Topic Page...

Page 542: ...l information is stored in RAM protected by parity 16 channels with individual enable Channel chaining capability 32 peripheral DMA requests Hardware and Software DMA requests 8 16 32 or 64 bit transa...

Page 543: ...n between program memory and data memory The DMA controller can transfer to and from any space within the 4 gigabyte physical address map by programming the absolute address for the source and destina...

Page 544: ...e and channel configuration Source address destination address and transfer count also have their respective working images The three fields of working images compose a working control packet and are...

Page 545: ...r Count Current Transfer Count 0x1F0 0x1E0 0x810 0x8F0 Base 0xXXXC Reserved 0x10 Primary CP0 Primary CP1 Primary CPnn Working CP0 Working CP1 Working CPnn Base 0XXX0 Base 0xXXX4 Base 0xXXX8 Initial So...

Page 546: ...control packet finish Channel Chaining 16 2 4 5 Element Frame Offset Value There are 4 offset values that allow the creation of different types of buffers in RAM and address registers in a structured...

Page 547: ...0x0C 0x0 0x4 0x0 0x4 0x0 0x4 0x0 E7 8 E1 3 5 7 E2 4 6 8 Source Element Index 12 Source Frame Index 1 The example assumes the following setup Read Element Size 8 bit Write Element Size 8 bit Element Co...

Page 548: ...DMA Module Figure 16 8 DMA Indexing Example 2 16 2 5 Priority Queue User can assign channels in to priority queues to facilitate request handling during arbitration The port has two priority queues a...

Page 549: ...e the next highest pending channel is serviced When there is no pending channels left in high queue then the DMA switches to service low queue channels Rotating Channels are arbitrated by using the ro...

Page 550: ...al to the write element size no packing is performed during read nor is any unpacking performed during write Figure 16 12 shows an example of data unpacking in which the DMA is used to transfer 128 tr...

Page 551: ...npacking When the read element size is smaller than the write element size the DMA controller needs to perform data packing The number of elements to pack is equal to the ratio between the write eleme...

Page 552: ...n www ti com 552 SPNU503C March 2018 Submit Documentation Feedback Copyright 2018 Texas Instruments Incorporated Direct Memory Access Controller DMA Module Figure 16 13 Example of DMA Data Packing For...

Page 553: ...A cannot capture more than three requests if its request buffers are already full If any request occur during this moment DMA will discard it The DMA controller also supports a mix of hardware and sof...

Page 554: ...MIBSPI3 8 DCAN1 IF3 MibADC2 G1 DMAREQ 16 MIBSPI1 MIBSPI3 DCAN3 MibADC2 MIBSPI1 9 MIBSPI3 9 DCAN3 IF1 MibADC2 G2 DMAREQ 17 RTI USB Device MIBSPI5 RTI DMAREQ2 USB_FUNC DMATXREQ_ON 1 MIBSPI5 8 DMAREQ 18...

Page 555: ...t can be issued when a bus error Illegal transaction with ok response is detected The imprecise read error is connected to the ESM module External imprecise error on write an interrupt can be issued w...

Page 556: ...O U P A DMA S C R DMA DMM imprecise read error Group 1 5 DMA DMM imprecise write error Group 1 13 Module Operation www ti com 556 SPNU503C March 2018 Submit Documentation Feedback Copyright 2018 Texas...

Page 557: ...ers two power management modes run and sleep In run mode the DMA is fully operational The sleep mode shuts down the DMA if no pending channels are waiting to be serviced If a DMA request is received o...

Page 558: ...8 bit 16 bit 32 bit 64 bit Read Element Size 8 bit 1 read 1 write 2 read 1 write 4 read 1 write 8 read 1 write 16 bit 1 read 2 write 1 read 1 write 2 read 1 write 4 read 1 write 32 bit 1 read 4 write...

Page 559: ...ilege for a given memory region the start and end address for the region and notification of an access violation for the protected region Each region to be protected is configured by software by writi...

Page 560: ...ample of Protection Mechanism 16 2 15 Parity Checking Parity checking is implemented using parity on a per byte basis for DMA Control Packets in the RAM Checking for even or odd parity can be programm...

Page 561: ...able 16 5 Table 16 6 and Table 16 7 P0 is the parity bit for byte 0 P1 is the parity bit for byte 1 and so on Each byte in the control packet RAM has its own parity bit in the control packet parity RA...

Page 562: ...Enable Set Register Section 16 3 1 10 4Ch GCHIENAR Global Channel Interrupt Enable Reset Register Section 16 3 1 11 54h DREQASI0 DMA Request Assignment Register 0 Section 16 3 1 12 58h DREQASI1 DMA Re...

Page 563: ...Section 16 3 1 53 1B0h DMAMPCTRL DMA Memory Protection Control Register Section 16 3 1 54 1B4h DMAMPST DMA Memory Protection Status Register Section 16 3 1 55 1B8h DMAMPR0S DMA Memory Protection Regio...

Page 564: ...to prevent state machines from carrying out bus transactions If DMA_EN bit is cleared in the middle of an bus transaction the state machine will stop at an arbitration boundary 0 The DMA is disabled 1...

Page 565: ...ly cleared for the following conditions At the end of a frame or a block transfer depending on how the channel is triggered as programmed in the TTYPE bit field of CHCTRL The control packet is modifie...

Page 566: ...ly for the following conditions At the end of a block transfer if the auto initiation bit AIM see CHCTRL is not active If an AHB bus error is detected for an active channel Reading from HWCHENAS gives...

Page 567: ...ng conditions The corresponding bit is cleared after one frame transfer if the TTYPE bit in Channel Control Register CHCTRL is programmed for frame transfer The corresponding bit is cleared after one...

Page 568: ...1 and so on 0 Read The corresponding channel was not triggered by SW Write No effect 1 Read The corresponding channel was triggered by SW Write The corresponding channel is disabled 16 3 1 8 Channel...

Page 569: ...e low priority queue 0 Read The corresponding channel is assigned to the low priority queue Write No effect 1 Read The corresponding channel is assigned to the high priority queue Write The correspond...

Page 570: ...WP 0 LEGEND R W Read Write R Read only WP Write in privilege mode only n value after reset Table 16 20 Global Channel Interrupt Enable Reset Register GCHIENAR Field Descriptions Bit Field Value Descr...

Page 571: ...0 assignment This bit field chooses the DMA request assignment for channel 0 0 DMA request line 0 triggers channel 0 1Fh DMA request line 31 triggers channel 0 20h 3Fh Reserved 23 22 Reserved 0 Reads...

Page 572: ...4 assignment This bit field chooses the DMA request assignment for channel 4 0 DMA request line 0 triggers channel 4 1Fh DMA request line 31 triggers channel 4 20h 3Fh Reserved 23 22 Reserved 0 Reads...

Page 573: ...ssignment This bit field chooses the DMA request assignment for channel 8 0 DMA request line 0 triggers channel 8 1Fh DMA request line 31 triggers channel 8 20h 3Fh Reserved 23 22 Reserved 0 Reads ret...

Page 574: ...ignment This bit field chooses the DMA request assignment for channel 12 0 DMA request line 0 triggers channel 12 1Fh DMA request line 31 triggers channel 12 20h 3Fh Reserved 23 22 Reserved 0 Reads re...

Page 575: ...eserved 27 Reserved 0 Reads return 0 Writes have no effect 26 24 CH1PA These bit fields determine to which port channel 1 is assigned 1xx Port B 0xx Reserved 23 Reserved 0 Reads return 0 Writes have n...

Page 576: ...rved 27 Reserved 0 Reads return 0 Writes have no effect 26 24 CH9PA These bit fields determine to which port channel 9 is assigned 1xx Port B 0xx Reserved 23 Reserved 0 Reads return 0 Writes have no e...

Page 577: ...onds to channel 0 bit 1 corresponds to channel 1 and so on 0 The FTC interrupt of the corresponding channel is routed to Group A 1 The FTC interrupt of the corresponding channel is routed to Group B 1...

Page 578: ...to channel 0 bit 1 corresponds to channel 1 and so on 0 The HBC interrupt of the corresponding channel is routed to Group A 1 The HBC interrupt of the corresponding channel is routed to Group B 16 3 1...

Page 579: ...a channel is disabled Write No effect 1 Read or write The FTC interrupt of the corresponding channel is enabled 16 3 1 23 FTC Interrupt Enable Reset FTCINTENAR NOTE On this device Group B interrupts...

Page 580: ...and so on 0 Read The corresponding LFS interrupt of a channel is disabled Write No effect 1 Read or write The LFS interrupt of the corresponding channel is enabled 16 3 1 25 LFS Interrupt Enable Reset...

Page 581: ...nd so on 0 Read The HBC interrupt of the corresponding channel is disabled Write No effect 1 Read or write The HBC interrupt of the corresponding channel is enabled 16 3 1 27 HBC Interrupt Enable Rese...

Page 582: ...and so on 0 Read The BTC interrupt of the corresponding channel is disabled Write No effect 1 Read or write The BTC interrupt of the corresponding channel is enabled 16 3 1 29 BTC Interrupt Enable Res...

Page 583: ...One or more of the interrupt types FTC LFS HBC or BTC is pending on the corresponding channel 16 3 1 31 FTC Interrupt Flag Register FTCFLAG Figure 16 48 FTC Interrupt Flag Register FTCFLAG offset 124h...

Page 584: ...enable bit is cleared 0 Read An LFS interrupt of the corresponding channel is not pending Write No effect 1 Read An LFS interrupt of the corresponding channel is pending Write The flag is cleared 16 3...

Page 585: ...TC flags Bit 0 corresponds to channel 0 bit 1 corresponds to channel 1 and so on Note Reading from the respective interrupt channel offset register also clears the corresponding flag see Section 16 3...

Page 586: ...FTC interrupt Group A These bits contain the channel number of the pending interrupt for Group A if the corresponding interrupt enable is set Note Reading this location clears the corresponding interr...

Page 587: ...inued Bit Field Value Description 5 0 LFSA Channel causing LFS interrupt Group A These bits contain the channel number of the pending interrupt for Group A if the corresponding interrupt enable is set...

Page 588: ...HBC interrupt Group A These bits contain the channel number of the pending interrupt for Group A if the corresponding interrupt enable is set Note Reading this location clears the corresponding interr...

Page 589: ...inued Bit Field Value Description 5 0 BTCA Channel causing BTC interrupt Group A These bits contain the channel number of the pending interrupt for Group A if the corresponding interrupt enable is set...

Page 590: ...FTC interrupt Group B These bits contain the channel number of the pending interrupt for Group B if the corresponding interrupt enable is set Note Reading this location clears the corresponding interr...

Page 591: ...inued Bit Field Value Description 5 0 LFSB Channel causing LFS interrupt Group B These bits contain the channel number of the pending interrupt for Group B if the corresponding interrupt enable is set...

Page 592: ...HBC interrupt Group B These bits contain the channel number of the pending interrupt for Group B if the corresponding interrupt enable is set Note Reading this location clears the corresponding interr...

Page 593: ...inued Bit Field Value Description 5 0 BTCB Channel causing BTC interrupt Group B These bits contain the channel number of the pending interrupt for Group B if the corresponding interrupt enable is set...

Page 594: ...ed It can be used to determine if there is still data transferred while DMA_EN is set to 0 in GCTCRL In this case once all transfers are finished the flag will be set to 0 0 No transfers are pending 1...

Page 595: ...d RTC R 0 R WP 0 LEGEND R W Read Write R Read only WP Write in privilege mode only n value after reset Table 16 53 RAM Test Control RTCTRL Field Descriptions Bit Field Value Description 31 1 Reserved...

Page 596: ...es the channel number that causes the watch point to match 23 17 Reserved 0 Reads return 0 Writes have no effect 16 DMADBGS DMA debug status When a watch point is set up to watch for a unique bus addr...

Page 597: ...with the watch mask register WMR When the DBGEN bit in the DCTRL register is set and a unique address or a range of addresses are detected on the AHB address bus of Port B a debug request signal is se...

Page 598: ...ion 31 0 PBACSA 0 FFFF FFFFh Port B Active Channel Source Address This register contains the current source address of the active channel as broadcasted in Section 16 3 1 3 for Port B 16 3 1 50 Port B...

Page 599: ...EGEND R Read only n value after reset Table 16 59 Port B Active Channel Transfer Count Register PBACTC Field Descriptions Bit Field Value Description 31 29 Reserved 0 Reads return 0 Writes have no eff...

Page 600: ...diately If a frame on control packet x is processed at the time the parity error is detected then remaining elements of this frame will not be transferred anymore The DMA will be disabled regardless o...

Page 601: ...ns Bit Field Value Description 31 25 Reserved 0 Reads return 0 Writes have no effect 24 EDFLAG Parity Error Detection Flag This flag indicates if a parity error occurred on reading DMA Control packet...

Page 602: ...is routed to the VIM Group A 1 The interrupt is routed to the second CPU Group B 27 INT3ENA Interrupt enable of region 3 0 The interrupt is disabled 1 The interrupt is enabled 26 25 REG3AP Region 3 ac...

Page 603: ...cesses are allowed 1h Read only accesses are allowed 2h Write only accesses are allowed 3h No accesses are allowed 8 REG1ENA Region 1 enable 0 The region is disabled no address checking done 1 The reg...

Page 604: ...an access permission violation was detected in this region 0 Read No fault was detected Write No effect 1 Read A fault was detected Write The bit was cleared 23 17 Reserved 0 Reads return 0 Writes ha...

Page 605: ...3 1 57 DMA Memory Protection Region 0 End Address Register DMAMPR0E Figure 16 73 DMA Memory Protection Region 0 End Address Register DMAMPR0E offset 1BCh 31 16 ENDADDRESS R WP 0 15 0 ENDADDRESS R WP...

Page 606: ...3 1 59 DMA Memory Protection Region 1 End Address Register DMAMPR1E Figure 16 75 DMA Memory Protection Region 1 End Address Register DMAMPR1E offset 1C4h 31 16 ENDADDRESS R WP 0 15 0 ENDADDRESS R WP...

Page 607: ...3 1 61 DMA Memory Protection Region 2 End Address Register DMAMPR2E Figure 16 77 DMA Memory Protection Region 2 End Address Register DMAMPR2E offset 1CCh 31 16 ENDADDRESS R WP 0 15 0 ENDADDRESS R WP...

Page 608: ...3 1 63 DMA Memory Protection Region 3 End Address Register DMAMPR3E Figure 16 79 DMA Memory Protection Region 3 End Address Register DMAMPR3E offset 1D4h 31 16 ENDADDRESS R WP 0 15 0 ENDADDRESS R WP...

Page 609: ...e Following there is the detailed layout of these registers shown for control packet 0 16 3 2 1 Initial Source Address ISADDR Figure 16 80 Initial Source Address ISADDR offset 00 31 16 ISADDR R WP X 1...

Page 610: ...ield Value Description 31 29 Reserved 0 Reads are undefined Writes have no effect 28 16 IFTCOUNT 0 1FFFh Initial frame transfer count These bits define the number of frame transfers 15 13 Reserved 0 R...

Page 611: ...ted 10h Channel 15 is selected 11h 3Fh Reserved 15 14 RES Read element size 0 The element is byte 8 bit 1h The element is half word 16 bit 2h The element is word 32 bit 3h The element is double word 6...

Page 612: ...15 13 Reserved 0 Reads are undefined Writes have no effect 12 0 EIDXS 0 1FFFh Source address element index These bits define the offset to be added to the source address after each element transfer 1...

Page 613: ...rent source address These bits contain the current working absolute 32 bit source address physical These bits are only updated after a channel is arbitrated out from the priority queue 16 3 2 8 Curren...

Page 614: ...NT R X R X LEGEND R Read only n value after reset X Unknown Table 16 80 Current Transfer Count Register CTCOUNT Field Descriptions Bit Field Value Description 31 29 Reserved 0 Reads are undefined Writ...

Page 615: ...Incorporated External Memory Interface EMIF Chapter 17 SPNU503C March 2018 External Memory Interface EMIF This chapter describes the external memory Interface EMIF Topic Page 17 1 Introduction 616 17...

Page 616: ...synchronous memories to extend the memory access The EMIF module supports up to 3 chip selects EMIF_nCS 4 2 Each chip select has the following individually programmable attributes Data Bus Width Read...

Page 617: ...pyright 2018 Texas Instruments Incorporated External Memory Interface EMIF 17 1 3 Functional Block Diagram Figure 17 1 illustrates the connections between the EMIF and its internal requesters along wi...

Page 618: ...rocessed In some cases the EMIF will perform one or more auto refresh cycles before processing the request For details on the EMIF s internal arbitration between performing requests and performing aut...

Page 619: ...mmands to the device EMIF_CKE O Clock enable pin This pin is connected to the CKE pin of the attached SDRAM device and is used for issuing the SELF REFRESH command which places the device in self refr...

Page 620: ...t access READ Read The READ command outputs the starting column address and signals the SDRAM to begin the burst read operation Address EMIF_A 10 is always pulled low to avoid auto precharge This allo...

Page 621: ...Waveform of SDRAM PRE Command 17 2 5 2 Interfacing to SDRAM The EMIF supports a glueless interface to SDRAM devices with the following characteristics Pre charge bit is A 10 The number of column addr...

Page 622: ...Documentation Feedback Copyright 2018 Texas Instruments Incorporated External Memory Interface EMIF Figure 17 4 EMIF to 512K 16 2 bank SDRAM Interface Table 17 6 16 bit EMIF Address Pin Connections S...

Page 623: ...ntering power down mode NM Narrow Mode This bit defines the width of the data bus between the EMIF and the attached SDRAM device When set to 1 the data bus is set to 16 bits When set to 0 the data bus...

Page 624: ...RAM and Asynchronous interfaces are performed until this auto initialization is complete A write is performed to any of the three least significant bytes of the SDRAM configuration register SDCR An SD...

Page 625: ...d 1 Place the SDRAM into Self Refresh Mode by setting the SR bit of SDCR to 1 A byte write to the upper byte of SDCR should be used to avoid restarting the SDRAM Auto Initialization Sequence described...

Page 626: ...the RR field of SDRCR The two counters used to perform auto refresh cycles are a 13 bit refresh interval counter and a 4 bit refresh backlog counter At reset and upon writing to the RR field the refr...

Page 627: ...state by setting the SR bit of SDCR to 1 This will cause the EMIF to issue the SLFR command after completing any outstanding SDRAM access requests and clearing the refresh backlog counter by performin...

Page 628: ...e SDRAM are closed precharged prior to issuing the POWER DOWN command Therefore the EMIF only supports Precharge Power Down The EMIF does not support Active Power Down where internal banks of the SDRA...

Page 629: ...onfigured to 16 bit by setting the NM bit of the SDRAM configuration register SDCR to 1 a burst size of eight is used Figure 17 5 shows a burst size of eight The EMIF will truncate a series of burstin...

Page 630: ...e NM bit of the SDRAM configuration register SDCR to 1 a burst size of eight is used Figure 17 6 shows a burst size of eight Figure 17 6 Timing Waveform for Basic SDRAM Write Operation The EMIF will t...

Page 631: ...his method of traversal through the SDRAM banks helps maximize the number of open banks inside of the SDRAM and results in an efficient use of the device There is no limitation on the number of banks...

Page 632: ...ces The second mode of operation is Select Strobe Mode in which the EMIF_nCS 4 2 pins act as a strobe active only during the strobe period of an access In this mode the EMIF_nDQM pins of the EMIF func...

Page 633: ...8 bit asynchronous device the EMIF_BA 1 and EMIF_BA 0 pins provide the least significant bits of the halfword or byte address respectively Additionally when the EMIF interfaces to a 16 bit asynchrono...

Page 634: ...details on this mode of operation W_SETUP R_SETUP Read Write setup widths These fields define the number of EMIF clock cycles of setup time for the address pins EMIF_A and EMIF_BA byte enables EMIF_n...

Page 635: ...od MAX_EXT_WAIT Maximum Extended Wait Cycles This field configures the number of EMIF clock cycles the EMIF will wait for the EMIF_nWAIT pin to be deactivated during the strobe period of an access cyc...

Page 636: ...n was directly proceeded by a write operation and the TA field has been cleared to 0 one turn around cycle will be inserted After the EMIF has waited for the turnaround cycles to complete it again che...

Page 637: ...be Hold 2 3 2 Address Data Byte enable www ti com EMIF Module Architecture 637 SPNU503C March 2018 Submit Documentation Feedback Copyright 2018 Texas Instruments Incorporated External Memory Interface...

Page 638: ...ill its highest priority task If so the EMIF proceeds to the setup period of the operation If it is no longer the highest priority task the EMIF terminates the operation Start of the setup period The...

Page 639: ...old 2 3 2 Address Data Address Byte enable www ti com EMIF Module Architecture 639 SPNU503C March 2018 Submit Documentation Feedback Copyright 2018 Texas Instruments Incorporated External Memory Inter...

Page 640: ...nother read operation no turn around cycles are inserted If the current read operation was directly proceeded by a write operation and the TA field has been cleared to 0 one turn around cycle will be...

Page 641: ...old 2 3 2 Byte enables Address Data www ti com EMIF Module Architecture 641 SPNU503C March 2018 Submit Documentation Feedback Copyright 2018 Texas Instruments Incorporated External Memory Interface EM...

Page 642: ...urnaround cycles to complete it again checks to make sure that the write operation is still its highest priority task If so the EMIF proceeds to the setup period of the operation If it is no longer th...

Page 643: ...to the device data manual for details on the timing requirements of the EMIF_nWAIT signal The EMIF_nWAIT pin cannot be used to extend the strobe period indefinitely The programmable MAX_EXT_WAIT fiel...

Page 644: ...bled when using the asynchronous interface in Page mode Figure 17 14 Asynchronous Read in Page Mode 17 2 7 Data Bus Parking The EMIF always drives the data bus to the previous write data value when it...

Page 645: ...is not affected by the WPn bit in the asynchronous wait cycle configuration register AWCC The asynchronous time out interrupt condition occurs when the attached asynchronous device fails to deassert t...

Page 646: ...been enabled by writing a 1 to the AT_MASK_SET bit in INTMSKSET LT_MASKED This bit is set only when line trap interrupt occurs and the interrupt has been enabled by writing a 1 to the LT_MASK_SET bit...

Page 647: ...according to the following priority scheme highest priority listed first 1 If the EMIF s backlog refresh counter is at the Refresh Must urgency level the EMIF performs multiple SDRAM auto refresh cyc...

Page 648: ...a 16 bit data bus The maximum request size that the EMIF can be sent is 16 words therefore the maximum number of access cycles per memory request is 64 when the EMIF is configured with an 8 bit data b...

Page 649: ...es to follow when stopping the EMIF memory controller clocks 17 2 15 1 Power Management Using Self Refresh Mode The EMIF can be placed into a self refresh state in order to place the attached SDRAM de...

Page 650: ...ister Section 17 3 2 08h SDCR SDRAM Configuration Register Section 17 3 3 0Ch SDRCR SDRAM Refresh Control Register Section 17 3 4 10h CE2CFG Asynchronous 1 Configuration Register Section 17 3 5 14h CE...

Page 651: ...n is high 28 WP0 EMIF_nWAIT 0 polarity bit This bit defines the polarity of the EMIF_nWAIT 0 pin 0 Insert wait cycles if EMIF_nWAIT 0 pin is low 1 Insert wait cycles if EMIF_nWAIT 0 pin is high 27 24...

Page 652: ...ection 17 2 5 7 The field should be written using a byte write to the upper byte of SDCR to avoid triggering the SDRAM initialization sequence 0 Writing a 0 to this bit will cause connected SDRAM devi...

Page 653: ...h 7h Reserved 3 Reserved 0 Reserved The reserved bit location is always read as 0 If writing to this field always write the default value of 0 2 0 PAGESIZE Page Size This field defines the internal pa...

Page 654: ...G Field Descriptions Bit Field Value Description 31 SS Select Strobe bit This bit defines whether the asynchronous interface operates in Normal Mode or Select Strobe Mode See Section 17 2 6 for detail...

Page 655: ...ved The reserved bit location is always read as 0 If writing to this field always write the default value of 0 22 20 T_RCD 0 7h Specifies the Trcd value of the SDRAM This defines the minimum number of...

Page 656: ...ther command The SDSRETR is shown in Figure 17 21 and described in Table 17 31 Figure 17 21 SDRAM Self Refresh Exit Timing Register SDSRETR offset 3Ch 31 16 Reserved R 0 15 5 4 0 Reserved T_XS R 0 R W...

Page 657: ...eserved The reserved bit location is always read as 0 If writing to this field always write the default value of 0 2 WR Wait Rise This bit is set to 1 by hardware to indicate that a rising edge on the...

Page 658: ...as 0 If writing to this field always write the default value of 0 2 WR_MASKED Wait Rise Masked This bit is set to 1 by hardware to indicate a rising edge has occurred on the EMIF_nWAIT pin provided th...

Page 659: ...ET Wait Rise Mask Set This bit determines whether or not the wait rise Interrupt is enabled Writing a 1 to this bit sets this bit sets the WR_MASK_CLR bit in the EMIF interrupt mask clear register INT...

Page 660: ...ears this bit clears the WR_MASK_SET bit in the EMIF interrupt mask set register INTMSKSET and disables the wait rise interrupt To set this bit a 1 must be written to the WR_MASK_SET bit in INTMSKSET...

Page 661: ...1 3Fh Page access delay for NOR Flash connected on CS4 Number of EMIF_CLK cycles required for the page read data to be valid minus 1 cycle This value must not be cleared to 0 17 CS4_PG_SIZE Page Size...

Page 662: ...interface the EMIF with the Samsung K4S641632H TC L 70 SDRAM and the SHARP LH28F800BJE PTTL90 8Mb Flash memory 17 4 2 1 Configuring the SDRAM Interface This section describes how to configure the EMIF...

Page 663: ...CE nCAS nRAS nWE CLK CKE BA 1 BA 0 A 11 0 LDQM UDQM DQ 15 0 FLASH 512k x 16 A 0 A 12 1 DQ 15 0 nCE nWE nOE nRESET A 18 13 RY BY nBYTE0 nBYTE1 FLASH 512k x 16 A 0 A 12 1 DQ 15 0 nCE nWE nOE nRESET A 18...

Page 664: ...es tRC as the minimum auto refresh period 2 The Samsung datasheet does not specify a tWR value Instead Samsung specifies tRDL as last data in to row precharge minimum delay Table 17 38 SDTIMR Field Ca...

Page 665: ...value to program into the T_XS field of this register Based on this calculation a value of 6h should be written to SDSRETR Figure 17 29 shows how SDSRETR should be programmed 1 The Samsung datasheet d...

Page 666: ...lation of the proper value to program into the RR field of this register Based on this calculation a value of 61Ah should be written to SDRCR Figure 17 30 shows how SDRCR should be programmed Table 17...

Page 667: ...d The EMIF is now ready to perform read and write accesses to the SDRAM Table 17 41 SDCR Field Values For the EMIF to K4S641632H TC L 70 Interface Field Value Purpose SR 0 To avoid placing the EMIF in...

Page 668: ...to 1 to select a 16 bit interface The other fields in this register control the shaping of the EMIF signals and the proper values can be determined by referring to the AC Characteristics in the Flash...

Page 669: ...MHz 1 R_STROBE 9 35 R_STROBE 10 The R_HOLD field must be large enough to satisfy the EMIF Data hold time tH R_HOLD tH fEMIF_CLK 1 R_HOLD 1 ns 100 MHz 1 R_HOLD 0 9 The R_HOLD field must also combine w...

Page 670: ...TROBE W_HOLD tAVAV fEMIF_CLK 3 W_SETUP W_STROBE W_HOLD 90 ns 100 MHz 3 W_SETUP W_STROBE W_HOLD 6 Solving the above equations for the Write fields results in the following possible solution W_SETUP 1 W...

Page 671: ...8 Texas Instruments Incorporated Parameter Overlay Module POM Chapter 18 SPNU503C March 2018 Parameter Overlay Module POM This chapter describes the parameter overlay module POM Topic Page 18 1 Introd...

Page 672: ...t the overlay is mapped on to available memory ECC must be disabled by software through CP15 in case POM overlay is enabled otherwise ECC errors will be generated POM overlay must not be enabled when...

Page 673: ...tically inserted until the data is available from the overlay memory This ensures that the overlay memory has the same in the case that the latency from overlay memory is less than the program memory...

Page 674: ...ddress based on the overlay start address If the address falls into multiple overlapping regions the region with the lowest number has highest priority and only one read request from overlay memory wi...

Page 675: ...MSET POM Claim Set Register Section 18 3 9 FA4h POMCLAIMCLR POM Claim Clear Register Section 18 3 10 FB0h POMLOCKACCESS POM Lock Access Register Section 18 3 11 FB4h POMLOCKSTATUS POM Lock Status Regi...

Page 676: ...OTADDR 60h Overlay target Address These bits determine the upper address bits of the target overlay address Writing a different value to this field will steer the POM access to a different location i...

Page 677: ...d 0 Reads return 0 writes have no effect 27 16 FUNC A03h Indicates the SW compatible module family 15 11 RTL 0 RTL version number 10 8 MAJOR 1h Major revision number 7 6 CUSTOM 0 Indicates a device sp...

Page 678: ...0 Reserved TO R 0 R W1CP 0 LEGEND R W Read Write R Read only W1CP Write 1 to clear in privilege mode only n value after reset Table 18 5 POM Status Register POMFLG Field Descriptions Bit Field Value...

Page 679: ...ion The start address has to be a multiple of the region size NOTE If the region start address is programmed to a non region size boundary the region will begin at the next lower region size boundary...

Page 680: ...64 Bytes 2h 128 Bytes Dh 256 kBytes Eh Fh Reserved NOTE If the region is enabled by writing a non zero value to the SIZE bitfield it will take some number of VCLK cycles until the write takes effect...

Page 681: ...at another master is controlling the module Figure 18 11 POM Claim Set Register POMCLAIMSET address FFA0 4FA0h 31 16 Reserved R 0 15 2 1 0 Reserved SET1 SET0 R 0 R W 1 R W 1 LEGEND R W Read Write R Re...

Page 682: ...functionality of these bits is to indicate that another master is controlling the module Figure 18 12 POM Claim Clear Register POMCLAIMCLR address FFA0 4FA4h 31 16 Reserved R 0 15 2 1 0 Reserved CLR1...

Page 683: ...STATUS This is a CoreSight register and is for debug purpose only The register reads 00000000 Figure 18 14 POM Lock Status Register POMLOCKSTATUS address FFA0 4FB4h 31 0 Reserved R 0 LEGEND R Read onl...

Page 684: ...ld Descriptions Bit Field Value Description 31 0 Reserved 0 Reads return 0 writes have no effect 18 3 15 POM Device Type Register POMDEVTYPE This is a CoreSight register and is for debug purpose only...

Page 685: ...ND R W Read Write R Read only n value after reset Table 18 17 POM Peripheral ID 4 Register POMPERIPHERALID4 Field Descriptions Bit Field Value Description 31 8 Reserved 0 Reads return 0 writes have no...

Page 686: ...ly n value after reset Table 18 19 POM Peripheral ID 6 Register POMPERIPHERALID6 Field Descriptions Bit Field Value Description 31 0 Reserved 0 Reads return 0 writes have no effect 18 3 19 POM Periphe...

Page 687: ...s Bit Field Value Description 31 8 Reserved 0 Reads return 0 writes have no effect 7 0 Part Number 0 Reads 0 since POMREV defines the module 18 3 21 POM Peripheral ID 1 Register POMPERIPHERALID1 This...

Page 688: ...heral ID 2 Register POMPERIPHERALID2 Field Descriptions Bit Field Value Description 31 8 Reserved 0 Reads return 0 writes have no effect 7 4 Revision 0 Reads 0 since POMREV defines the module 3 JEDEC...

Page 689: ...gister POMCOMPONENTID0 Field Descriptions Bit Field Value Description 31 8 Reserved 0 Reads return 0 writes have no effect 7 0 Preamble Dh Preamble 18 3 25 POM Component ID 1 Register POMCOMPONENTID1...

Page 690: ...able 18 27 POM Component ID 2 Register POMCOMPONENTID2 Field Descriptions Bit Field Value Description 31 8 Reserved 0 Reads return 0 writes have no effect 7 0 Preamble 5h Preamble 18 3 27 POM Componen...

Page 691: ...gital converter ADC module Topic Page 19 1 Overview 692 19 2 Introduction 693 19 3 Basic Features and Usage of the ADC 696 19 4 Advanced Conversion Group Configuration Options 702 19 5 ADC Module Basi...

Page 692: ...ests for transferring conversion results Multichannel conversions performed in ascending order one channel at a time Single or continuous conversion modes Embedded self test logic for input channel fa...

Page 693: ...rs AIN AD REFHI AD REFLO V CCAD V SSAD Control Signals End Of Conversion Result VBUSP www ti com Introduction 693 SPNU503C March 2018 Submit Documentation Feedback Copyright 2018 Texas Instruments Inc...

Page 694: ...itched capacitor array during this period providing an inherent sample and hold function The sampling period ends one full ADCLK after the falling edge of the START signal The sequencer can control th...

Page 695: ...s three conversion groups for this purpose Group1 Group2 and the Event Group Any of the available analog input channels can be assigned to any of the conversion groups This also allows a particular ch...

Page 696: ...n time tACQG1 G1SAMP 11 0 2 in ADCLK cycles The minimum acquisition time is specified in the device datasheet This time also depends on the impedance of the circuit connected to the analog input chann...

Page 697: ...vent trigger is also configurable with a falling edge being the default An Event Group conversion starts when at least one channel is selected for conversion in this group and when the defined event t...

Page 698: ...range of addresses provided to facilitate the use of the ARM Cortex R4 CPU s Load Multiple LDM instruction A single read performed using the LDR instruction can also be used to read out a single conv...

Page 699: ...ted the channel id field of the conversion result reads as zeros Protection against reading from empty FIFO There is also a hardware mechanism to protect the application from reading past the number o...

Page 700: ...e to be read Benefit of reading conversion results directly from ADC RAM The application does not have to read out conversion results sequentially as in the case of reading from a FIFO As a result the...

Page 701: ...Write 1 to the ADC_EN bit of the Operating Mode Control Register ADOPMODECR to enable the ADC state machine 3 Configure the ADCLK frequency by programming the desired divider into the Clock Control R...

Page 702: ...fset Address Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x010 ADEVMODECR Reserved No Reset On ChnSel Reserved EV_ DATA_FMT Reserved EV_ CHID OVR_ EV...

Page 703: ...the group is set once all the channels in that group are converted For example say channels 0 2 4 and 6 are selected for conversion in Group1 in single conversion mode When the Group1 gets serviced t...

Page 704: ...ted the Event Group conversions start from where they were frozen While a group s conversions are frozen the group s STOP status bit is set This bit is cleared once the group s conversions are restart...

Page 705: ...O This control field is not effective when the application chooses to access the conversion result memory directly In that case the application can choose to mask off the number of bits as required 19...

Page 706: ...the CPU is interrupted This feature can be used to significantly reduce the CPU load when using interrupts for reading the conversion results The group s threshold register needs to be configured befo...

Page 707: ...ust be left cleared default if a DMA request is desired to be generated for new results getting written to the results memory 19 6 2 DMA Request for a Fixed Number of Conversion Results This mode is e...

Page 708: ...the conversion result can be masked off by writing 0xF to the interrupt comparison mask register allowing a gross comparison to be made By default the full 10 12 bit conversion results are compared 19...

Page 709: ...th minimum noise Calibration mode is enabled by setting the CAL_EN bit ADCALCR 0 The application needs to ensure that no conversion group is being serviced when the calibration mode is enabled The inp...

Page 710: ...calibration conversion When the calibration conversion is interrupted by an ADC enable ADC_EN 0 CAL_EN 1 and CAL_ST 1 a new conversion is automatically restarted as soon as the ADC enable bit is relea...

Page 711: ...rocess deviation Consequently the mid point voltage s accuracy can be affected due to the imperfections in the two resistors expected mismatch error is around 1 5 The switched reference voltage device...

Page 712: ...he Real function shown is a straight line between the ends points of the real staircase characteristic The Theoretical transfer function is for reference only straight line Transfer Function CPU MEMOR...

Page 713: ...rsion results However the next channel in the sequence is converted correctly during the additional self test cycle The logic associated with both self test and calibration is shown in Figure 19 13 Fi...

Page 714: ...al sampling capacitor throughout this extended acquisition period Figure 19 14 shows the self test mode timing when the ADREFLO is chosen as the reference voltage for the self test mode conversion It...

Page 715: ...s the enhanced power down mode of the ADC Once this bit is set the ADC module will power down the ADC core whenever there are no more ongoing or pending ADC conversions The ADC core will be powered do...

Page 716: ...DIS_EN bit of the group s ADSAMPDISEN register A discharge period for the sampling capacitor is added before the sampling period for each channel as shown in Figure 19 15 The duration of this discharg...

Page 717: ...32 bit reads and writes are allowed to the ADC results RAM in this test mode NOTE Contention on access to ADC Results RAM The ADC module cannot handle a contention between the application write to the...

Page 718: ...tionality www ti com 718 SPNU503C March 2018 Submit Documentation Feedback Copyright 2018 Texas Instruments Incorporated Analog To Digital Converter ADC Module Figure 19 16 ADC Memory Map in Parity Te...

Page 719: ...e enabled or disabled depending on bit PDIS in the pull disable register ADEVTPDIS Output buffer The ADxEVT pin can be driven as an output pin if the ADEVTDIR bit is set in the pin direction control r...

Page 720: ...up1 Interrupt Flag Register Section 19 11 15 3Ch ADG2INTFLG ADC Group2 Interrupt Flag Register Section 19 11 16 40h ADEVTHRINTCR ADC Event Group Threshold Interrupt Control Register Section 19 11 17 4...

Page 721: ...h ADG2SAMPDISEN ADC Group2 Sample Cap Discharge Control Register Section 19 11 53 128h 138h ADMAGINTxCR ADC Magnitude Compare Interrupt x Control Register Section 19 11 54 12Ch 13Ch ADMAGxMASK ADC Mag...

Page 722: ...le s internal state machines and the control status registers are reset 19 11 2 ADC Operating Mode Control Register ADOPMODECR Figure 19 19 and Table 19 7 describe the ADOPMODECR register Figure 19 19...

Page 723: ...Mode is enabled The application can directly write to the ADC RAM by the CPU or the DMA 15 9 Reserved 0 Read returns 0 Writes have no effect 8 POWERDOWN ADC Power Down This bit powers down only the A...

Page 724: ...datasheet specification Any operation mode read write t C ADCLK t C VCLK PS 4 0 1 where tC ADCLK is the period of the ADCLK and t C VCLK is the period of the VCLK 19 11 4 ADC Calibration Mode Control...

Page 725: ...de Table 19 1 defines the four different reference voltages that can be selected 8 HILO ADC Self Test mode and Calibration Mode Reference Source Selection In the ADC Self Test mode this bit defines th...

Page 726: ...Figure 19 22 12 bit ADC Event Group Operating Mode Control Register ADEVMODECR offset 10h 31 24 Reserved R 0 23 17 16 Reserved No Reset on ChnSel R 0 R W 0 15 10 9 8 Reserved EV_DATA_FMT R 0 R W 0 7...

Page 727: ...ult 3h Reserved The full 12 bit conversion result is returned if programmed Reserved 0 Reads return zeros writes have no effect EV_CHID Enable Channel Id for the Event Group conversion results to be r...

Page 728: ...continuously when the selected event trigger condition occurs FRZ_EV Event Group Freeze Enable This bit allows an Event Group conversion sequence to be frozen if a Group1 or a Group2 conversion is re...

Page 729: ...24 12 bit ADC Group1 Operating Mode Control Register ADG1MODECR offset 14h 31 24 Reserved R 0 23 17 16 Reserved No Reset on ChnSel R 0 R W 0 15 10 9 8 Reserved G1_DATA_FMT R 0 R W 0 7 6 5 4 3 2 1 0 Re...

Page 730: ...bit read performed in the read from RAM mode will return the 5 bit channel id along with the 10 bit conversion result Any operation mode read write 0 Bits 14 10 the channel id field of the data read...

Page 731: ...nuously FRZ_G1 Group1 Freeze Enable This bit allows a Group1 conversion sequence to be frozen if an Event Group or a Group2 conversion is requested The Group1 conversion is kept frozen while the Event...

Page 732: ...26 12 bit ADC Group2 Operating Mode Control Register ADG2MODECR offset 18h 31 24 Reserved R 0 23 16 Reserved No Reset on ChnSel R 0 R W 0 15 10 9 8 Reserved G2_DATA_FMT R 0 R W 0 7 6 5 4 3 2 1 0 Rese...

Page 733: ...6 bit read performed in the read from RAM mode will return the 5 bit channel id along with the 10 bit conversion result Any operation mode read write 0 Bits 14 10 the channel id field of the data read...

Page 734: ...inuously FRZ_G2 Group2 Freeze Enable This bit allows a Group2 conversion sequence to be frozen if an Event Group or a Group1 conversion is requested The Group2 conversion is kept frozen while the Even...

Page 735: ...This bit configures the event group to be triggered on both rising and falling edge detected on the selected trigger source Any operation mode read write 0 The conversion is triggered only upon detec...

Page 736: ...Select This bit configures the group1 to be triggered on both rising and falling edge detected on the selected trigger source Any operation mode read write 0 The conversion is triggered only upon det...

Page 737: ...Select This bit configures the group2 to be triggered on both rising and falling edge detected on the selected trigger source Any operation mode read write 0 The conversion is triggered only upon det...

Page 738: ...rated when conversion of all the channels selected for conversion in the Event Group is done 1 An Event Group conversion end interrupt is generated when conversion of all the channels selected for con...

Page 739: ...write 0 No interrupt is generated when conversion of all the channels selected for conversion in the Group1 is done 1 A Group1 conversion end interrupt is generated when conversion of all the channels...

Page 740: ...write 0 No interrupt is generated when conversion of all the channels selected for conversion in the Group2 is done 1 A Group2 conversion end interrupt is generated when conversion of all the channels...

Page 741: ...nt Group conversion end interrupt is generated if enabled when this bit gets set This bit can be cleared by any one of the following ways By writing a 1 to this bit By writing a 1 to the Event Group s...

Page 742: ...verted A Group1 conversion end interrupt is generated if enabled when this bit gets set This bit can be cleared by any one of the following ways By writing a 1 to this bit By writing a 1 to the Group1...

Page 743: ...verted A Group2 conversion end interrupt is generated if enabled when this bit gets set This bit can be cleared by any one of the following ways By writing a 1 to this bit By writing a 1 to the Group2...

Page 744: ...if new conversion results are not allowed to overwrite the existing memory contents then the Event Group threshold counter is not decremented Please refer to Section 19 5 2 for more details on the th...

Page 745: ...These bits always read the same as the bit 8 of this register 8 0 G2_THR Group2 Threshold Counter Before ADC conversions begin on the Group2 this field is initialized to the number of conversion resul...

Page 746: ...Threshold Control Register and the EV_BLOCKS field of the Event Group DMA Control Register are the same Any operation mode read write 0 No DMA transfer occurs even if EV_BLK_XFER is set to 1 1h 1FFh O...

Page 747: ...ister ADEVDMACR Field Descriptions continued Bit Field Value Description 0 EV_DMA_EN Event Group DMA Transfer Enable Any operation mode read 0 ADC module does not generate a DMA request when it writes...

Page 748: ...Threshold Control Register and the G1_BLOCKS field of the Group1 DMA Control Register are the same Any operation mode read write 0 No DMA transfer occurs even if G1_BLK_XFER is set to 1 1h 1FFh One D...

Page 749: ...l Register ADG1DMACR Field Descriptions continued Bit Field Value Description 0 G1_DMA_EN Group1 DMA Transfer Enable Any operation mode read 0 ADC module does not generate a DMA request when it writes...

Page 750: ...Threshold Control Register and the G2_BLOCKS field of the Group2 DMA Control Register are the same Any operation mode read write 0 No DMA transfer occurs even if G2_BLK_XFER is set to 1 1h 1FFh One D...

Page 751: ...l Register ADG2DMACR Field Descriptions continued Bit Field Value Description 0 G2_DMA_EN Group2 DMA Transfer Enable Any operation mode read 0 ADC module does not generate a DMA request when it writes...

Page 752: ...ion results The memory available is specified in terms of pairs of result buffers Any operation mode read write 0 Event Group conversions are not required If Event Group conversions are performed with...

Page 753: ...ization of the ADC results memory then the ADC results memory has been completely initialized to zeros For devices requiring parity checking on the ADC results memory the parity bit in the results mem...

Page 754: ...eeds to be guaranteed by configuring the EV_ACQ value properly considering the frequency of the ADCLK signal Please refer to the device datasheet to determine the minimum sampling time for this device...

Page 755: ...32 ADC Group2 Sampling Time Configuration Register ADG2SAMP Field Descriptions Bit Field Value Description 31 12 Reserved 0 Reads return zeros writes have no effect 11 0 G2_ACQ Group2 Acquisition Tim...

Page 756: ...ts memory is empty or does not contain any unread conversion results 2 EV_BUSY Event Group Conversion Busy Any operation mode read 0 Event Group conversions are neither in progress nor frozen 1 Event...

Page 757: ...oup1 results memory is empty or does not contain any unread conversion results 2 G1_BUSY Group1 Conversion Busy Any operation mode read 0 Group1 conversions are neither in progress nor frozen 1 Group1...

Page 758: ...oup2 results memory is empty or does not contain any unread conversion results 2 G2_BUSY Group2 Conversion Busy Any operation mode read 0 Group2 conversions are neither in progress nor frozen 1 Group2...

Page 759: ...Results Memory pointer to be reset so that the memory allocated for storing the Event Group conversion results gets overwritten Care should be taken to re program the corresponding Interrupt Threshold...

Page 760: ...ults Memory pointer to be reset so that the memory allocated for storing the Group1 conversion results gets overwritten Care should be taken to re program the corresponding Interrupt Threshold Counter...

Page 761: ...ults Memory pointer to be reset so that the memory allocated for storing the Group2 conversion results gets overwritten Care should be taken to re program the corresponding Interrupt Threshold Counter...

Page 762: ...ing on whether the ADC is configured to be in 12 bit or 10 bit resolution mode respectively Bits 11 10 are reserved when the module is configured as a 10 bit ADC module The ADC module writes the resul...

Page 763: ...Descriptions Bit Field Value Description 31 24 Reserved 0 Reads return zeros writes have no effect 23 0 LAST_CONV ADC Input Channel s Last Converted Value This register indicates whether the last con...

Page 764: ...Value Description Reserved 0 Reads return zeros writes have no effect EV_EMPTY Event Group FIFO Empty This bit is applicable only when the read from FIFO mode is used for reading the Event Group conve...

Page 765: ...ons Field Value Description Reserved 0 Reads return zeros writes have no effect G1_EMPTY Group1 FIFO Empty This bit is applicable only when the read from FIFO mode is used for reading the Group1 conve...

Page 766: ...ons Field Value Description Reserved 0 Reads return zeros writes have no effect G2_EMPTY Group2 FIFO Empty This bit is applicable only when the read from FIFO mode is used for reading the Group2 conve...

Page 767: ...W Read Write R Read only n value after reset U value after reset is unknown Table 19 45 ADC Event Group Results Emulation FIFO Register ADEVEMUBUFFER Field Descriptions Field Value Description Reserv...

Page 768: ...D R W Read Write R Read only n value after reset U value after reset is unknown Table 19 46 ADC Group1 Results Emulation FIFO Register ADG1EMUBUFFER Field Descriptions Field Value Description Reserved...

Page 769: ...D R W Read Write R Read only n value after reset U value after reset is unknown Table 19 47 ADC Group2 Results Emulation FIFO Register ADG2EMUBUFFER Field Descriptions Field Value Description Reserved...

Page 770: ...ed in Table 19 48 Figure 19 70 ADC ADEVT Pin Direction Control Register ADEVTDIR offset FCh 31 1 0 Reserved ADEVT_DIR R 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 19 48 ADC AD...

Page 771: ...This bit determines the logic level to be output to the ADEVT pin when the pin is configured to be an output pin Any operating mode read write 0 Output logic LOW on the ADEVT pin 1 Output logic HIGH o...

Page 772: ...lways returns the current state of the ADEVT pin Any operating mode read write 0 Output value on the ADEVT pin is unchanged 1 Output logic HIGH on the ADEVT pin if the pin is configured to be an outpu...

Page 773: ...the ADEVT pin if it is configured to be an output and a logic HIGH is being driven on to the pin Any operating mode read write 0 Output value on the ADEVT pin is logic HIGH 1 The ADEVT pin is tristat...

Page 774: ...egister ADEVSAMPDISEN is shown in Figure 19 78 and described in Table 19 56 Figure 19 78 ADC Event Group Sample Cap Discharge Control Register ADEVSAMPDISEN offset 11Ch 31 16 Reserved R 0 15 8 7 1 0 E...

Page 775: ...ster ADG1SAMPDISEN Field Descriptions Bit Field Value Description 31 16 Reserved 0 Reads return zeros writes have no effect 15 8 G1_SAMP_DIS_CYC Group1 sample cap discharge cycles These bits specify t...

Page 776: ...ster ADG2SAMPDISEN Field Descriptions Bit Field Value Description 31 16 Reserved 0 Reads return zeros writes have no effect 15 8 G2_SAMP_DIS_CYC Group2 sample cap discharge cycles These bits specify t...

Page 777: ...supports up to three magnitude compare interrupts These registers are at offset addresses 128h 130h and 138h Figure 19 81 12 bit ADC Magnitude Compare Interrupt x Control Registers ADMAGINTxCR offset...

Page 778: ...t is compared with the MAG_CHIDx channel s conversion result Reserved 0 Reads return zeros writes have no effect CHN_THR_COMPx Channel OR Threshold comparison Any operation mode read write 0 The ADC m...

Page 779: ...igure 19 83 12 bit ADC Magnitude Compare Interrupt x Mask Register ADMAGxMASK offset 12Ch 13Ch 31 12 11 0 Reserved MAG_INTx_MASK R 0 R W 0 LEGEND R W Read Write R Read only n value after reset Figure...

Page 780: ...ration mode read write for each bit 0 The enable status of the corresponding magnitude compare interrupt is left unchanged 1 The corresponding magnitude compare interrupt is enabled 19 11 57 ADC Magni...

Page 781: ...responding flag is cleared The flag can also be cleared by reading from the magnitude compare interrupt offset register 19 11 59 ADC Magnitude Compare Interrupt Offset Register ADMAGINTOFF ADC Magnitu...

Page 782: ...ion needs the Event Group memory to always be overwritten with the latest available conversion results then the OVR_EV_RAM_IGN bit in the Event Group operating mode control register ADEVMODECR needs t...

Page 783: ...to 1 As a result the G2_FIFO_RESET bit will always be read as a 0 The G2_FIFO_RESET bit will only have the desired effect when the Group2 results memory is in an overrun condition It must be used when...

Page 784: ...ill be stored This is specified in terms of the buffer number The application can read this register to determine the number of valid Group1 conversion results available until that time 19 11 65 ADC G...

Page 785: ...Descriptions Bit Field Value Description 31 9 Reserved 0 Reads return zeros writes have no effect 8 TEST This bit maps the parity bits into the ADC results RAM frame so that the application can acces...

Page 786: ...error generated in the ADC results RAM This error address is frozen from being updated until it is read by the application In emulation mode this address is maintained frozen even when read 1 0 Reserv...

Page 787: ...structions The N2HET micromachine is connected to a port of up to 32 input output I O pins NOTE This chapter describes a superset implementation of the N2HET module that includes features and function...

Page 788: ...memory with dedicated High End Timer Transfer Unit HTU or DMA Diagnostic capabilities with different loopback mechanisms and pin status readback functionality Hardware Angle Generator HWAG 20 1 2 Maj...

Page 789: ...solution prescaler HETPFR 5 0 Loop resolution prescaler HETPFR 10 8 Register S Register T HR clock to IO PIN CONTROL HR clock CURRENT INSTRUCTION HOST INTERFACE N2HET RAM SPECIALIZED TIMER MICROMACHIN...

Page 790: ...ce The total timer program is a set of instructions executed sequentially one after the other Reaching the end the program must roll to the first instruction so that it behaves as a loop The time for...

Page 791: ...son conditions Two additional 32 bit temporary working registers R S New HETAND register for AND Sharing of High Resolution structure between pairs of pins Improved high resolution PCNT instruction 20...

Page 792: ...ized timer micromachine The host interface and I O control provide an interface to the CPU and external pins respectively 20 2 1 Specialized Timer Micromachine The N2HET has its own instruction set de...

Page 793: ...rity 2 T o VIM Rotate Shift By N HETADDR 8 0 HETPRY 31 0 From N2HET RAM To I O Control Register T Register S CURRENT INSTRUCTION PROGRAM FIELD CONTROL FIELD DATA FIELD www ti com N2HET Functional Desc...

Page 794: ...s prefetched The program execution begins at the occurrence of the loop resolution clock and continues executing the instructions until the program branches to 00h location The instruction is prefetch...

Page 795: ...cutes linearly NOTE While it would be unusual to code an N2HET program that is only one instruction long it is trivial to modify such a program to meet the requirement of restriction 1 Simply add a se...

Page 796: ...nect to the device that has been already programmed with the N2HET code that needs to debugged downloading to on chip flash is outside the scope of this section 3 Execute the CPU program at least unti...

Page 797: ...o The N2HET will automatically start executing when it sees that the CPU has exited the debug state Figure 20 6 Debug Control Configuration NOTE Consecutive break points are not supported Instructions...

Page 798: ...et while the N2HET is executing from on the same address See Section 20 2 4 3 Except for the case of automatic read clear the external host is stalled when the host and N2HET have a bank conflict Howe...

Page 799: ...field whereby each is 32 bit wide So when fetching N2HET instructions parity checking is performed on three words in parallel If a parity error is detected in two or more words in the same cycle then...

Page 800: ...nitialized With parity enabled the N2HET parity RAM will be initialized automatically by N2HET at the same time that the N2HET instruction RAM is initialized by the CPU Note that loading the N2HET pro...

Page 801: ...me slots VCLK2 cycles required to complete the worst case execution path through the N2HET program Otherwise a program overflow condition may occur see Section 20 2 1 4 Because of the relationship of...

Page 802: ...an LRP within one N2HET loop LRP The last section showed that LRP lr HRP There are lr high resolution clock periods HRP within the N2HET loop resolution clock period LRP If lr 128 then the HR delay c...

Page 803: ...HET RAM In general a 64 bit read access of one master could be interrupted by a 64 bit read access of another master A total of three shadow registers are available Therefore up to three masters can p...

Page 804: ...r the CPU accesses to the timer RAM or control registers are freely executed Ignore suspend The timer RAM ignores the suspend signal and operates real time as normal 20 2 4 5 Power Down After setting...

Page 805: ...hich avoids the possible coherency problem of the read modify write approach Coding Example C program Set pins using the 2 methods unsigned int MASK Variable that content the bit mask volatile unsigne...

Page 806: ...the next loop resolution cycle the Z flag is evaluated and the opposite pin action is performed if it is set The Z flag will only be active for one loop resolution cycle Figure 20 10 Loop Resolution...

Page 807: ...nchronized to the next loop resolution cycle which HR function to perform and on which edges it should take an action with the information given by the instruction The HR structure for each pin decode...

Page 808: ...es N and N 1 are connected to pin N In this structure pin N 1 remains available for general purpose input output See Figure 20 12 Figure 20 12 Example of HR Structure Sharing for N2HET Pins 0 1 The fo...

Page 809: ...1 remains available for general purpose input output Figure 20 13 XOR shared HR I O The following N2HET program gives an example for one channel of the symmetrical PWM The generated timing is given in...

Page 810: ...T instruction needs to be set to the period of the symmetric counter The next two waveforms HR 0 and HR 1 show the output of the HR structures which are the inputs for the XOR gate to create the PWM o...

Page 811: ...back between the two structures in the structure pair is determined by the value of LBPDIR x in the HETLBPDIR Register For example if bit LBPSEL 0 is set to 1 then HR structures 0 and 1 will be intern...

Page 812: ...loopback mode the structure pairs are connected outside of the output buffers Therefore the loopback values WILL be seen on the corresponding pins Figure 20 17 shows an example of analog loopback bet...

Page 813: ...s Actual limitations will be slightly different due to on chip routing and IO buffer delays usually by several nanoseconds Be sure to consult the device datasheet for actual timings that apply to that...

Page 814: ...100000b Shifting this value right by 5 bits results in 10b which equals the two HR clock cycles delay mentioned above Figure 20 19 ECMP Execution Timings HETPFR 31 0 register 0x201 lr 4 and hr 2 ts 8...

Page 815: ...5 11 Pulse Generation Example in HR Mode The PWCNT instruction may also be used in HR mode to generate pulse outputs with HR width It generates a single pulse when the data field of the instruction is...

Page 816: ...t 2018 Texas Instruments Incorporated High End Timer N2HET Module Figure 20 21 shows what happens when the capture edge arrives after the HR counter overflows This causes the incremented value to be c...

Page 817: ...r is captured in the HR capture register and written into the RAM after the next WCAP execution The WCAP instruction effectively time stamps the free running timer saved in a register for example regi...

Page 818: ...pull up if the bit in the N2HET Pull Select Register HETPSL is cleared the pin will have a pull down If the bit in the N2HET Pull Disable Register HETPULDIS is set there is no pull up or pull down on...

Page 819: ...0 Disabled Disabled Disabled No 0 1 1 Disabled Disabled Enabled No 1 X X Disabled Enabled Enabled 20 2 5 15 Open Drain Feature The following apply if the open drain feature is enabled on a pin that i...

Page 820: ...ETDIN register of the GIO pin that the level on nDIS is inactive high Software sets bit HET_PIN_ENA to deactivate the high impedance state of the pins 20 2 6 Suppression Filters Each N2HET pin is equi...

Page 821: ...e address code for this flag is determined by the five LSBs of the current timer program address The flag in the N2HET Interrupt Flag Register HETFLG is set even if the corresponding bit in the N2HET...

Page 822: ...ciated with a priority level level 1 or level 2 When multiple interrupts with the same priority level occur during the same loop resolution the lowest flag bit is serviced first In addition to the int...

Page 823: ...set vector T o Vectored Interrupt Manager PL bit 0 SW Int flag 0 PL bit 1 SW Int flag 1 PL bit 23 SW Int flag 23 PL bit 24 SW Int flag 24 PL bit 31 SW Int flag 31 PL bit 34 ExcInt En 2 ExcInt flag 2 w...

Page 824: ...HTUREQ x or both signals shown in Figure 20 29 The request line number x corresponds to the reqnum parameter used in the instruction Figure 20 29 Request Line Assignment Example 20 3 Angle Functions...

Page 825: ...Functions 825 SPNU503C March 2018 Submit Documentation Feedback Copyright 2018 Texas Instruments Incorporated High End Timer N2HET Module Figure 20 30 Operation of N2HET Count Instructions Due to ste...

Page 826: ...ons of the external signal measured by APCNT and compensates related counting errors A period increase is flagged in the deceleration flag A period decrease is flagged in the acceleration flag If no v...

Page 827: ...ference signal can be masked The start and end of singularities are defined by gap start and gap end values specified in SCNT and ACNT When ACNT reaches gap start or gap end it sets resets the gap fla...

Page 828: ...period value accidentally falls below the minimum allowed APCNT stops the capture of these periods and sets the APCNT underflow interrupt flag located in the exceptions interrupt control register In...

Page 829: ...used has 60 teeth with 6 tooth the period between two tooth edges interpolates the angle value and the step width gives the number of interpolated angles For an example of the angle generator principl...

Page 830: ...CPU HWAG Angle Tick Generation Noise Filtering HET Interface HWAG core 4 2 Angle Functions www ti com 830 SPNU503C March 2018 Submit Documentation Feedback Copyright 2018 Texas Instruments Incorporate...

Page 831: ...which the HWAG global control register 2 HWAGCR2 defines as the falling or the rising edge of the input signal For an example of the angle tick generation principle see Figure 20 37 The speed of the t...

Page 832: ...signal The gap flag signal which changes the behavior of the HWAG during the singularity and resets the TCNT on the next active edge of the toothed wheel input The PCNT calculates the period P n betw...

Page 833: ...Instruments Incorporated High End Timer N2HET Module Figure 20 39 Angle Generation Using Time Based Algorithm Because of stepping the final count of the SCNT will usually be unequal to the target valu...

Page 834: ...icks like for a normal tooth but with three times the value To generate these angle ticks the HWAG uses a constant period based on the previous tooth period Because the period is based on the previous...

Page 835: ...cause the Gap flag 1 The tick counter is not reloaded because the Criteria flag is raised If PCNT n 2 x PCNT n 1 and the Gap flag 1 then the Criteria flag is raised The Gap flag and tooth active edge...

Page 836: ...corresponding interrupt you can also use the wired criteria When researching which algorithm to apply the counters ACNT and TCNT are frozen and must be initialized to their start values The ACNT valu...

Page 837: ...subroutine in code using the PCNT n 2 PCNT n 3 PCNT n 1 algorithm Figure 20 44 Code 20 3 2 2 3 Stopping the HWAG The HWAG starts synchronously with the active edge of the toothed wheel but stops when...

Page 838: ...tware must recover from such an interrupt to keep the HWAG operating optimally For an example of gap verification criteria for a 60 2 toothed wheel see Figure 20 45 Figure 20 45 Gap Verification Crite...

Page 839: ...the ACNT must be reset when it reaches the angle zero point To reset the ACNT when it reaches the angle zero point set the ARST bit to 1 Setting the ARST bit before the reload of the tick counter will...

Page 840: ...ounter The value of the remaining percentage of the tick counter 1 X need to be set because the tick counter is a down counter Calculate the value to put into the filter registers from the step width...

Page 841: ...s When conditions are set the HWAG interrupts are generated When the interrupt condition is true the corresponding flag is set in the HWAG interrupt flag register HWAFLG If the corresponding enable bi...

Page 842: ...mation on these interrupts see Table 20 14 Each interrupt source is associated with a low or high priority When one or more interrupts with the same priority occur a fixed priority determines the offs...

Page 843: ...ious one when the HWAG expects a normal tooth This interrupt can detect the singularity without bit manipulation by the CPU Bad active edge tooth This interrupt indicates that an active edge has occur...

Page 844: ...igh end timers This connection allows you to perform angle compare and angle time compare For an example of the hardware angle generator high end timer interface see Figure 20 50 Figure 20 50 Hardware...

Page 845: ...ion The NHET can then implement its own angle counter using a CNT instruction in angle mode which will be incremented once per resolution by the value given by the angle increment For an example of an...

Page 846: ...P instruction performs an in between comparison old angle value compare value new angle value to match the position of the toothed wheel This instruction where an equality compare executes every resol...

Page 847: ...ed to 1 20 3 2 4 3 2 HWAG to NHET Interface The NHET interface is a 11 bit counter sampled by the NHET and reset by the NHET resolution The counter contains the value of ACNT incremented during the la...

Page 848: ...ven SYSCLK RPM minimum is related to PCNT overflow and SYSCLK Maximum PCNT value SYSCLK Maximum tooth period PCNT is a 24 bit counter based on SYSCLK RPM maximum is related to the angle step and SYSCL...

Page 849: ...maximum angle accuracy is a function of the angle step and the NHET loop resolution The increment per resolution limits the interface between the HWAG and the NHET The maximum angle increment per NHET...

Page 850: ...the next falling edge Because of this compensation the NHET interface will not overflow and fewer errors will occur on the NHET angle counter in case of strong acceleration NOTE Reading the angle incr...

Page 851: ...4 11 2Ch HETAND AND Share Control Register Section 20 4 12 34h HETHRSH HR Share Control Register Section 20 4 13 38h HETXOR HR XOR Share Control Register Section 20 4 14 3Ch HETREQENS Request Enable S...

Page 852: ...ET RAM between the HET Transfer Unit and another arbiter which outputs the access of one of the remaining masters The MP bits allow the following selections 0 The HTU has lower priority to access the...

Page 853: ...erved 0 Reads return 0 Writes have no effect 0 TO Turn On Off TO does not affect the state of the pins You must set reset the timer pins when they are turned off or re initialize the timer RAM and con...

Page 854: ...0 LEGEND R W Read Write R Read only WP Write in privileged mode only n value after reset Table 20 17 Prescale Factor Register HETPFR Field Descriptions Bit Field Value Description 31 11 Reserved 0 Rea...

Page 855: ...address Write Writes have no effect 20 4 4 Offset Index Priority Level 1 Register HETOFF1 N2HET1 offset FFF7 B80Ch N2HET2 offset FFF7 B90Ch Figure 20 59 Offset Index Priority Level 1 Register HETOFF1...

Page 856: ...10h Figure 20 60 Offset Index Priority Level 2 Register HETOFF2 31 16 Reserved R 0 15 6 5 0 Reserved OFFSET2 R 0 R 0 LEGEND R Read only n value after reset Table 20 21 Offset Index Priority Level 2 Re...

Page 857: ...uction set Writing a 0 to HETINTENAS has no effect When reading from HETINTENAS bit x gives the information if N2HET instructions x 0 x 32 x 64 and so on have the interrupt enabled or disabled 0 Read...

Page 858: ...es have no effect 24 APCNT_OVRFL_ENA APCNT Overflow Enable 0 APCNT overflow exception is not enabled 1 Enables the APCNT overflow exception 23 17 Reserved 0 Reads return 0 Writes have no effect 16 APC...

Page 859: ...ped at a breakpoint Also generates a debug request to halt the ARM CPU 0 Read N2HET is either running or stopped flag cleared but not yet restarted Write No effect 1 Read N2HET is stopped at a breakpo...

Page 860: ...e R Read only W1C Write 1 to clear n value after reset X Unknown Table 20 27 Interrupt Flag Register HETFLG Field Descriptions Bit Field Value Description 31 0 HETFLAG n Interrupt Flag Register Bits B...

Page 861: ...8 AND SHARE7 6 AND SHARE5 4 AND SHARE3 2 AND SHARE1 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 20 28 AND Share Control Register HETAN...

Page 862: ...HR SHARE9 8 HR SHARE7 6 HR SHARE5 4 HR SHARE3 2 HR SHARE1 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 20 29 HR Share Control Register...

Page 863: ...XOR SHARE7 6 XOR SHARE5 4 XOR SHARE3 2 XOR SHARE1 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 20 30 XOR Share Control Register HETXOR...

Page 864: ...ne n Note The request line can trigger a DMA control packet DMA channel an HTU double control packet DCP or both simultaneously The HETREQDS register determines to which module s the N2HET request lin...

Page 865: ...ly n value after reset Table 20 33 Request Destination Select Register HETREQDS Field Descriptions Bit Field Value Description 31 24 Reserved 0 Reads return 0 Writes have no effect 23 16 TDBSn HTU DMA...

Page 866: ...Figure 20 73 N2HET Direction Register HETDIR 31 16 HETDIR R W 0 15 0 HETDIR R W 0 LEGEND R W Read Write R Read only n value after reset Table 20 34 N2HET Direction Register HETDIR Field Descriptions...

Page 867: ...at logic low 0 1 Pin HET n is at logic high 1 20 4 20 N2HET Data Output Register HETDOUT N2HET1 offset FFF7 B854h N2HET2 offset FFF7 B954h Figure 20 75 N2HET Data Output Register HETDOUT 31 16 HETDOUT...

Page 868: ...as logic 0 leave the same bit in HETDOUT unchanged Reads from this address return the value of the HETDOUT register 0 Write HETDOUT n is unchanged 1 Write HETDOUT n is set 20 4 22 N2HET Data Clear Reg...

Page 869: ...e of the output buffer HETDOUT n 0 The output buffer of pin HET n is driven low HETDOUT n 1 The output buffer of pin HET n is tristated 20 4 24 N2HET Pull Disable Register HETPULDIS Values in this reg...

Page 870: ...DIS is 0 1 The pull up functionality is enabled if corresponding bit in HETPULDIS is 0 NOTE See device data sheet for which pins provide programmable pullups pulldowns Table 20 9 shows how the registe...

Page 871: ...ffect 8 TEST Test Bit When this bit is set the parity bits are mapped into the peripheral RAM frame to make them accessible by the CPU 0 Read Parity bits are not memory mapped Write Disable mapping 1...

Page 872: ...ds the offset address of the first parity error which is detected in N2HET RAM This error address is frozen from being updated until it is read by the CPU During emulation mode this address is frozen...

Page 873: ...s Bit Field Value Description 31 0 HETPPR n NHET Parity Pin Select Bits Allows HET n pins to be configured to drive to a known state when an N2HET parity error is detected 0 Pin HET n is not affected...

Page 874: ...k and VCLK2 0 CCLK VCLK2 1h CCLK VCLK2 2 2h CCLK VCLK2 3 3h CCLK VCLK2 4 15 10 Reserved 0 Reads return 0 Writes have no effect 9 0 CPRLD Counter Preload Value CPRLD contains the preload value for the...

Page 875: ...19 18 LBPSEL17 16 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 7 6 5 4 3 2 1 0 LBPSEL15 14 LBPSEL13 12 LBPSEL11 10 LBPSEL9 8 LBPSEL7 6 LBPSEL5 4 LBPSEL3 2 LBPSEL1 0 R W 0 R W 0 R W 0 R W 0 R W 0 R...

Page 876: ...3 12 LBPDIR11 10 LBPDIR9 8 LBPDIR7 6 LBPDIR5 4 LBPDIR3 2 LBPDIR1 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 LEGEND R W Read Write R Read only WP Write in privileged mode only n value after rese...

Page 877: ...ster HETPINDIS 31 16 HETPINDIS R W 0 15 0 HETPINDIS R W 0 LEGEND R W Read Write R Read only n value after reset Table 20 50 NHET Pin Disable Register HETPINDIS Field Descriptions Bit Field Value Descr...

Page 878: ...20 5 6 B4h HWALVLSET HWAG Interrupt Level Set Register Section 20 5 7 B8h HWALVLCLR HWAG Interrupt Level Clear Register Section 20 5 8 BCh HWAFLG HWAG Interrupt Flag Register Section 20 5 9 C0h HWAOFF...

Page 879: ...alue after reset Table 20 52 HWAG Pin Select Register HWAPINSEL Field Descriptions Bit Field Value Description 31 5 Reserved 0 Reads return 0 Writes have no effect 4 0 PINSEL HWAG Pin Select Selects f...

Page 880: ...eturn 0 Writes have no effect 0 RESET HWAG Module Reset 0 HWAG module is reset 1 HWAG module is not in reset 20 5 3 HWAG Global Control Register 1 HWAGCR1 Figure 20 91 HWAG Global Control Register 1 H...

Page 881: ...HWAG generates an interruption singularity not found if the interrupt is enabled 0 Do not reset ACNT once it reaches the angle zero point 1 Reset ACNT once it reaches the angle zero point 23 18 Reserv...

Page 882: ...R W 0 LEGEND R W Read Write R Read only n value after reset Table 20 56 HWAG Interrupt Enable Set Register HWAENASET Field Descriptions Bit Field Value Description 31 8 Reserved 0 Reads return 0 Write...

Page 883: ...A6 CLRINTENA5 CLRINTENA4 CLRINTENA3 CLRINTENA2 CLRINTENA1 CLRINTENA0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 20 58 HWAG Interrupt En...

Page 884: ...effect 7 0 SETINTLVL n Set Interrupt Level See Table 20 57 0 Read Low priority interrupt Write No effect 1 Read High priority interrupt Write Set interrupt priority to high 20 5 8 HWAG Interrupt Leve...

Page 885: ...escription 31 8 Reserved 0 Reads return 0 Writes have no effect 7 0 INTFLG n Interrupt Flag These bit are set when an interrupt condition has occurred inside the HWAG The interrupt is sent to the CPU...

Page 886: ...register is the bit for which the corresponding interrupt enable bit is set During suspend mode a read to this register does not clear the corresponding interrupt bit Figure 20 98 HWAG Interrupt Offse...

Page 887: ...register is the bit for which the corresponding interrupt enable bit is set During suspend mode a read to this register does not clear the corresponding interrupt bit Figure 20 99 HWAG Interrupt Offse...

Page 888: ...G Angle Value Register HWAACNT 31 24 23 16 Reserved ACNT R 0 R W 0 15 0 ACNT R W 0 LEGEND R W Read Write R Read only n value after reset Table 20 64 HWAG Angle Value Register HWAACNT Field Description...

Page 889: ...Fh Period n 1 Value Gives the period value of the previous tooth 20 5 14 HWAG Current Tooth Period Value Register HWAPCNT Figure 20 102 HWAG Current Tooth Period Value Register HWAPCNT 31 24 23 16 Res...

Page 890: ...R W Read Write R Read only n value after reset Table 20 67 HWAG Step Width Register HWASTWD Field Descriptions Bit Field Value Description 31 4 Reserved Reads return 0 Writes have no effect 3 0 STWD...

Page 891: ...8 Reserved 0 Reads return 0 Writes have no effect 7 0 THNB 0 FFh Teeth Number Sets the teeth number with the maximum value of the toothed wheel This must be equal to N 1 real teeth that is 57 for a 6...

Page 892: ...h signal to be taken into account by the HWAG This function works only if the mode filtering is set The value is calculated as shown in Section 20 3 2 2 5 20 5 19 HWAG Filter Register 2 HWAFIL2 Figure...

Page 893: ...t Register HWAANGI 31 16 Reserved R 0 15 10 9 0 Reserved ANGI R 0 R 0 LEGEND R Read only n value after reset Table 20 72 HWAG Angle Increment Register HWAANGI Field Descriptions Bit Field Value Descri...

Page 894: ...rry and Shift 4h C 25 23 011 C5 1 1 3 ADD Add and Shift 4h C 25 23 001 C5 1 1 3 ADM32 Add Move 32 4h C 25 23 000 C5 1 1 2 AND Bitwise AND and Shift 4h C 25 23 010 C5 1 1 3 APCNT Angle Period Count Eh...

Page 895: ...P ACNT BR ECMP MCMP MOV32 RCNT SCMP SHFT X Angle Compare Match Flag ACMP SCMP SWF 0 1 Step Width flags SCNT ACNT NAF New Angle Flag ACNT NAF_global NAF_global New Angle Flag global HWAG or NAF ACMP BR...

Page 896: ...quest NOREQ request GENREQ and quiet request QUIET See Section 20 2 9 Default No request Location Control Field 28 27 Request C 28 C 27 To HTU To DMA NOREQ 0 0 no request no request 1 0 GENREQ 0 1 req...

Page 897: ...ilable for ACMP ADC ADD ADM32 AND DADM64 ECMP ECNT MCMP MOV32 MOV64 OR RADM64 SBB SHFT SUB WCAP WCAPE instructions Register Ext Reg C 7 C 2 C 1 A 0 0 0 B 0 0 1 T 0 1 0 None 0 1 1 R 1 0 0 S 1 0 1 Reser...

Page 898: ...A value of ON sets the previous pin level bit to 1 A value of OFF sets the initial value of the previous prv bit to 0 The prv bit is overwritten set or reset by the N2HET the first time the instructi...

Page 899: ...ol OFF ON en_pin_action OFF ON cond_addr label 9 bit unsigned integer pin pin number action CLEAR SET reg A B R S T NONE irq OFF ON data 25 bit unsigned integer Figure 20 109 ACMP Program Field P31 P0...

Page 900: ...upt is generated Specifying ON generates an interrupt when the edge state is satisfied and the gap flag is set Specifying OFF prevents an interrupt from being generated Default OFF data Specifies the...

Page 901: ...24 0 Res Request type Control Prv Gap End 3 2 1 1 25 Figure 20 114 ACNT Data Field D31 D0 31 7 6 0 Data Reserved 25 7 Cycles Two as follows First cycle Angle increment condition and gap end comparison...

Page 902: ...ge Select Rising 1 Detects a rising edge of HET 2 Falling 0 Detects a falling edge of HET 2 irq ON generates an interrupt when the edge state is satisfied and the gap flag is set OFF prevents an inter...

Page 903: ...1 If specified edge is detected on pin HET 2 DCF 0 If target_edge_field 0 AND DCF 0 ACF 1 If GPF 1 GPF 0 Z 1 If Interrupt Enable 1 HETFLG n 1 n depends on address If C28 C27 01 Generate request on req...

Page 904: ...ure 20 116 ADCNST Control Field C31 C0 31 27 26 25 24 0 Reserved Control Res Minimum offset 5 1 1 25 Figure 20 117 ADCNST Data Field D31 D0 31 7 6 0 Data HR Data 25 7 Cycles Two Register modified Regi...

Page 905: ...orated High End Timer N2HET Module Figure 20 118 and Figure 20 119 illustrate the behavior of ADCNST if the remote data field is zero or is not zero Figure 20 118 ADCNST Operation If Remote Data Field...

Page 906: ...Control Sub Opcode Src1 Src2 5 1 3 4 3 15 13 12 8 7 6 5 4 3 2 1 0 Smode Scount Ext Reg Init flag 1 Rdest Register select Res 3 5 1 1 1 2 2 1 Figure 20 122 ADC ADD AND OR SBB SUB XOR Data Field D31 D0...

Page 907: ...ation may be selected through the smode and scount operands The shift or rotate type is selected by the smode field Table 20 79 illustrates the options that are available for smode The number of bits...

Page 908: ...s the updated carry flag after the shift operation is performed s is the sign bit Table 20 79 Shift Encoding Shift Type C 15 13 smode Operation Illustrated 1 No Shift Applied 0 0 0 n a no shift ASR Ar...

Page 909: ...1 SRC1 31 0 0xFFFFFFFF case 1000 SRC1 31 0 Remote Data Field D 31 0 case 1001 SRC1 31 9 0 SRC1 8 0 Remote Program Field P 8 0 switch C18 C16 case 000 SRC2 31 0 0x00000000 case 001 SRC2 31 0 Immediate...

Page 910: ...OR IR1 31 OR IV1 case 011 smode Carry Shift Left IR2 31 scount IR1 31 scount 0 if scount 0 IR2 scount 1 0 IC1 IC1 IC2 IR1 31 scount 1 else IC2 IC1 IN2 IR2 31 if IR2 0 IZ2 1 else IZ2 0 IV2 IR2 31 XOR I...

Page 911: ...31 if IR2 0 IZ2 1 else IZ2 0 IV2 IR2 31 XOR IR1 31 OR IV1 WRITE REGISTER DESTINATION STAGE switch C7 C2 C1 case 000 A 24 0 IR2 31 8 case 001 B 24 0 IR2 31 8 case 010 T 31 0 IR2 31 0 case 011 IR2 is n...

Page 912: ...000 Reserved 5 1 3 15 15 8 7 6 5 4 3 2 1 0 Reserved Ext Reg Init flag 1 Move type Register select Res 15 1 1 1 2 2 1 Figure 20 125 ADM32 Data Field D31 D0 31 7 6 0 Data HR Data 25 7 Cycles One or two...

Page 913: ...R S or T Remote data field 1 If selected register is R S or T the operation is a 32 bit Addition move If A or B register is selected it is limited to 25 bit operation since A and B only support 25 bi...

Page 914: ...B R S or T 32 bits LSBs HR data field 25 32 bit addition move HR HR HR dashed for R S T dashed for R S T Instruction Set www ti com 914 SPNU503C March 2018 Submit Documentation Feedback Copyright 2018...

Page 915: ...1 1 25 Figure 20 130 APCNT Data Field D31 D0 31 7 6 0 Data Reserved 25 7 Cycles One or two cycles Cycle 1 edge detected normal operation Cycle 2 edge detected and GPF 1 and underflow condition is true...

Page 916: ...The edge select encoding is shown in Table 20 82 irq ON generates an interrupt when the edge state is satisfied OFF prevents an interrupt from being generated Default OFF type Specifies the edge type...

Page 917: ...od count 1FFFFFFh elseIf GPF 0 AND Data Field register Step width Register A Data field register 1 Register T Register A Period count Register T If Interrupt Enable 1 HETFLG n 1 n depends on address I...

Page 918: ...31 P0 31 26 25 23 22 21 13 12 9 8 0 0 Request Number BRK Next program address 1101 Reserved 6 3 1 9 4 9 Figure 20 132 BR Control Field C31 C0 31 29 28 27 26 25 24 22 21 16 Reserved Request type Contro...

Page 919: ...Z 0 0 1 0 1 Equal or Zero Z 1 NE NZ 0 0 1 1 1 Not Equal or Not Zero Z 0 N 0 1 0 0 1 Negative N 1 PZ 0 0 1 1 1 Positive or Zero N 0 V 0 1 1 0 1 Overflow V 1 NV 0 1 1 1 1 No Overflow V 0 ZN 1 0 0 0 1 Z...

Page 920: ...1 Figure 20 135 CNT Control Field C31 C0 31 29 28 27 26 25 24 0 Res Request type Control Res Max Count 3 2 1 1 25 Figure 20 136 CNT Data Field D31 D0 31 7 6 0 Data Reserved 25 7 Cycles One or two One...

Page 921: ...t to EQ the counter is reset when it is equal to the maximum count When set to GE the counter is reset when it is greater or equal to the maximum count Default GE irq ON generates an interrupt when th...

Page 922: ...3 If C28 C27 11 Generate quiet request on request line P25 P23 else Selected register Immediate Data Field Angle Increment Immediate Data Field Immediate Data Field Angle Increment else if Time mode b...

Page 923: ...d integer request NOREQ GENREQ QUIET control OFF ON en_pin_action OFF ON cond_addr label 9 bit unsigned integer pin pin number comp_mode ECMP SCMP MCMP1 MCMP2 action CLEAR SET PULSELO PULSEHI reg A B...

Page 924: ...trol field at the remote address The remote data field value is not just replaced but is added with the DADM64 data field DADM64 has two distinct syntaxes In the first syntax bit values may be set by...

Page 925: ...remote instruction action maintains the control field for the remote instruction irq maintains the control field for the remote instruction data Specifies the 25 bit initial value for the data field h...

Page 926: ...program address 1010 Res 10 Reserved 6 3 1 9 4 1 2 6 Figure 20 142 DJZ Control Field C31 C0 31 29 28 27 26 25 22 21 16 Reserved Request type Control Reserved Conditional address 3 2 1 4 9 15 13 12 8 7...

Page 927: ...r value used as a counter This counter is decremented each time the DJZ instruction is executed until the counter reaches 0 Default 0 Execution If Data 0 Data Selected register Data 1 Jump to Next Pro...

Page 928: ...er action CLEAR SET PULSELO PULSEHI reg A B R S T NONE irq OFF ON data 25 bit unsigned integer hr_data 7 bit unsigned integer Figure 20 144 ECMP Program Field P31 P0 31 26 25 23 22 21 13 12 9 8 7 6 0...

Page 929: ...oop resolution clock If the hr_lr bit is set the delay is ignored This delay is programmed in the data field D6 D0 The behavior of the pins is governed by the four action options in bits C4 C3 ECMP us...

Page 930: ...AT next loop resolution clock If Interrupt Enable 1 HETFLG n 1 n depends on address If C28 C27 01 Generate request on request line P25 P23 If C28 C27 11 Generate quiet request on request line P25 P23...

Page 931: ...21 16 Reserved Request type Control Prv Reserved Conditional address 3 2 1 1 3 9 15 13 12 8 7 6 4 3 2 1 0 Conditional address Pin select Ext Reg Event Res Register select Int ena 9 5 1 3 1 2 1 Figure...

Page 932: ...ion N irq ON generates an interrupt when event in counter mode occurs No interrupt is generated with OFF Default OFF data 25 bit integer value serving as a counter Default 0 Execution If event occurs...

Page 933: ...T PULSELO PULSEHI reg A B R S T NONE irq OFF ON data 25 bit unsigned integer hr_data 7 bit unsigned integer Figure 20 150 MCMP Program Field P31 P0 31 26 25 23 22 21 13 12 9 8 7 6 5 4 0 0 Request Numb...

Page 934: ...ompare Values The difference between the two data values must not exceed 224 1 angle_comp Determines whether or not an angle compare is performed A value of ON causes the comparison to be performed on...

Page 935: ...1 If hr_lr P 8 0 Schedule Action on Selected Pin C 12 8 at start of next loop HR Delay D 6 0 else Schedule Pin Action on Selected Pin C 12 8 at start of next loop If Interrupt Enable 1 HETFLG n 1 n de...

Page 936: ...0100 Remote Address 6 3 1 9 4 9 Figure 20 154 MOV32 Control Field C31 C0 31 27 26 25 23 22 21 16 Reserved Control Reserved Z Fl Cond Reserved 5 1 3 1 14 15 8 7 6 5 4 3 2 1 0 Reserved Ext Reg Init flag...

Page 937: ...angle flag NAF 0 A value of OFF results in no change to the system flags type Specifies the move type to be executed Table 20 87 Move Type Encoding Selection Move Type C4 C3 Source Destination s Cycl...

Page 938: ...field 25 32 bit move Immediate DF Register A B R S or T Remote DF HR HR HR dashed for R S T Instruction Set www ti com 938 SPNU503C March 2018 Submit Documentation Feedback Copyright 2018 Texas Instr...

Page 939: ...22 1 AND Z Flag 1 switch type C 4 3 case 00 IMTOREG Selected register Immediate Data Field case 01 IMTOREG REM Selected register Immediate Data Field Remote Data Field Immediate Data Field case 10 REG...

Page 940: ...integer request NOREQ GENREQ QUIET control OFF ON en_pin_action OFF ON cond_addr label 9 bit unsigned integer pin pin number comp_mode ECMP SCMP MCMP1 MCMP2 action CLEAR SET PULSELO PULSEHI reg A B R...

Page 941: ...syntax bit values may be set by assigning a value to each of the control fields This syntax is convenient for modifying control fields that are arranged similarly to the format of the MOV64 control f...

Page 942: ...tains the control field for the remote instruction data Specifies the 25 bit initial count value for the data field If omitted the field defaults to 0 hr_data Optional HR delay The default value for a...

Page 943: ...Int ena Type select hr_lr Pin select 6 3 1 9 4 1 2 1 5 Figure 20 165 PCNT Control Field C31 C0 31 29 28 27 26 25 24 0 Res Request type Control Prv Period Count 3 2 1 1 25 Figure 20 166 PCNT Data Fiel...

Page 944: ...ay Default 0 If period measure is selected PCNT captures the counter value into the period pulse data field D31 D7 on the selected edge The HR structure provides HR capture field D6 D0 The counter val...

Page 945: ...ue 1FF_FFFFh HR Capture Value selected HR counter else HR Capture Value 7Fh If Interrupt Enable 1 HETFLG n 1 n depends on address If C28 C27 01 Generate request on request line P25 P23 If C28 C27 11 G...

Page 946: ...r action CLEAR SET PULSELO PULSEHI reg A B T NONE irq OFF ON data 25 bit unsigned integer hr_data 7 bit unsigned integer Figure 20 167 PWCNT Program Field P31 P0 31 26 25 23 22 21 13 12 9 8 7 6 5 0 0...

Page 947: ...stays at zero until it is reloaded with a non zero value The specified pin action is performed as long as the count after count value is decremented is greater than 0 The opposite pin action is perfor...

Page 948: ...Data field value 1 Selected register 0000000h Data field value 0000000h If Opposite action 1 If hr_lr bit 0 If Enable Pin action 1 Selected Pin Opposite level of Pin Action AT next loop resolution clo...

Page 949: ...gned integer request NOREQ GENREQ QUIET control OFF ON en_pin_action OFF ON cond_addr label 9 bit unsigned integer pin pin number comp_mode ECMP SCMP MCMP1 MCMP2 action CLEAR SET PULSELO PULSEHI reg A...

Page 950: ...s also the next address Register modified None Description This instruction modifies the data field the HR data field and the control field at the remote address The advantage over DADM64 is that It e...

Page 951: ...instruction cond_addr Maintains the control field for the remote instruction pin Maintains the control field for the remote instruction register Maintains the control field for the remote instruction...

Page 952: ...an input period measurement TInput to the form of Equation 31 where the input period is expressed as a fraction of a reference period TReference 31 RCNT computes the numerator N of Equation 31 The den...

Page 953: ...struction detects a falling edge on pin 0 Between falling edges on pin0 RCNT accumulates counts 10x faster than PCNT so that the working data field of RCNT will reach the reference value of 0x400 in 1...

Page 954: ...Control Field C31 C0 31 29 28 27 26 25 24 23 22 21 16 Reserved Request type Control Cout prv Reserved En pin action Conditional address 3 2 1 1 2 1 9 15 13 12 8 7 6 5 4 3 2 1 0 Conditional address Pi...

Page 955: ...nce the LSB of the conditional address is used to select between time mode and angle mode and since the conditional address is taken only in time mode the destination for the conditional address must...

Page 956: ...ata Reserved 25 7 Cycles One or two cycles two cycles when DF is involved in the calculations Register modified Register A Description This instruction can be used only once in a program and defines a...

Page 957: ...NT stored in register T The resulting period of SCNT is P n 1 K Due to stepping the final count of SCNT will not usually exactly match the target p n 1 SCNT compensates for this error by starting each...

Page 958: ...umber BRK Next program address 1111 Reserved Smode 6 3 1 9 4 5 4 Figure 20 184 SHFT Control Field C31 C0 31 29 28 27 26 25 24 22 21 16 Reserved Request type Control Prv Reserved Conditional address 3...

Page 959: ...SB 1st on HETx 1 into LSB ORZ 0 1 0 0 Shift Out Right LSB 1st on HETx Z into MSB OLZ 0 1 0 1 Shift Out Left MSB 1st on HETx Z into LSB IRM 1 0 0 0 Shift In Right HETx into MSB ILL 1 0 0 1 Shift In Lef...

Page 960: ...f P3 P0 1011 Z MSB of the Immediate Data Field If Immediate Data Field all 0 s OR Immediate Data Field all 1 s if Interrupt Enable 1 HETFLG n 1 n depends on address Jump to Conditional Address else Ju...

Page 961: ...umber BRK Next program address 1011 hr_lr Reserved 6 3 1 9 4 1 8 Figure 20 187 WCAP Control Field C31 C0 31 29 28 27 26 25 24 22 21 16 Reserved Request type Control Prv Reserved Conditional address 3...

Page 962: ...ynchronize to the next loop clock When N2HET is turned on and a capture edge occurs in the first loop clock where the HR counter hasn t been synchronized to the loop clock then the captured HR counter...

Page 963: ...26 25 23 22 21 13 12 9 8 0 0 Request Number BRK Next program address 1000 Reserved 6 3 1 9 4 9 Figure 20 190 WCAPE Control Field C31 C0 31 29 28 27 26 25 24 23 22 21 16 Reserved Request type Control...

Page 964: ...eger value for D31 D7 Default 0 ec_data Specifies the initial 7 bit integer value for D6 D0 Default 0 Execution If Specified Capture Condition is true on Selected Pin OR Unconditional capture is selec...

Page 965: ...lized to transfer N2HET High End Timer data to or from the microcontroller RAM NOTE This chapter describes a superset implementation of the HTU module that includes features and functionality that req...

Page 966: ...to gather measurement data or creating output waveforms and thus freeing up the CPU to perform other tasks 21 1 1 Features Independently transfers data between the N2HET and the main memory 8 double c...

Page 967: ...initiates transfers with the help of requests generated by the N2HET program and configurable control packets Figure 21 1 shows a system block diagram of the HTU and the main path for the data transf...

Page 968: ...the data is transferred This serves as memory protection in the case that information in the control packet RAM was unintentionally altered and avoids that the HTU can overwrite important application...

Page 969: ...1 21 2 1 2 Single Buffer Implementation In a single buffer implementation the DCP is set up to transfer data to from a single buffer in the main RAM With each transfer request the programmed number o...

Page 970: ...20h 24h 3 2 1 28h 2Ch 30h end of buffer end of buffer 1 Buffer X 5 4 3 2 1 1 2 3 4 5 X X 15 14 13 12 11 10 9 8 15 15 15 15 15 15 7 6 5 4 3 2 1 TU request 1 Element Counter Element Number t1 t2 Increa...

Page 971: ...ouble control packets DCPs supporting the use of two buffers per data stream per HTU request source If one buffer should be read by the CPU or DMA the data stream is directed to the other buffer and t...

Page 972: ...me t3 then the frame is processed by the new control packet although the old control packet was active at the time of the request The delays between the HTU requests and the start of the element trans...

Page 973: ...t the HTU modifying the main memory It could happen that a request was already active but the frame transfer hasn t started yet when the application disabled the control packets The timing diagram in...

Page 974: ...stopped Accordingly the busy bit is cleared after the element which follows the element that caused the error In case of the Bus Error the counter for the element which follows the element that cause...

Page 975: ...o the N2HET loop LRP in which the N2HET updates the data fields of the L1 L2 and L3 instructions In this case the HTU could read inconsistent data as shown in the diagram A wrong new value is read fro...

Page 976: ...uest could also be used to define periods in which the data read by a control packet is safe The following HET code will capture counter time stamps to the L1 WCAP data field after rising edges at pin...

Page 977: ...P x will not be affected 5 The FT flag will be set 6 An error is signaled to the ESM module 21 2 6 Control Packet RAM Parity Checking The HTU module can detect parity errors in the DCP Double Control...

Page 978: ...memory Table 21 3 DCP RAM Bit 31 24 23 16 15 8 7 0 FF4E 0000h Byte 0 Byte 1 Byte 2 Byte 3 FF4E 0004h Byte 4 Byte 5 Byte 6 Byte 7 FF4E 0008h Byte 8 Byte 9 Byte 10 Byte 11 FF4E 000Ch Byte 12 Byte 13 Byt...

Page 979: ...ame PCNT instruction without loading or interrupting the CPU 21 3 2 Example Multiple Element Transfer with One Trigger Request The following example shows how the HTU could be used to fill a RAM buffe...

Page 980: ...t Counter 3 2 1 3 2 1 3 2 1 Source Address HET 38h 48h 58h 38h 48h 58h 38h 48h 58h Destination Address main CPU RAM 70h 74h 78h 7Ch 80h 84h 88h 8Ch 90h The destination buffer is filled with the WCAP E...

Page 981: ...as shown on the right in Table 21 9 Table 21 9 Destination Buffer Values Address Frame Count Instruction Value 70h 3 WCAP Control Field Value 74h 3 WCAP 3 78h 3 ECNT Control Field Value 7Ch 3 ECNT 1...

Page 982: ...and Bus Error Control Register Section 21 4 8 24h HTU BFINTS Buffer Full Interrupt Enable Set Register Section 21 4 9 28h HTU BFINTC Buffer Full Interrupt Enable Clear Register Section 21 4 10 2Ch HTU...

Page 983: ...d to 0 and the parity functionality must be enabled by PARITY_ENA during the automatic DCP RAM initialization see Initializing Parity Bits If HTUEN is 1 when the initialization is triggered by the sys...

Page 984: ...led simultaneously 1 0 CP B is enabled and CP A are disabled simultaneously 1 1 CP B and CP A are both disabled simultaneously Table 21 14 CPENA Read Results Bit 2 x 1 Bit 2 x State of DCP 0 0 The DCP...

Page 985: ...Flag for CP B of DCP 0 15 9 Reserved 0 Reads return 0 Writes have no effect 8 BUSY1A Busy Flag for CP A of DCP 1 7 1 Reserved 0 Reads return 0 Writes have no effect 0 BUSY1B Busy Flag for CP B of DCP...

Page 986: ...lag for CP B of DCP 2 15 9 Reserved 0 Reads return 0 Writes have no effect 8 BUSY3A Busy Flag for CP A of DCP 3 7 1 Reserved 0 Reads return 0 Writes have no effect 0 BUSY3B Busy Flag for CP B of DCP 3...

Page 987: ...BUSY7A Busy Flag for CP A of DCP 7 7 1 Reserved 0 Reads return 0 Writes have no effect 0 BUSY7B Busy Flag for CP B of DCP 7 21 4 7 Active Control Packet and Error Register HTU ACPE Figure 21 20 Activ...

Page 988: ...PN is frozen from being updated until the upper 16 bit word of the ACPE register or the complete 32 bit register is read by the CPU After this read the HTU will update ERRCPN if one of the above condi...

Page 989: ...NTENA Bus Error Interrupt Enable Bit 0 The bus error interrupt is disabled for all DCPs 1 The bus error interrupt is enabled for all DCPs 15 9 Reserved 0 Reads return 0 Writes have no effect 8 CORL Co...

Page 990: ...r A is full that is once the frame counter CFTCTA decrements to 0 The same applies for CP B and CFTCTB 0 Interrupt is disabled Writing a 0 has no effect 1 Writing to bit 2 x enables the interrupt for...

Page 991: ...ffect 16 MAPSEL Interrupt Mapping Select Bit 0 If MAPSEL is 0 then one bit of CPINTMAP selects one of two interrupt priorities 0 or 1 for the buffer full interrupt for the according CP The request los...

Page 992: ...errupt Line 0 Indicates whether a buffer full RLOST or BER interrupt assigned to interrupt line 0 is currently pending 0 No interrupt 1h Interrupt caused by full buffer on CP DCP specified by CPOFF0 2...

Page 993: ...whether a buffer full RLOST or BER interrupt assigned to interrupt line 1 is currently pending 0 No interrupt 1h Interrupt caused by full buffer on CP DCP specified by CPOFF1 2h RLOST interrupt genera...

Page 994: ...A buffer is initialized In circular buffer transfer mode defined by TMBx when the end of the buffer is reached When CPs are switched or enabled according to Buffer Initialization The CPENA bits 2 x 1...

Page 995: ...ed for the cases E and F and not for all the other cases shown in Table 21 27 Also when a buffer reaches its end in circular mode it uses the initial DCP information to restart independently of the BI...

Page 996: ...r Full Interrupt Flag Register HTU BFINTFL offset 44h 31 16 Reserved R 0 15 0 BFINTFL R W1CP 0 LEGEND R W Read Write R Read only W1CP Write 1 in privilege mode to clear the bit n value after reset Tab...

Page 997: ...rite R Read only W1CP Write 1 in privilege mode to clear the bit n value after reset Table 21 30 BER Interrupt Flag Register HTU BERINTFL Field Descriptions Bit Field Value Description 31 16 Reserved...

Page 998: ...accesses an address smaller than STARTADDRESS1 and the MPCS bit REG01ENA register is configured accordingly The address is 32 bit aligned so the 2 LSBs are not significant and will always read 0 21 4...

Page 999: ...of DCP0 2h CP A of DCP1 3h CP B of DCP1 4h CP A of DCP2 5h CP B of DCP2 6h CP A of DCP3 7h CP B of DCP3 8h CP A of DCP4 9h CP B of DCP4 Ah CP A of DCP5 Bh CP B of DCP5 Ch CP A of DCP6 Dh CP B of DCP6...

Page 1000: ...set then the application code execution is stopped This register can only be programmed during debug mode This register and all other bits of the DCTRL and WMR registers are reset by the test reset nT...

Page 1001: ...Class Subtype Number R Module Revision Number LEGEND R Read only n value after reset Table 21 36 Module Identification Register HTU ID Field Descriptions Bit Field Value Description 31 24 Reserved 0...

Page 1002: ...then the DCP x will automatically be disabled in the CPENA register If a frame is active on DCP x during this read access then in addition the element counter of DCP x is cleared and all new element t...

Page 1003: ...ity error and parity checking is enabled 0 No fault is detected 1 Fault is detected Note Once PEFT is set a read access to the lower 16 bits or to the complete 32 bit HTUPAR register will clear the PE...

Page 1004: ...irst memory protection error when only one memory protection region is used This number is not updated for multiple access violations until it is read by the CPU During debug mode CPNUM0 is frozen eve...

Page 1005: ...ess is allowed but write access will be signaled 1 Any access performed by the HTU is forbidden and will be signaled 3 REG01ENA Region Enable 01 This bit needs to be set when working with two memory m...

Page 1006: ...ined by the MP0S and MP0E registers is not enabled This means the HTU can access any implemented memory space 1 The protection outside the memory region defined by the MP0S and MP0E registers is enabl...

Page 1007: ...the HTU accesses an address smaller than STARTADDRESS0 and the MPCS register is configured accordingly The address is 32 bit aligned so the 2 LSBs are not significant and will always read 0 21 4 28 Me...

Page 1008: ...DCP0 ITCOUNT Initial Transfer Count Register Section 21 5 4 10h HTU DCP1 IFADDRA Initial Full Address A Register Section 21 5 1 14h HTU DCP1 IFADDRB Initial Full Address B Register Section 21 5 2 18h...

Page 1009: ...iption 31 0 IFADDRA Initial Address of Buffer A in main memory Initial byte address of buffer A placed in the main memory address range Bits 0 and 1 are ignored by the logic due to 32 bit alignment 21...

Page 1010: ...rred 21 ADDMH Addressing Mode N2HET Address This bit determines the N2HET address index from one to the next element of a frame 0 Increment by 16 bytes Examples If the initial N2HET address points to...

Page 1011: ...required for the actual N2HET RAM size If the N2HET address exceeds the actual N2HET RAM size the unused MSB bits of the address will be ignored and the address rolls over to the start of the N2HET R...

Page 1012: ...re to find out the recently transferred element in the frozen buffer while the address of the active buffer increments Note A frame can be automatically stopped if any of the events listed in Conditio...

Page 1013: ...software to find out the recently transferred element in the frozen buffer while the address of the active buffer increments Note A frame can be automatically stopped if any of the events listed in Co...

Page 1014: ...48 Current Frame Count Register HTU CFCOUNT 31 24 23 16 Reserved CFTCTA R 0 R WP X 15 8 7 0 Reserved CFTCTB R 0 R WP X LEGEND R W Read Write R Read only WP Write in privilege mode only n value after r...

Page 1015: ...d is determined by the time of the interrupt determined by the frequency of the N2HET transfer requests 21 6 2 Software Example Sequence Assuming Circular Mode for Both CP A and B The example assumes...

Page 1016: ...After reading the CPU does not need to clear the frozen buffer B After some time the CPU intends to read buffer A A1 see above NOTE The buffer full interrupt doesn t need to be enabled The BFINTFL fl...

Page 1017: ...he general purpose input output GIO module The GIO module provides the family of devices with input output I O capability The I O pins are bidirectional and bit programmable The GIO module also suppor...

Page 1018: ...on The GIO module also supports generation of interrupts whenever a rising edge or falling edge or any toggle is detected on up to 32 of these GIO terminals Refer to the device datasheet for identifyi...

Page 1019: ...ding bits in to GIOPSL to 1 Read corresponding bits in GIODIN getting input value Write 1 to corresponding bits inGIODSET Write 1 to corresponding bits in GIODCLR www ti com Quick Start Guide 1019 SPN...

Page 1020: ...l High level Write 1 to corresponding bits in to enable interrupt GIOENASET Write 0xFF to clean the GIO interrupt flag register GIOFLG Enable Peripherals by setting PENA bit in Clock Control Register...

Page 1021: ...OUT Configures the logic level to be output on GIO terminal s configured as outputs A low value 0 written to the data output register forces the pin to a low output voltage V OL or lower A high value...

Page 1022: ...n the selected GIO pin s that is are used to generate interrupt s rising falling both Rising or falling edge can be selected via the GIOPOL register If interrupt is required to be generated on both ri...

Page 1023: ...pt handling 1 High level level A interrupt handling 1 To VIM To VIM www ti com Functional Description of GIO Module 1023 SPNU503C March 2018 Submit Documentation Feedback Copyright 2018 Texas Instrume...

Page 1024: ...ring the flags During emulation mode External interrupts are not captured because the VIM is unable to service interrupts Any register can be read without affecting the state of the system A write to...

Page 1025: ...O Interrupt Enable Clear Register Section 22 5 4 2 18h GIOLVLSET GIO Interrupt Priority Set Register Section 22 5 5 1 1Ch GIOLVLCLR GIO Interrupt Priority Clear Register Section 22 5 5 2 20h GIOFLG GI...

Page 1026: ...any other register of the GIO module Figure 22 5 and Table 22 2 describe this register Figure 22 5 GIO Global Control Register GIOGCR0 offset 00h 31 16 Reserved R 0 15 1 0 Reserved RESET R 0 R WP 0 LE...

Page 1027: ...NTDET 3 Interrupt detection select for pins GIOD 7 0 0 The flag sets on either a falling or a rising edge on the corresponding pin depending on the polarity setup in the polarity register GIOPOL 1 The...

Page 1028: ...ponding pin Low power mode GIO module clocks off 0 The interrupt is triggered on the low level 1 The interrupt is triggered on the high level 23 16 GIOPOL 2 Interrupt polarity select for pins GIOC 7 0...

Page 1029: ...rupt Enable Set Register GIOENASET offset 10h 31 24 23 16 GIOENASET 3 GIOENASET 2 R W 0 R W 0 15 8 7 0 GIOENASET 1 GIOENASET 0 R W 0 R W 0 LEGEND R W Read Write n value after reset Table 22 5 GIO Inte...

Page 1030: ...lue Description 31 24 GIOENACLR 3 Interrupt disable for pins GIOD 7 0 0 Read The interrupt is disabled Write Writing a 0 to this bit has no effect 1 Read The interrupt is enabled Write Disables the in...

Page 1031: ...1 16 GIOLVLSET 3 GIOLVLSET 2 R W 0 R W 0 15 8 7 0 GIOLVLSET 1 GIOLVLSET 0 R W 0 R W 0 LEGEND R W Read Write n value after reset Table 22 7 GIO Interrupt Priority Register GIOLVLSET Field Descriptions...

Page 1032: ...ld Value Description 7 0 GIOLVLSET 0 GIO high priority interrupt for pins GIOA 7 0 0 Read The interrupt is a low level interrupt The low level interrupts are recorded to GIOOFF2 and GIOEMU2 Write Writ...

Page 1033: ...GIOEMU1 Write Sets the interrupt as a low level interrupt The low level interrupts are recorded to GIOOFF2 and GIOEMU2 23 16 GIOLVLCLR 2 GIO low priority interrupt for pins GIOC 7 0 0 Read The interr...

Page 1034: ...in the appropriate offset register 23 16 GIOFLG 2 GIO flag for pins GIOC 7 0 0 Read A transition has not occurred since the last clear Write Writing a 0 to this bit has no effect 1 Read The selected t...

Page 1035: ...y pending interrupt The application can choose to service all GIO interrupts from the same service routine by continuing to read the GIOOFF1 register until it reads zeros Figure 22 13 GIO Offset 1 Reg...

Page 1036: ...rity pending interrupt The application can choose to service all GIO interrupts from the same service routine by continuing to read the GIOOFF1 register until it reads zeros Figure 22 14 GIO Offset 2...

Page 1037: ...r GIOEMU1 offset 2Ch 31 16 Reserved R 0 15 6 5 0 Reserved GIOEMU1 R 0 R 0 LEGEND R Read only n value after reset Table 22 12 GIO Emulation 1 Register GIOEMU1 Field Descriptions Bit Field Value Descrip...

Page 1038: ...ister GIOEMU2 offset 30h 31 16 Reserved R 0 15 6 5 0 Reserved GIOEMU2 R 0 R 0 LEGEND R Read only n value after reset Table 22 13 GIO Emulation 2 Register GIOEMU2 Field Descriptions Bit Field Value Des...

Page 1039: ...1 8 Reserved 0 Reads return 0 Writes have no effect 7 0 GIODIR n GIO data direction of port n pins 7 0 0 The GIO pin is an input Note If the pin direction is set as an input the output buffer is trist...

Page 1040: ...o logic low 0 1 The pin is driven to logic high 1 Note Output is in high impedance state if the GIOPDRx bit 1 and GIODOUTx bit 1 Note GIO pin is placed in output mode by setting the GIODIRx bit to 1 2...

Page 1041: ...1 Write The corresponding GIO pin is driven to logic low 0 Note The current logic state of the GIODOUT bit will also be displayed by this bit Note GIO pin is placed in output mode by setting the GIODI...

Page 1042: ...e GIO pin configured as an input pin 0 The pull functionality is enabled 1 The pull functionality is disabled Note The GIO pin is placed in input mode by clearing the GIODIRx bit to 0 22 5 18 GIO Pull...

Page 1043: ...isabling pull control 5 GIOPSL 0 for pull down functionality 1 for pull up functionality 6 If open drain is enabled output buffer will be disabled if a high level 1 is being output Table 22 22 Output...

Page 1044: ...the number of instantiations of the DCAN IP and the number of mailboxes supported on your specific device being used Topic Page 23 1 Overview 1045 23 2 CAN Blocks 1046 23 3 CAN Bit Timing 1048 23 4 C...

Page 1045: ...es for self test operation Direct access to Message RAM in test mode Supports Two interrupt lines Level 0 and Level 1 Others Automatic Message RAM initialization Automatic bus on after Bus Off state b...

Page 1046: ...ule shown in Figure 23 1 comprises of the following basic blocks 23 2 1 CAN Core The CAN Core consists of the CAN Protocol Controller and the Rx Tx Shift Register It handles all ISO 11898 1 protocol f...

Page 1047: ...ated clock output from FMPLL is used as the VCLK source then VCLKA should be derived from an unmodulated clock source for example OSCIN source The clock source for VCLKA is selected by the Peripheral...

Page 1048: ...Each segment consists of a specific number of time quanta The length of one time quantum tq which is the basic time unit of the bit time is given by the CAN_CLK and the Baud Rate Prescalers BRPE and B...

Page 1049: ...nts Edges are detected by sampling the actual bus level in each time quantum and comparing it with the bus level at the previous sample point A synchronization may be done only if a recessive bit was...

Page 1050: ...t of 8 to 25 time quanta The length of the time quantum tq is defined by the Baud Rate Prescaler with tq Baud Rate Prescaler CAN_CLK Several combinations may lead to the desired bit time allowing iter...

Page 1051: ...2 delays 1 7 tq tSJW 100 ns 1 tq tTSeg1 800 ns tProp tSJW tTSeg2 100 ns Information Processing Time 1 tq tSync Seg 100 ns 1 tq bit time 1000 ns tSync Seg tTSeg1 tTSeg2 tolerance for CAN_CLK 1 58 34 3...

Page 1052: ...ters in the system module 1 Memory Hardware Initialization Global Control Register MINITGCR 2 Memory Initialization Enable Register MSINENA For more details on RAM hardware initialization support refe...

Page 1053: ...r BTR value calculation for a given bit timing Step 5 Clear the CCE bit followed by Init bit Step 6 Wait for the Init bit to clear This would make sure that the module has come out of initialization m...

Page 1054: ...Mask bits are used for acceptance filtering Note If the UMask bit is set to 1 the message object s mask bits have to be programmed during initialization of the message object before MsgVal is set to 1...

Page 1055: ...me 1 IntPnd will be triggered after the successful transmission of a frame IntPnd Interrupt Pending 0 This message object is not the source of an interrupt 1 This message object is the source of an in...

Page 1056: ...RAM Addressing in Debug Suspend and RDA Mode Message Object Number Base Address Offset Word Number Debug Suspend mode see Section 23 5 3 RDA mode see Section 23 5 4 1 0x0020 1 Parity Data Bytes 4 7 0...

Page 1057: ...Mode Test bit in CAN control register is set the CPU has direct access to the Message RAM Due to the 32 bit bus structure the RAM is split into word lines to support this feature The CPU has access to...

Page 1058: ...ee Section 23 5 4 For the Message RAM Base address please refer to the device datasheet A complete message object see Section 23 5 1 or parts of the message object may be transferred between the Messa...

Page 1059: ...ster Sets 1 and 2 The Command Register addresses the desired message object in the Message RAM and specifies whether a complete message object or only parts should be transferred The data transfer is...

Page 1060: ...IF3 Update Enable 5 0x16C IF3 Update Enable 8 IF3 Update Enable 7 The automatic update functionality can be programmed for each message object see IF3 Update Enable Register Section 23 17 29 All valid...

Page 1061: ...Frames Setting TxRqst for a Receive Object will cause the transmission of a Remote Frame with the same identifier as the Data Frame for which this receive Object is configured 23 7 3 Configuration of...

Page 1062: ...Data Length Code The data bytes of the message object will remain unchanged If the RxIE bit is set the IntPnd bit will be set when a received Remote Frame is accepted and stored in the message object...

Page 1063: ...ed by IF1 IF2 registers when priority is same or higher as message the object found by last scanning Handling of TxRqst flags Handling of interrupt flags The Message Handler registers contains status...

Page 1064: ...of a Data Frame if in the matching Transmit Object the RmtEn bit is set 23 8 4 Updating a Transmit Object The CPU may update the data bytes of a Transmit Object any time via the IF1 IF2 Interface Reg...

Page 1065: ...s already set MsgLst is set to indicate that the previous data supposedly not seen by the CPU is lost If the RxIE bit is set the IntPnd bit is set causing the Interrupt Register to point to this messa...

Page 1066: ...matching to a FIFO Buffer are stored into a message object of this FIFO Buffer starting with the message object with the lowest message number When a message is stored into a message object of a FIFO...

Page 1067: ...ntPnd Read IF1 IF2 message control NewDat 1 Read data from IF1 IF2 Data A B EoB 1 Next Message Number in this FIFO Buffer Yes No Yes No Message interrupt Interrupt Handling Message Number interrupt id...

Page 1068: ...PU may read or write each message at any time via the Interface Registers as the Message Handler guarantees data consistency in case of concurrent accesses for reconfiguration see Section 23 7 6 If a...

Page 1069: ...Int1ID in the Interrupt Register see Section 23 17 5 When no interrupt is pending the register will hold the value zero Each interrupt line remains active until the dedicated field in the Interrupt R...

Page 1070: ...each CAN frame independent of bus errors or valid CAN communication and also independent of the Message RAM configuration Status Change interrupts can only be routed to interrupt line DCAN0INT that ha...

Page 1071: ...waits until a bus idle state is recognized Then it will automatically set the Init bit to indicate that the global power down mode has been entered 23 11 2 Wakeup From Global Power Down Mode When the...

Page 1072: ...it while PDR is set If there are any messages in the Message RAM configured as to be transmitted and the application resets the init bit these messages may be sent 23 12 2 Wakeup From Local Power Down...

Page 1073: ...work DCAN Module 23 13 GIO Support The CAN_RX and CAN_TX pins of each DCAN module can be used as general purpose IO pins if CAN functionality is not needed This function is controlled by the CAN TX IO...

Page 1074: ...re that all message transfers are finished before setting the Init bit to 1 23 14 1 Silent Mode The Silent Mode may be used to analyze the traffic on the CAN bus without affecting it by sending domina...

Page 1075: ...put pin is disregarded by the CAN Core Transmitted messages still can be monitored at the CAN_TX pin In order to be independent from external stimulation the CAN Core ignores acknowledge errors recess...

Page 1076: ...Tx pin itself and the signal path from Tx pin back to CAN Core When External Loop Back Mode is selected the input of the CAN core is connected to the input buffer of the Tx pin With this configuration...

Page 1077: ...combination of Loop Back Mode with Silent Mode Figure 23 18 CAN Core in Loop Back Combined with Silent Mode 23 14 5 Software Control of CAN_TX Pin Four output functions are available for the CAN trans...

Page 1078: ...the modulo 2 sum of the data bits is 1 This definition is equivalent to The parity bit will be set if the number of 1 bits in the data is odd NOTE Parity scheme can be changed via the System module D...

Page 1079: ...reset the registers of the DCAN hold the values shown in the register descriptions The base address for the control registers is FFF7 DC00h for DCAN1 FFF7 DE00h for DCAN2 and FFF7 E000h for DCAN3 Add...

Page 1080: ...ommand Register Section 23 17 19 104h DCAN IF1MSK IF1 Mask Register Section 23 17 20 108h DCAN IF1ARB IF1 Arbitration Register Section 23 17 21 10Ch DCAN IF1MCTL IF1 Message Control Register Section 2...

Page 1081: ...ssage which Initiates the bus activity cannot be received This means that the first message received in power down and automatic wake up mode will be lost 24 PDR Request for local low power down mode...

Page 1082: ...rted transmission or reception to be completed before entering Debug Suspend mode 1 When Debug Suspend mode is requested DCAN will interrupt any transmission or reception and enter Debug Suspend mode...

Page 1083: ...nd PER R 0 R 0 R C 0 R C 0 7 6 5 4 3 2 0 BOff EWarn EPass RxOK TxOK LEC R 0 R 0 R 0 R C 0 R C 0 R S 7h LEGEND R Read only C Clear S Set n value after reset Table 23 8 Error and Status Register Field D...

Page 1084: ...wed 2h Form Error A fixed format part of a received frame has the wrong format 3h Ack Error The message this CAN Core transmitted was not acknowledged by another node 4h Bit1 Error During the transmis...

Page 1085: ...ter reset Table 23 9 Error Counter Register Field Descriptions Bit Field Value Description 31 16 Reserved 0 These bits are always read as 0 Writes have no effect 15 RP Receive Error Passive 0 The Rece...

Page 1086: ...actual TSeg2 value that is interpreted for the Bit Timing will be the programmed TSeg2 value 1 11 8 TSeg1 1h Fh Time segment before the sample point Valid programmed values are 1 to 15 The actual TSe...

Page 1087: ...ighest priority The DCAN1INT interrupt line remains active until Int1ID reaches value 0 the cause of the interrupt is reset or until IE1 is cleared A message interrupt is cleared by clearing the messa...

Page 1088: ...ceive Pin Monitors the actual value of the CAN_RX pin 0 The CAN bus is dominant 1 The CAN bus is recessive 6 5 Tx Control of CAN_TX pin 0 Normal operation CAN_TX is controlled by the CAN Core 1h Sampl...

Page 1089: ...by reading the Error and Status Register In addition to the PER flag the Parity Error Code Register will indicate the memory area where the parity error has been detected message number and word numbe...

Page 1090: ...access to the CAN Control register while Auto Bus On timer is running the Auto Bus On procedure will be aborted During Debug Suspend mode running Auto Bus On timer will be paused 23 17 10 Transmissio...

Page 1091: ...ssful transmission Figure 23 29 Transmission Request 12 Register offset 88h 31 0 TxRqst 32 1 R 0 LEGEND R Read only n value after reset Figure 23 30 Transmission Request 34 Register offset 8Ch 31 0 Tx...

Page 1092: ...If at least on of the NewDat bits of these message objects are set the corresponding bit in the New Data X Register will be set Figure 23 33 New Data X Register DCAN NWDAT X offset 98h 31 16 Reserved...

Page 1093: ...New Data 12 Register offset 9Ch 31 0 NewDat 32 1 R 0 LEGEND R Read only n value after reset Figure 23 35 New Data 34 Register offset A0h 31 0 NewDat 64 33 R 0 LEGEND R Read only n value after reset F...

Page 1094: ...If at least one of the IntPnd bits of these message objects are set the corresponding bit in the Interrupt Pending X Register will be set Figure 23 38 Interrupt Pending X Register DCAN INTPND X offse...

Page 1095: ...eption or a successful transmission Figure 23 39 Interrupt Pending 12 Register offset B0h 31 0 IntPnd 32 1 R 0 LEGEND R Read only n value after reset Figure 23 40 Interrupt Pending 34 Register offset...

Page 1096: ...ects If at least one of the MsgVal bits of these message objects are set the corresponding bit in the Message Valid X Register will be set Figure 23 43 Message Valid X Register DCAN MSGVAL X offset C0...

Page 1097: ...successful transmission Figure 23 44 Message Valid 12 Register offset C4h 31 0 MsgVal 32 1 R 0 LEGEND R Read only n value after reset Figure 23 45 Message Valid 34 Register offset C8h 31 0 MsgVal 64 3...

Page 1098: ...the Interrupt Register Figure 23 48 Interrupt Multiplexer 12 Register offset D8h 31 0 IntMux 32 1 R W 0 LEGEND R W Read Write n value after reset Figure 23 49 Interrupt Multiplexer 34 Register offset...

Page 1099: ...d transfer will start after the first one has been completed NOTE While the Busy bit is 1 IF1 IF2 Register sets are write protected For debug support the auto clear functionality of the IF1 IF2 Comman...

Page 1100: ...to the corresponding IF1 IF2 Register set Direction Write The Message Control bits will be transferred from the IF1 IF2 Register set to the message object addressed by Message Number Bits 7 0 If the T...

Page 1101: ...ts 7 0 IF1 IF2 Register set will be write protected The bit is cleared after read write action has finished 14 DMA Active Activation of DMA feature for subsequent internal IF1 IF2 update 0 DMA request...

Page 1102: ...0 Msk 15 0 R WP FFFFh LEGEND R W Read Write R Read only WP Protected Write protected by Busy bit n value after reset Table 23 22 IF1 IF2 Mask Register Field Descriptions Bit Field Value Description 31...

Page 1103: ...Field Descriptions Bit Field Value Description 31 MsgVal Message Valid 0 The message object is ignored by the Message Handler 1 The message object is used by the Message Handler Note The CPU should r...

Page 1104: ...gisters DCAN IF1MCTL DCAN IF2MCTL The bits of the IF1 IF2 Message Control Registers mirror the message control bits of a message object The function of the relevant message objects bits is described i...

Page 1105: ...ammed during initialization of the message object before MsgVal is set to 1 11 TxIE Transmit Interrupt Enable 0 IntPnd will not be triggered after the successful transmission of a frame 1 IntPnd will...

Page 1106: ...ta 2 R WP 0 R WP 0 15 8 7 0 Data 1 Data 0 R WP 0 R WP 0 LEGEND R W Read Write WP Protected Write protected by Busy bit n value after reset Figure 23 61 IF1 Data B Register DCAN IF1DATB offset 114h 31...

Page 1107: ...status of the current read cycle can be observed via status flags Bits 12 8 An interrupt request may be generated by the IF3Upd flag if the DE3 bit of DCAN CTL register is set See the device data shee...

Page 1108: ...ection still has data to read 7 5 Reserved 0 These bits are always read as 0 Writes have no effect 4 DataB Data B read observation 0 Data B section does not need to be read 1 Data B section has to be...

Page 1109: ...ng 1 The extended identifier bit IDE is used for acceptance filtering Note When 11 bit standard identifiers are used for a message object the identifiers of received Data Frames are written into bits...

Page 1110: ...ets bit Init in the CAN Control Register MsgVal must also be reset if the messages object is no longer used in operation For reconfiguration of message objects during normal operation see Section 23 7...

Page 1111: ...tored a new message into this object when NewDat was still set so the previous message has been overwritten 13 IntPnd Interrupt Pending 0 This message object is not the source of an interrupt 1 This m...

Page 1112: ...8h Data Frame has 0 8 data bytes 9h Fh Data Frame has 8 data bytes Note The Data Length Code of a message object must be defined the same as in all the corresponding objects with the same identifier a...

Page 1113: ...cts Figure 23 70 IF3 Update Enable 12 Register offset 160h 31 0 IF3UpdEn 32 1 R W 0 LEGEND R W Read Write n value after reset Figure 23 71 IF3 Update Enable 34 Register offset 164h 31 0 IF3UpdEn 64 33...

Page 1114: ...PD 0 1 CAN_TX Pullup is selected when pull logic is active PD 0 17 PD CAN_TX pull disable This bit is only active when CAN_TX is configured to be an input 0 CAN_TX pull is active 1 CAN_TX pull is dis...

Page 1115: ...15 4 3 2 1 0 Reserved Func Dir Out In R 0 R WP 0 R WP 0 R WP 0 R U LEGEND R W Read Write R Read only WP Protected Write protected by Init bit D Device dependent n value after reset U Undefined Table...

Page 1116: ...output Forced to 0 if Init bit of CAN control register is reset 1 Out CAN_RX data out write This bit is only active when CAN_RX pin is configured to be in GIO mode RIOC Func 0 and configured to be an...

Page 1117: ...or other microcontrollers Throughout this chapter all references to SPI also apply to MibSPI MibSPIP unless otherwise noted NOTE This chapter describes a superset implementation of the MibSPI SPI modu...

Page 1118: ...mat SPI pins can be used as functional or digital Input Output pins GIOs NOTE SIMO Slave In Master Out Pin SOMI Slave Out Master In Pin SPICS SPI Chip Select Pin SPIENA SPI Enable Pin 24 1 1 Word Form...

Page 1119: ...bSPI It is only accessible in compatibility mode 24 1 3 Transmission Lock Multi Buffer Mode Master Only Some slave devices require transmission of a command followed by data In this case the SPI trans...

Page 1120: ...the TX shift register and TXBUF are empty then the data is directly copied to the TX shift register For devices with DMA if DMA is enabled a transmit DMA request TX_DMA_REQ is generated to cause the...

Page 1121: ...ead TXFULL RXOVRN INT0 RXOVR INT 16 16 16 RXEMPTY RX INT ENA Clock polarity Clock phase Prescale Charlen SPISIMO SPISOMI Peripheral clock SPI clock generation logic SPIDAT0 SPIDAT1 TX INT ENA Kernel F...

Page 1122: ...ected number of bits have been transmitted the received data in the shift register is transferred to the SPIBUF register for the CPU to read Data is stored right justified in SPIBUF See Section 24 2 2...

Page 1123: ...setting one of the SPICS pins as a chip select It is disabled by setting all SPICS pins as GIOs in SPIPC0 24 2 3 1 Multiple Chip Selects The SPICS pins that are used must be configured as functional p...

Page 1124: ...NA pin is in high impedance mode ENABLE_HIGHZ 1 the slave will put SPIENA into the high impedance once it completes receiving a new character If the SPIENA pin is in push pull mode ENABLE_HIGHZ 0 the...

Page 1125: ...ow when new data is written to the slave shift register and the slave has been selected by the master SPICS is low If the SPIENA pin is in push pull mode ENABLE_HIGHZ 0 the slave SPI drives this pin h...

Page 1126: ...r each data format If a received parity bit does not match with the locally calculated parity bit the parity error flag PARITYERR is set and an interrupt is asserted if enabled Since the master mode S...

Page 1127: ...delay and the polarity rising edge falling edge of the clock The data input and output edges depend on the values of both POLARITY and PHASE as shown in Table 24 2 Table 24 2 Clocking Modes POLARITY...

Page 1128: ...ling edge of SPICLK Input data is latched on the rising edge of SPICLK Write SPIDAT SPISIMO SPISOMI receive sample MSB D6 D5 D4 D3 D2 D1 D0 LSB D6 D5 D4 D3 D2 D1 D7 1 2 3 4 5 6 7 8 SPICLK Operating Mo...

Page 1129: ...Clock polarity 0 Clock phase 0 Clock phase 1 www ti com Operating Modes 1129 SPNU503C March 2018 Submit Documentation Feedback Copyright 2018 Texas Instruments Incorporated Multi Buffered Serial Perip...

Page 1130: ...red Both delay counters are clocked with the peripheral clock VCLK If a particular data format specifically does not require these additional set up or hold times for the chip select pins then they ca...

Page 1131: ...ss all the buffers then the slave in multi buffer mode requires its SPICS pins to be deasserted between any two buffer transfers otherwise the Slave SPI will be unable to respond to the next data tran...

Page 1132: ...ecting any mismatch in length of received or transmitted data and the programmed character length under certain conditions Data Length Error in Master Mode During a data transfer if the SPI detects a...

Page 1133: ...ting Modes 1133 SPNU503C March 2018 Submit Documentation Feedback Copyright 2018 Texas Instruments Incorporated Multi Buffered Serial Peripheral Interface Module MibSPI with Parallel Pin Option MibSPI...

Page 1134: ...SIMO pin mapping when the SPI is used in parallel mode 1 2 4 8 pin mode MSB first NOTE MSB first or LSB first can be configured using the SHIFTDIRx bit of the SPIFMTx registers Table 24 3 Pin Mapping...

Page 1135: ...B First Table 24 5 and Table 24 6 describe the SIMO and SOMI pin mapping when SPI is used in parallel mode 1 2 4 8 pin mode LSB first Table 24 5 Pin Mapping for SIMO Pin with LSB First Parallel Mode S...

Page 1136: ...MI 0 or vice versa in slave mode After writing to the SPIDAT0 SPIDAT1 register the bits 15 and 7 will be output on SIMO 1 and SIMO 0 on the rising edge if SPICLK With the falling clock edge of the SPI...

Page 1137: ...e versa in slave mode After writing to SPIDAT1 SPIDAT0 the bits 15 11 7 and 3 will be output on SIMO 3 SIMO 2 SIMO 1 and SIMO 0 on the rising edge of SPICLK With the falling clock edge of the SPICLK t...

Page 1138: ...4 SIMO 3 SIMO 2 SIMO 1 and SIMO 0 on the rising edge of SPICLK On the falling clock edge of the SPICLK the received data on SOMI 8 SOMI 7 SOMI 6 SOMI 5 SOMI 4 SOMI 3 SOMI 2 SOMI 1 and SOMI 0 will be l...

Page 1139: ...I 3 SOMI 2 SOMI 1 SOMI 0 www ti com Operating Modes 1139 SPNU503C March 2018 Submit Documentation Feedback Copyright 2018 Texas Instruments Incorporated Multi Buffered Serial Peripheral Interface Modu...

Page 1140: ...work like an RX pin while the HDUPLEX_ENAx bit in SPIFMTx register is set to 1 In Half Duplex Master mode the SIMO pin acts as an RX pin Switching between Full Duplex and Half Duplex can be achieved u...

Page 1141: ...ck available The IOLPBKTSTCR register defines all of the available control fields In loopback mode it is also possible to induce various error conditions See Section 24 9 43 for details of the registe...

Page 1142: ...bled 24 4 General Purpose I O All of the SPI pins may be programmed via the SPIPCx control registers to be either functional or general purpose I O pins If the SPI function is to be used application s...

Page 1143: ...r full and transmit buffer empty By programming one to Level 0 and the other to Level 1 it is possible to avoid a check on whether an interrupt occurred for transmit or for receive A programmer can al...

Page 1144: ...as RXOVRNINTFLG and the corresponding vector number is updated in TGINTVECT0 TGINTVECT1 register If an overrun interrupt is enabled then an interrupt will be generated indicating an overrun condition...

Page 1145: ...lowing is true DMAREQEN SPIINT0 16 is set to 1 while SPIEN SPIGCR1 24 is already 1 SPIEN SPIGCR1 24 is set to 1 while DMAREQEN SPIINT0 16 is already 1 The SPI generates a request on the RX_DMA_REQ lin...

Page 1146: ...SPIENA pins for SPI functionality by setting the corresponding bit in SPIPC0 register Configure the module to function as Master or Slave using CLKMOD and MASTER bits Configure the required SPI data...

Page 1147: ...using SPIDELAY register Check for BUFINITACTIVE bit to be active before configuring MIBSPI RAM From Device Power On it take Number of Buffers Peripheral clock period to initialize complete RAM Enable...

Page 1148: ...Section 24 9 8 20h SPIPC3 SPI Pin Control Register 3 Section 24 9 9 24h SPIPC4 SPI Pin Control Register 4 Section 24 9 10 28h SPIPC5 SPI Pin Control Register 5 Section 24 9 11 2Ch SPIPC6 SPI Pin Cont...

Page 1149: ...r Section 24 9 42 134h IOLPBKTSTCR I O Loopback Test Control Register Section 24 9 43 138h EXTENDED_PRESCALE1 SPI Extended Prescale Register 1 Section 24 9 44 13Ch EXTENDED_PRESCALE2 SPI Extended Pres...

Page 1150: ...Reserved 0 Reads return 0 Writes have no effect 16 LOOPBACK Internal loop back test mode The internal self test option can be enabled by setting this bit If the SPISIMO and SPISOMI pins are configured...

Page 1151: ...4 3 2 1 0 Reserved RXOVRNINT ENA Reserved BITERR ENA DESYNC ENA PARERR ENA TIMEOUT ENA DLENERR ENA R 0 R W 0 R 0 R W 0 R W 0 R W 0 R W 0 R W 0 LEGEND R W Read Write R Read only n value after reset Ta...

Page 1152: ...7 Reserved 0 Reads return 0 Writes have no effect 6 RXOVRNINTENA Overrun interrupt enable 0 Overrun interrupt will not be generated 1 Overrun interrupt will be generated 5 Reserved 0 Reads return 0 Wr...

Page 1153: ...ved 0 Reads return 0 Writes have no effect 6 RXOVRNINTLVL Receive overrun interrupt level 0 Receive overrun interrupt is mapped to interrupt line INT0 1 Receive overrun interrupt is mapped to interrup...

Page 1154: ...isters or buffer handling Note If the SPIFLG register is read while the multi buffer RAM is being initialized the BUFINITACTIVE bit will be read as 1 If SPIFLG is read after the internal automatic buf...

Page 1155: ...NTVECT1 register when there is a receive buffer overrun interrupt Writing a 1 to RXOVRNINTFLG in the SPI Flag Register SPIFLG itself Writing a 0 to SPIEN Reading the data field of the SPIBUF register...

Page 1156: ...is set This flag can be cleared by one of the following methods Write a 1 to this bit Clear the SPIEN bit to 0 0 No parity error is detected 1 A parity error occurred 1 TIMEOUTFLG Time out caused by...

Page 1157: ...ill control the SPISOMI 0 pin The read value of bit 24 always reflects the value of bit 11 0 The SPISOMI x pin is a GIO pin 1 The SPISOMI x pin is a SPI functional pin 23 16 SIMOFUN Slave in master ou...

Page 1158: ...gister 1 SPIPC1 NOTE Register bits vary by device Register bits 31 24 and 23 16 of this register reflect the number of SIMO SOMI data lines per device On devices with 8 data line support all of bits 3...

Page 1159: ...functional pin the I O direction is determined by the MASTER bit in the SPIGCR1 register 0 The SPISOMI 0 pin is an input 1 The SPISOMI 0 pin is an output 10 SIMODIR0 SPISIMO 0 direction This bit cont...

Page 1160: ...ite R Read only U Undefined n value after reset Table 24 15 SPI Pin Control Register 2 SPIPC2 Field Descriptions Bit Field Value Description 31 24 SOMIDIN SPISOMI x data in The value of each SPISOMI x...

Page 1161: ...11 will have priority over bit 24 0 Current value on SPISOMI x pin is logic 0 1 Current value on SPISOMI x pin is logic 1 23 16 SIMODOUT SPISIMO x data out write This bit is only active when the SPISI...

Page 1162: ...a subset of these bits are available Unimplemented bits return 0 upon read and are not writable Figure 24 35 SPI Pin Control Register 4 SPIPC4 offset 24h 31 24 23 16 SOMISET SIMOSET R W U R W U 15 12...

Page 1163: ...it has no effect 1 Read SPISIMO 0 is logic 1 Write Logic 1 is placed on SPISIMO 0 pin if it is in general purpose output mode 9 CLKSET SPICLK data out set This bit is only active when the SPICLK pin i...

Page 1164: ...it 24 0 Read The current value on SPISOMI x is 0 Write Writing a 0 to this bit has no effect 1 Read The current value on SPISOMI x is 1 Write Logic 0 is placed on SPISOMI x pin if it is in general pur...

Page 1165: ...s bit has no effect 1 Read The current value on SPIENA is 1 Write Logic 0 is placed on SPIENA pin if it is in general purpose output mode 7 0 SCSCLR SPICS data out clear This bit is only active when t...

Page 1166: ...0 open drain enable This bit enables open drain capability for the SPISOMI 0 pin if the following conditions are met SPISOMI 0 pin is configured in GIO mode as output pin Output value on SPISOMI 0 pin...

Page 1167: ...x pull control disable This bit disables pull control capability for each SPISOMI x pin if it is in input mode regardless of whether it is in functional or GIO mode Note Bit 11 or bit 24 can be used t...

Page 1168: ...n is disabled 24 9 14 SPI Pin Control Register 8 SPIPC8 NOTE Register bits vary by device Register bits 31 24 and 23 16 of this register reflect the number of SIMO SOMI data lines per device On device...

Page 1169: ...is bit selects the type of pull logic at the SPISOMI 0 pin 0 Pull down on the SPISOMI 0 pin 1 Pull up on the SPISOMI 0 pin 10 SIMOPSEL0 SPISIMO 0 pull select This bit selects the type of pull logic at...

Page 1170: ...empty TXBUF holds the written data SPIEN SPICGR1 24 must be set to 1 before this register can be written to Writing a 0 to the SPIEN register forces the lower 16 bits of the SPIDAT0 to 0x00 Note When...

Page 1171: ...the end of a transfer until a control field with new data and control information is loaded into SPIDAT1 If the new chip select number equals the previous one the active chip select signal is extended...

Page 1172: ...t is empty If the shift register is not empty then they are held in TXBUF SPIEN must be set to 1 before this register can be written to Writing a 0 to SPIEN forces the lower 16 bits of SPIDAT1 to 0x00...

Page 1173: ...CS 0 0h No chip select pin is active 20h x 1h x 21h x x 2h x 22h x x 3h x x 23h x x x 4h x 24h x x 5h x x 25h x x x 6h x x 26h x x x 7h x x x 27h x x x x 8h x 28h x x 9h x x 29h x x x Ah x x 2Ah x x...

Page 1174: ...s set Overruns always occur to RXBUF not to SPIBUF the contents of SPIBUF are overwritten only after it is read by the Peripheral VBUSP master CPU DMA or other host processor If enabled the RXOVRN int...

Page 1175: ...the desync flag is always assured to be for the current buffer Note This flag is cleared to 0 when the RXDATA field of the SPIBUF register is read 0 No slave desynchronization is detected 1 A slave d...

Page 1176: ...Delay Register SPIDELAY Figure 24 44 SPI Delay Register SPIDELAY offset 48h 31 24 23 16 C2TDELAY T2CDELAY R W 0 R W 0 15 8 7 0 T2EDELAY C2EDELAY R W 0 R W 0 LEGEND R W Read Write n value after reset T...

Page 1177: ...g one or more clock edges it becomes de synchronized In this case although the master has finished the data transfer the slave is still waiting for the missed clock pulses and the ENA signal is not di...

Page 1178: ...C March 2018 Submit Documentation Feedback Copyright 2018 Texas Instruments Incorporated Multi Buffered Serial Peripheral Interface Module MibSPI with Parallel Pin Option MibSPIP Figure 24 45 Example...

Page 1179: ...ed CSDEF R 0 R W FFh LEGEND R W Read Write R Read only n value after reset Table 24 28 SPI Default Chip Select Register SPIDEF Field Descriptions Bit Field Value Description 31 8 Reserved 0 Reads retu...

Page 1180: ...each transmitted word At the end of a transfer the parity generator compares the received parity bit with the locally calculated parity flag If the parity bits do not match the RXERR flag is set in th...

Page 1181: ...ould be reset and reconfigured if clock phase polarity needs to be switched In summary SPI format switching is not fully supported in slave mode Even while using chip select pins the polarity of SPICL...

Page 1182: ...of interrupt suspend or finished 11h Error Interrupt pending The lower half of SPIFLG contains more details about the type of error 13h The pending interrupt is a Receive Buffer Overrun interrupt 12h...

Page 1183: ...1 INTVECT1 Bit Field Value Description 31 6 Reserved 0 Reads return 0 Writes have no effect 5 1 INTVECT1 INTVECT1 Interrupt vector for interrupt line INT1 Returns the vector of the pending interrupt a...

Page 1184: ...highest priority transfer group A read from INTVECT1 automatically causes the next highest priority transfer group s interrupt status to get loaded into INTVECT1 and its corresponding SUSPEND flag to...

Page 1185: ...te control is used for this pin 23 17 Reserved 0 Reads return the value that was last written Writes have no effect 16 SIMOSRS0 SPI2 SIMO 0 slew control This bit controls between the fast or slow slew...

Page 1186: ...Reserved MODCLKPOL3 MMODE3 PMODE3 R 0 R WP 0 R WP 0 R WP 0 23 22 21 20 18 17 16 Reserved MODCLKPOL2 MMODE2 PMODE2 R 0 R WP 0 R WP 0 R WP 0 15 14 13 12 10 9 8 Reserved MODCLKPOL1 MMODE1 PMODE1 R 0 R WP...

Page 1187: ...mine whether the SPI MibSPI operates with 1 2 4 or 8 data lines 0 Normal operation 1 data line MMODE2 should be set to 000 1h 2 data line mode MMODE2 should be set to 000 2h 4 data line mode MMODE2 sh...

Page 1188: ...o option is supported by the module 0 1 data line mode default PMODE0 should be set to 00 1h 2 data line mode PMODE0 should be set to 00 2h 3 data line mode PMODE0 should be set to 00 3h 4 data line m...

Page 1189: ...ting of receive RAM direct read write access is enabled by setting this bit 0 The RX portion of multi buffer RAM is not writable by the CPU 1 The whole of multi buffer RAM is fully accessible for read...

Page 1190: ...t Table 24 35 TG Interrupt Enable Set Register TGITENST Field Descriptions Bit Field Value Description 31 16 SETINTENRDY n TG interrupt set enable when transfer finished Bit 16 corresponds to TG0 bit...

Page 1191: ...ield Descriptions Bit Field Value Description 31 16 CLRINTENRDY n TG interrupt clear disabled when transfer finished Bit 16 corresponds to TG0 bit 17 corresponds to TG1 and so on 0 Read The TGx comple...

Page 1192: ...offset 7Ch 31 16 SETINTLVLRDY 15 0 R W 0 15 0 SETINTLVLSUS 15 0 R W 0 LEGEND R W Read Write n value after reset Table 24 37 Transfer Group Interrupt Level Set Register TGITLVST Field Descriptions Bit...

Page 1193: ...ffset 80h 31 16 CLRINTLVLRDY 15 0 R W 0 15 0 CLRINTLVLSUS 15 0 R W 0 LEGEND R W Read Write n value after reset Table 24 38 Transfer Group Interrupt Level Clear Register TGITLVCR Field Descriptions Bit...

Page 1194: ...tically clears the interrupt flag bit INTFLGRDYx referenced by the vector number given by INTVECT0 INTVECT1 bits if the SUSPEND 0 1 bit in the vector registers is 0 0 Read No transfer completed interr...

Page 1195: ...able 0 The internal tick counter is disabled The counter value remains unchanged Note When the tick counter is disabled the trigger signal is forced low 1 The internal tick counter is enabled and is c...

Page 1196: ...1h TG0 is being serviced by the sequencer 10h TG15 is being serviced by the sequencer Note The number of transfer groups varies by device 11h 1Fh Invalid values 23 15 Reserved 0 Reads return 0 Writes...

Page 1197: ...ransfer can be triggered before the host enables the TG again This one shot mode ensures that after one group transfer the host has enough time to read the received data and to provide new transmit da...

Page 1198: ...buffer transfer the sequencer continues with the same TG until it is completed 0 never Never trigger TGx This is the default value after reset 1h rising edge A rising edge 0 to 1 at the selected trigg...

Page 1199: ...e HET I O channel event pin Ch EXT11 External trigger source 11 The actual source varies per device for example HET I O channel event pin Dh EXT12 External trigger source 12 The actual source varies p...

Page 1200: ...e DMA requests are generated In conjunction with NOBRKx a burst transfer can be initiated without any other transfer through another buffer 30 24 BUFIDx 0 7Fh Buffer utilized for DMA transfer BUFIDx d...

Page 1201: ...rmed from the buffer referenced by BUFIDx without a data transfer from any other buffer The sequencer remains at the DMA buffer until ICOUNTx 1 transfers have been processed For example this can be us...

Page 1202: ...sponding DMA channel If NOBRKx is set ICOUNTx defines the number of DMA transfers that are performed in one sequence without a transfer from any other buffer 15 0 COUNTx 0 FFFFh Actual number of remai...

Page 1203: ...n to in the DMAxCOUNT register before the RXDMAENA or TXDMAENA bits are set in the DMAxCTRL register The DMAxCOUNT register should be used for reading COUNT or ICOUNT 24 9 38 Multi buffer RAM Uncorrec...

Page 1204: ...TAT Field Descriptions Bit Field Value Description 31 2 Reserved 0 Reads return 0 Writes have no effect 1 EDFLG1 Uncorrectable parity error detection flag This flag indicates if a parity error occurre...

Page 1205: ...ister holds the address where a parity error is generated while reading RXRAM Only the CPU or DMA can read from RXRAM locations The address captured is byte aligned This error address is frozen from b...

Page 1206: ...ss where a parity error is generated while reading from TXRAM The TXRAM can be read either by CPU or by the MibSPI sequencer logic for transmission The address captured is byte aligned This error addr...

Page 1207: ...urred This address value will show only the offset address of the RAM location in the multi buffer RAM address space Refer to the device specific data sheet for the actual absolute address of RXRAM Th...

Page 1208: ...during analog loopback 0 Read No miscompares occurred on any of the eight chip select pins vs the internal chip select number CSNR during transfers Write Writing a 0 to this bit has no effect 1 Read A...

Page 1209: ...have no effect 5 3 ERR SCS PIN Inject error on chip select pin number x The value in this field is decoded as the number of the chip select pin on which to inject an error During analog loopback if C...

Page 1210: ...ded Prescale value for SPIFMT1 EPRESCALE_FMT1 determines the bit transfer rate of data format 1 if the SPI MibSPI is the network master EPRESCALE_FMT1 is use to derive SPICLK from VCLK If the SPI is c...

Page 1211: ...mplemented register The clock rate for data format 0 can be calculated as BRFormat0 VCLK EPRESCALE_FMT0 1 Write This register field should be written if a SPICLK prescaler of more VCLK 256 is required...

Page 1212: ...ded Prescale value for SPIFMT3 EPRESCALE_FMT3 determines the bit transfer rate of data format 3 if the SPI MibSPI is the network master EPRESCALE_FMT3 is use to derive SPICLK from VCLK If the SPI is c...

Page 1213: ...mplemented register The clock rate for data format 0 can be calculated as BRFormat2 VCLK EPRESCALE_FMT2 1 Write This register field should be written if a SPICLK prescaler of more VCLK 256 is required...

Page 1214: ...tioned into multiple TGs each containing a programmable number of buffers Each of the buffers can be subdivided into 16 bit transmit field 16 bit receive field 16 bit control field and 16 bit status f...

Page 1215: ...set to reflect that the initialization is ongoing 3 When the memory initialization is completed the corresponding status bit in the MINISTAT register will be set Also the BUFINITACTIVE bit will get cl...

Page 1216: ...ip this buffer until the corresponding RXEMPTY flag is set new receive data can be stored in RXDATA without data loss 3h skip single transfer overwrite protect mode Skip this buffer until both of the...

Page 1217: ...e delay counter No transaction will be performed until the WDELAY counter overflows The SPICS pins will be de activated for at least WDELAY 2 VCLK_Period duration 25 24 DFSEL Data word format select 0...

Page 1218: ...CS 0 0h No chip select pin is active 20h x 1h x 21h x x 2h x 22h x x 3h x x 23h x x x 4h x 24h x x 5h x x 25h x x x 6h x x 26h x x x 7h x x x 27h x x x x 8h x 28h x x 9h x x 29h x x x Ah x x 2Ah x x x...

Page 1219: ...eceived data is copied into RXBUF while it is already full RXOVR is set Overruns always occur to RXBUF not to RXRAM the contents of RXRAM are overwritten only after it is read by the Peripheral VBUSP...

Page 1220: ...ode the desync flag is always guaranteed to be for the current buffer Note This flag is cleared to 0 when the RXDATA field of the RXRAM register is read 0 No slave desynchronization is detected 1 A sl...

Page 1221: ...or testing the parity portion of the multi buffer RAM which is a 4 bit field per word address 1 bit per byte a separate parity memory test mode is available Parity memory test mode can be enabled and...

Page 1222: ...XBUF127 Parity0 Parity1 0 31 0 3 Parity127 Parity126 Parity locations are not accessible by CPU TX Parity0 TX Parity1 0 Shaded areas indicate they are physically not present Memory Map During Normal O...

Page 1223: ...A001_AA55 If the polarity of the parity is set to odd the corresponding parity location parity5 will get updated with equivalent parity of 1011 in its field During parity memory test mode these bits...

Page 1224: ...operation In each mode different configurations like Phase and Polarity affect the pin timings The pin directions are based on the mode of operation Master mode SPI SPICLK SPI Clock Output SPISIMO SP...

Page 1225: ...K SPIENA VCLK Dotted vertical lines indicate the receive edges Write to SPIDAT www ti com MibSPI Pin Timing Parameters 1225 SPNU503C March 2018 Submit Documentation Feedback Copyright 2018 Texas Instr...

Page 1226: ...ster Write to SPIDAT SPICLK VCLK SPICLK SPISOMI SPISIMO Dotted vertical lines indicate the receive edges Write to SPIDAT MibSPI Pin Timing Parameters www ti com 1226 SPNU503C March 2018 Submit Documen...

Page 1227: ...ster will wait for an active low from the Slave on the input pin to start the SPICLK 24 12 4 Slave Mode Timing Parameter Details In case of Slave mode the module will drive only the SPISOMI and SPIENA...

Page 1228: ...mode NOTE This chapter describes a superset implementation of the LIN SCI module that includes features and functionality that require DMA Since not all devices have DMA capability consult your device...

Page 1229: ...of the SCI module Standard universal asynchronous receiver transmitter UART communication Supports full or half duplex operation Standard nonreturn to zero NRZ format Double buffered receive and trans...

Page 1230: ...Slave automatic synchronization Synchronization break detection Optional baud rate update Synchronization validation 231 programmable transmission rates with 7 fractional bits Wakeup on LINRX dominan...

Page 1231: ...receiver shift register SCIRXSHF shifts data in from the LINRX pin one bit at a time and transfers completed data into the receive data buffer The receiver data buffer register SCIRD contains receive...

Page 1232: ...26 SCIGCR1 25 TXENA SCIFLR 10 BRKDT INT ENA WAKEUP INT ENA PE OE FE RECEIVER TRANSMITTER CLOCK Baud clock SCIBAUD generator Baud rate registers LINTX RXENA SCISETINT 9 SCISETINT 0 SCISETINT 1 SCIGCR1...

Page 1233: ...n and Features 1233 SPNU503C March 2018 Submit Documentation Feedback Copyright 2018 Texas Instruments Incorporated Serial Communication Interface SCI Local Interconnect Network LIN Module Figure 25 2...

Page 1234: ...Both receive and transmit data is in nonreturn to zero NRZ format which means that the transmit and receive lines are at logic high when idle Each frame transmission begins with a start bit in which...

Page 1235: ...contiguous SCI baud clock periods to detect a valid start bit The bus is considered idle if this condition is not met When a valid start bit is detected the SCI determines the value of each bit by sam...

Page 1236: ...onal VCLK period added to their Tbit If the character length is more than 10 then the modulation table will be a rolled over version of the original table Table 25 1 as shown in Table 25 2 The baud ra...

Page 1237: ...y Bit Stop Bit 0 Stop Bit 1 Table 25 2 Superfractional Bit Modulation for SCI Mode Maximum Configuration 1 BRS 30 28 Start Bit D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 Addr Parity Stop0 Stop1 0h 0 0 0 0 0 0 0...

Page 1238: ...n 10 idle bits is a data frame Figure 25 6 illustrates the format of several blocks and frames with idle line mode There are two ways to transmit an address frame using idle line mode Method 1 In soft...

Page 1239: ...ltiprocessor Communication Format 25 2 4 2 Address Bit Multiprocessor Mode In the address bit protocol each frame has an extra bit immediately following the data field called an address bit A frame wi...

Page 1240: ...ta bytes transferred from the SCIRXSHF register to the RDy receive buffers and TDy transmit buffers register to SCITXSHF register The 3 bit compare register contains the number of data bytes expected...

Page 1241: ...X DMA Request CHECKSUM CALCULATOR TX MBUF MODE TX Ready Flag Not MBUF MODE www ti com SCI Communication Formats 1241 SPNU503C March 2018 Submit Documentation Feedback Copyright 2018 Texas Instruments...

Page 1242: ...gisters SCIINTVECT0 and SCIINTVECT1 determine which flag triggered the interrupt according to the respective priority encoders Each interrupt condition has a bit to enable disable the interrupt in the...

Page 1243: ...r can write data to SCITD in the transmit Interrupt service routine Writing data to the SCITD register clears the TXRDY bit When this data has been moved to the SCITXSHF register the TXRDY bit is set...

Page 1244: ...til the end of the frame Each of these flags is located in the receiver status SCIFLR register There are 16 interrupt sources in the SCI LIN module In SCI mode 8 interrupts are supported as seen in Ta...

Page 1245: ...eived and copied to the corresponding RDy buffer successfully If the multi buffer option is disabled then DMA requests will be generated on a byte per byte basis In multiprocessor mode the SCI can gen...

Page 1246: ...ation breakpoint until its current reception or transmission is complete this bit is used only in an emulation environment Set the LOOP BACK bit in SCIGCR1 to 1 to connect the transmitter to the recei...

Page 1247: ...Single Buffer Mode Single buffer mode is selected when the MBUF MODE bit in SCIGCR1 is cleared to 0 In this mode SCI waits for data to be written to SCITD transfers it to SCITXSHF and transmits the da...

Page 1248: ...or Multiprocessor Communication When the SCI receives data and transfers that data from SCIRXSHF to SCIRD the RXRDY bit is set and if RX INT ENA is set the SCI also generates an interrupt The interrup...

Page 1249: ...mode can help free some CPU resources Except for the RXRDY flag the SCI continues to update the receiver status flags see Table 25 12 while sleep mode is active In this way if an error occurs on the...

Page 1250: ...byte spaces In frame response and inter byte spaces may be 0 There is no arbitration in the definition of the LIN protocol therefore multiple slave nodes responding to a header might be detected as an...

Page 1251: ...er all data bytes in the data fields of the response Figure 25 14 Response Format of LIN Message Frame The format of the response is a stream of N data fields and one checksum field Typically N is fro...

Page 1252: ...ing this defines the bit time Tbit The bit time is derived from the fields P and M in the baud rate selection register BRS There is an additional 3 bit fractional divider value field U in the BRS regi...

Page 1253: ...r Tbit 1 1 In LIN master mode bit modulation applies to synch field identifier field response field 2 In LIN slave mode bit modulation applies to identifier field response field Table 25 7 Superfracti...

Page 1254: ...dominant bits The synch break length may be extended from the minimum with the 3 bit SBREAK value in the LINCOMP register The synchronization break delimiter SDEL consists of a minimum of 1 recessive...

Page 1255: ...ent triggered frame header the master node will set the NRE flag and a NRE interrupt will occur if enabled If a collision occurs a frame error and checksum error may arise before the NRE error Those e...

Page 1256: ...bit is used as required by the LIN protocol For detection of the dominant data stream of the synch break the synchronizer counter is started on a falling edge and stopped on a rising edge of the LINRX...

Page 1257: ...ling edge On LINRX o Reset counter 2 3 1 4 Save counter BAUD_count Verify valid Synch Field If ADAPT 1 compare baud rate and Baud Update flag is set if baudrates differ www ti com LIN Communication Fo...

Page 1258: ...ed The length for this identifier will be set at network configuration time to be shared with the LIN bus nodes Extended frame communication is triggered on reception of a header with identifier 0x3E...

Page 1259: ...ssage frame is not fully completed within the maximum length allowed TFRAME_MAX After this time a no response error NRE is flagged in the NRE bit of the SCIFLR register An interrupt is triggered if en...

Page 1260: ...sleep mode by writing the POWERDOWN bit NOTE After the timeout was flagged a software RESET should be asserted before entering Low Power Mode This is required to reset the receiver in case that an inc...

Page 1261: ...ing back on the LINRX pin as shown in Figure 25 21 NOTE If BE Occurs due to New Header reception during a Slave Response NRE TIMEOUT flag will not be set for the new Frame Figure 25 21 TXRX Error Dete...

Page 1262: ...ulo 256 sum is calculated over each byte by adding with carry where the carry bit of each addition is added to the LSB of its resulting sum For the transmitting node the checksum byte sent at the end...

Page 1263: ...ts of the received identifier and thus there will be an ID match regardless of the content of the ID SlaveTask BYTE field in the LINID register NOTE When the HGEN CTRL bit 0 the LIN nodes compare the...

Page 1264: ...g Parity Enable ID Parity Error No ID Parity Error HGEN CTRL ID INT 0 1 0 1 From AND AND RX No ID Parity Error RXENA RX Match TX Match ID RX Flag ID TX Fla g No ID Parity Error HGEN CTRL LIN Communic...

Page 1265: ...does not convey message length see Note Optional Control Length Bits in Section 25 7 5 the LENGTH value indicates the expected length and is used to load the 3 bit compare register Whether the length...

Page 1266: ...s not used to convey message length see Note Optional Control Length Bits in Section 25 7 5 the LENGTH value indicates the expected length and is used instead to load the 3 bit compare register Whethe...

Page 1267: ...N DMA Interface LIN DMA Interface uses the SCI DMA interface logic DMA requests for receive RXDMA request and transmit TXDMA request are available for the SCI LIN module There are two modes for DMA tr...

Page 1268: ...ID MASK fields in the LINMASK register Set the SWnRST bit to 1 after LIN is configured Perform receiving or transmitting data see Section 25 10 1 or Section 25 10 2 25 10 1 Receiving Data The LIN rec...

Page 1269: ...active independently of the receiver The ID TX flag is set after a valid LIN ID is received with TX Match An ID interrupt is generated if enabled 25 10 2 1 Transmitting Data in Single Buffer Mode Sing...

Page 1270: ...leared The BLIN module may enter low power mode either when there was no activity on the LINRX pin for more than 4s this can be either a constant recessive or dominant level or when a Sleep Command fr...

Page 1271: ...bits Figure 25 26 Wakeup Signal Generation 47 Assuming a perfect bus with no noise or loading effects a write of 0xF0 to TD0 will load the transmitter to meet the wakeup signal timing requirement for...

Page 1272: ...nditions the MBRS register must be set to assure that the LIN 2 0 real time based timings meet the LIN 1 3 bit time base A node triggering the wakeup should set the MBRS register accordingly to meet t...

Page 1273: ...CIFLR SCI Flags Register Section 25 13 8 20h SCIINTVECT0 SCI Interrupt Vector Offset 0 Section 25 13 9 24h SCIINTVECT1 SCI Interrupt Vector Offset 1 Section 25 13 10 28h SCIFORMAT SCI Format Control R...

Page 1274: ...gister Figure 25 27 SCI Global Control Register 0 SCIGCR0 offset 00 31 16 Reserved R 0 15 1 0 Reserved RESET R 0 R WP 0 LEGEND R W Read Write R Read only R WP Read Write in privileged mode only n valu...

Page 1275: ...are disabled 1 Transfers from SCITD or TDy to SCITXSHF are enabled Note Data written to SCITD or the transmit multi buffer before TXENA is set is not transmitted If TXENA is cleared while transmission...

Page 1276: ...ped this bit is cleared automatically 0 This bit has no effect 1 Extended frame communication will be stopped when current frame transmission reception is completed 12 HGEN CTRL HGEN control This bit...

Page 1277: ...be done After this bit is set to 1 the configuration of the module should not change Note The SCI LIN should only be configured while SWnRST 0 6 LIN MODE LIN mode This bit is effective in LIN and SCI...

Page 1278: ...ects the SCI timing mode 0 Synchronous timing is used 1 Asynchronous timing is used 0 COMM MODE SCI LIN communication mode bit In compatibility mode it selects the SCI communication mode In LIN mode i...

Page 1279: ...it will be auto cleared after the checkbyte has been received and compared Checksum reception is not guaranteed if CC bit is write cleared by software during the checksum reception See Section 25 7 6...

Page 1280: ...LIN or SCI mode When this bit is set the SCI LIN module attempts to enter local low power mode If the POWERDOWN bit is set while the receiver is actively receiving data and the wakeup interrupt is di...

Page 1281: ...y Setting this bit enables the SCI LIN module to generate an interrupt when there is a bit error 0 Read The interrupt is disabled Write Writing a 0 to this bit has no effect 1 Read or write The interr...

Page 1282: ...requests are generated for both address and data frames 0 Read The DMA request is disabled for address frames the receive interrupt request is enabled for address frames Write Writing a 0 to this bit...

Page 1283: ...urs after one wakeup signal has been sent 0 Read The interrupt is disabled Write Writing a 0 to this bit has no effect 1 Read or write The interrupt is enabled 5 Reserved 0 Reads return 0 Writes have...

Page 1284: ...le mode only n value after reset Table 25 16 SCI Clear Interrupt Register SCICLEARINT Field Descriptions Bit Field Value Description 31 CLR BE INT Clear bit error interrupt This bit is effective in LI...

Page 1285: ...This bit disables the parity error interrupt when set 0 Read The interrupt is disabled Write Writing a 0 to this bit has no effect 1 Read The interrupt is enabled Write The interrupt is disabled 23 19...

Page 1286: ...led Write The interrupt is disabled 7 CLR TOA3WUS INT Clear timeout after three wakeup signals interrupt This bit is effective in LIN mode only This bit disables the timeout after three wakeup signals...

Page 1287: ...odule Table 25 16 SCI Clear Interrupt Register SCICLEARINT Field Descriptions continued Bit Field Value Description 0 CLR BRKDT INT Clear break detect interrupt This bit is effective in SCI compatible...

Page 1288: ...The interrupt level is mapped to the INT0 line Write Writing a 0 to this bit has no effect 1 Read or write The interrupt level is mapped to the INT1 line 30 SET PBE INT LVL Set physical bus error inte...

Page 1289: ...eserved 0 Reads return 0 Writes have no effect 9 SET RX INT LVL Set receiver interrupt level This bit is effective in LIN or SCI compatible mode 0 Read The interrupt level is mapped to the INT0 line W...

Page 1290: ...work LIN Module Table 25 17 SCI Set Interrupt Level Register SCISETINTLVL Field Descriptions continued Bit Field Value Description 0 SET BRKDT INT LVL Set break detect interrupt level This bit is effe...

Page 1291: ...fective in LIN mode only 0 Read The interrupt level is mapped to the INT0 line Write Writing a 0 to this bit has no effect 1 Read The interrupt level is mapped to the INT1 line Write The interrupt lev...

Page 1292: ...0 Read The receive interrupt request for address frames is mapped to the INT0 line Write Writing a 0 to this bit has no effect 1 Read The receive interrupt request for address frames is mapped to the...

Page 1293: ...imeout interrupt This bit is effective in LIN mode only 0 Read The interrupt level is mapped to the INT0 line Write Writing a 0 to this bit has no effect 1 Read The interrupt level is mapped to the IN...

Page 1294: ...information The bit error flag is cleared by any of the following Setting of the SWnRST bit Setting of the RESET bit A system reset Writing a 1 to this bit On reception of a new synch break Reading th...

Page 1295: ...hen an inconsistent synch field error has been detected by the synchronizer during header reception See Section 25 7 5 2 for more information The inconsistent synch field error flag is cleared by the...

Page 1296: ...rites unread data already in SCIRD or the RDy buffers in LINRD0 and LINRD1 Detection of an overrun error causes the LIN to generate an error interrupt if the SET OE INT bit 1 The OE flag is reset by t...

Page 1297: ...he following Setting the SWnRST bit Setting of the RESET bit A system reset Writing a 1 to this bit Reading the LINID register Receiving a new synch break Reading the corresponding interrupt offset in...

Page 1298: ...bit is set SCISETINT 9 RXRDY is cleared by the following Setting of the SWnRST bit Setting of the RESET bit A system reset Writing a 1 to this bit Reading the SCIRD register in compatibility mode Rea...

Page 1299: ...3 for more information 0 Read No timeout occurred after one wakeup signal 150 ms Write Writing a 0 to this bit has no effect 1 Read Timeout occurred after one wakeup signal Write The bit is cleared t...

Page 1300: ...n interrupt is generated if the SET WAKEUP INT bit SCISETINT 2 is set It is cleared by the following Setting of the SWnRST bit Setting of the RESET bit A system reset Writing a 1 to this bit Reading t...

Page 1301: ...nterrupts Note The flags for the receive SCIFLR 9 and the transmit SCIFLR 8 interrupt cannot be cleared by reading the corresponding offset vector in this register see detailed description in SCIFLR r...

Page 1302: ...ode these bits indicate the transmitter receiver format for the number of characters 1 to 8 There can be up to eight characters with eight bits each 0 The response field has 1 byte character 1h The re...

Page 1303: ...ne tuning of the fractional baud rate with seven more intermediate values for each of the M fractional divider values See Section 25 7 4 1 for more details 27 24 M 0 3h SCI LIN 4 bit fractional divide...

Page 1304: ...D SCIRD SCITD The SCI has three addressable registers in which transmit and receive data is stored These three registers are available in SCI mode only 25 13 13 1 Receiver Emulation Data Buffer SCIED...

Page 1305: ...ld Value Description 31 8 Reserved 0 Reads return 0 Writes have no effect 7 0 RD 0 FFh Receiver data This bit is effective in SCI compatible mode only When a frame has been completely received the dat...

Page 1306: ...to be loaded with another byte of data Note If SET TX INT is set this data transfer also causes an interrupt NOTE Data written to the SCITD register that is fewer than eight bits long must be right j...

Page 1307: ...Table 25 30 for the LINTX pin control with this bit and others 0 LINTX is a general purpose input pin 1 LINTX is a general purpose output pin 1 RX DIR Receive pin direction This bit is effective in LI...

Page 1308: ...0 R x R x R x LEGEND R Read only n value after reset x value is indeterminate Table 25 32 SCI Pin I O Control Register 2 SCIPIO2 Field Descriptions Bit Field Value Description 31 3 Reserved 0 Reads r...

Page 1309: ...X if the following conditions are met TX FUNC 0 LINTX pin is a general purpose I O TX DIR 1 LINTX pin is a general purpose output See Table 25 30 for an explanation of this bit s effect in combination...

Page 1310: ...it sets the logic to be output on pin LINTX if the following conditions are met TX FUNC 0 LINTX pin is a general purpose I O TX DIR 1 LINTX pin is a general purpose output See Table 25 30 for an expla...

Page 1311: ...clear This bit is effective in LIN or SCI mode This bit clears the logic to be output on pin LINTX if the following conditions are met TX FUNC 0 LINTX pin is a general purpose I O TX DIR 1 LINTX pin i...

Page 1312: ...n drain capability in the output pin LINTX if the following conditions are met TX FUNC 0 LINTX pin is a general purpose I O TX DIR 1 LINTX pin is a general purpose output 0 Open drain functionality is...

Page 1313: ...Receive pin pull control disable This bit is effective in LIN or SCI mode This bit disables pull control capability on the input pin LINRX 0 Pull control on the LINRX pin is enabled 1 Pull control on...

Page 1314: ...the synch field The default value is 0 The formula to program the value in Tbits for the synchronization delimiter is TSDEL SDEL 1 Tbit 0 The synch delimiter has 1 Tbit 1h The synch delimiter has 2 T...

Page 1315: ...bytes received 7 0 RD3 0 FFh Receive buffer 3 Byte 3 of the response data byte Each response data byte that is received in the SCIRXSHFT register is transferred to the corresponding RDy register acco...

Page 1316: ...e only This 8 bit mask is used for filtering an incoming ID message and comparing it to the ID byte A compare match of the received ID with the RX ID MASK will set the ID RX flag and trigger an ID int...

Page 1317: ...e contains the current message identifier During header reception the received ID is copied from the SCIRXSHF register to this byte if there is no ID parity error and there has been an RX TX match 15...

Page 1318: ...2 Byte 2 to be transmitted is written into this register and then copied to SCITXSHF for transmission 7 0 TD3 0 FFh 8 Bit transmit buffer 3 Byte 3 to be transmitted is written into this register and t...

Page 1319: ...scriptions Bit Field Value Description 31 13 Reserved 0 Reads return 0 Writes have no effect 12 0 MBR 0 1FFFh Maximum baud rate prescaler This bit is effective in LIN mode only This 13 bit prescaler i...

Page 1320: ...privilege mode only n value after reset Table 25 47 Input Output Error Enable Register IODFTCTRL Field Descriptions Bit Field Value Description 31 BEN Bit error enable This bit is effective in LIN mo...

Page 1321: ...CENTER 2h Invert the TX Pin value at TBIT_CENTER SCLK 3h Invert the TX Pin value at TBIT_CENTER 2 SCLK 18 16 TX SHIFT Transmit shift These bits define the amount by which the value on TX pin is delaye...

Page 1322: ...d Serial Communication Interface SCI Local Interconnect Network LIN Module 25 14 GPIO Functionality The following sections apply to all device pins that can be configured as functional or general purp...

Page 1323: ...ction control register SCIPIO1 Section 25 13 15 AND the open drain feature is not enabled in the SCIPIO6 register Section 25 13 20 25 14 4 Open Drain Feature Enabled on a Pin The following apply if th...

Page 1324: ...8 Serial Communication Interface SCI Module This chapter contains the description of the serial communication interface SCI module Topic Page 26 1 Introduction 1325 26 2 SCI Communication Formats 1327...

Page 1325: ...urces during multiprocessor communication and then wake up to receive an incoming message The 24 bit programmable baud rate supports 224 different baud rates provide high accuracy baud rate selection...

Page 1326: ...CI VCLK Peripheral Introduction www ti com 1326 SPNU503C March 2018 Submit Documentation Feedback Copyright 2018 Texas Instruments Incorporated Serial Communication Interface SCI Module The SCI receiv...

Page 1327: ...he transmit and receive lines are at logic high when idle Each frame transmission begins with a start bit in which the transmitter pulls the SCI line low logic low Following the start bit the frame da...

Page 1328: ...rpreting noise as Start bit SCI expects SCIRX line to be low for at least four contiguous SCI baud clock periods to detect a valid start bit The bus is considered idle if this condition is not met Whe...

Page 1329: ...ase of data sent to an individual device the receiving devices must determine when they are being addressed When a message is not intended for them the devices can ignore the following data When only...

Page 1330: ...a delay loop in software Method 2 can be implemented by using the transmit buffer and the TXWAKE bit in the following manner Step 1 Write a 1 to the TXWAKE bit Step 2 Write a dummy data value to the S...

Page 1331: ...ss bit A frame with the address bit set to 1 is an address frame a frame with the address bit set to 0 is a data frame The idle period timing is irrelevant in this mode Figure 26 5 illustrates the for...

Page 1332: ...and SCIINTVECT1 determine which flag triggered the interrupt according to the respective priority encoders Each interrupt condition has a bit to enable and disable the interrupt in the SCISETINT and S...

Page 1333: ...to SCITD in the transmit Interrupt service routine Writing data to the SCITD register clears the TXRDY bit When this data has been moved to the SCITXSHF register the TXRDY bit is set again The interr...

Page 1334: ...nerated if enabled A message is valid for both the transmitter and the receiver if there is no error detected until the end of the frame Each of these flags is located in the receiver status SCIFLR re...

Page 1335: ...and data frames If the SET RX DMA ALL bit is cleared and the SET RX DMA bit is set when the SCI sets the RXRDY flag upon receipt of a data frame then a receive DMA request is generated Receive interru...

Page 1336: ...ion environment Set LOOP BACK bit in SCIGCR1 to 1 to connect the transmitter to the receiver internally this feature is used to perform a self test Set the RXENA bit in SCIGCR1 to 1 if data is to be r...

Page 1337: ...interrupt DMA request should be halted This can either be done by disabling the transmit interrupt CLR TX INT DMA request CLR TX DMA bit or by disabling the transmitter clear TXENA bit NOTE The TXRDY...

Page 1338: ...k the address in SCIRD against its own address If it is still being addressed then sleep mode should remain disabled Otherwise the SLEEP bit should be set again Following is a sequence of events typic...

Page 1339: ...ster Section 26 7 5 18h SCICLEARINTLVL SCI Clear Interrupt Level Register Section 26 7 6 1Ch SCIFLR SCI Flags Register Section 26 7 7 20h SCIINTVECT0 SCI Interrupt Vector Offset 0 Section 26 7 8 24h S...

Page 1340: ...llustrate this register Figure 26 8 SCI Global Control Register 0 SCIGCR0 offset 00 31 16 Reserved R 0 15 1 0 Reserved RESET R 0 R WP 0 LEGEND R Read only R WP Read Write in privileged mode only n val...

Page 1341: ...ng the data previously written to SCITD is sent 24 RXENA Receive enable RXENA allows or prevents the transfer of data from SCIRXSHF to SCIRD 0 The receiver will not transfer data from the shift buffer...

Page 1342: ...n an address frame is detected The remaining receiver status flags see Table 26 11 are updated and an error interrupt is requested if the corresponding interrupt enable bit is set regardless of the va...

Page 1343: ...the parity calculation For odd parity the SCI transmits and expects to receive a value in the parity bit that makes odd the total number of bits in the frame with the value of 1 For even parity the S...

Page 1344: ...upt Setting this bit enables the SCI module to generate an interrupt when an overrun error occurs 0 Read The interrupt is disabled Write Writing a 0 to this bit has no effect 1 Read or write The inter...

Page 1345: ...it has no effect 1 Read or write The interrupt is enabled 8 SET TX INT Set transmitter interrupt Setting this bit enables the SCI to generate a transmit interrupt as data is being transferred from SCI...

Page 1346: ...disables the framing error interrupt when set 0 Read The interrupt is disabled Write Writing a 0 to this bit has no effect 1 Read The interrupt is enabled Write The interrupt is disabled 25 CLR CE INT...

Page 1347: ...0 Reads return 0 Writes have no effect 9 CLR RX INT Clear receiver interrupt This bit disables the receiver interrupt when set 0 Read The interrupt is disabled Write Writing a 0 to this bit has no ef...

Page 1348: ...ng error interrupt level 0 Read The interrupt level is mapped to the INT0 line Write Writing a 0 to this bit has no effect 1 Read or write The interrupt level is mapped to the INT1 line 25 SET CE INT...

Page 1349: ...a 0 to this bit has no effect 1 Read or write The interrupt level is mapped to the INT1 line 26 7 6 SCI Clear Interrupt Level Register SCICLEARINTLVL Figure 26 13 and Table 26 9 illustrate this regis...

Page 1350: ...nterrupt request for address frames is mapped to the INT1 line Write The receive interrupt request for address frames is mapped to the INT0 line 17 10 Reserved 0 Reads return 0 Writes have no effect 9...

Page 1351: ...amed Detection of a framing error causes the SCI to generate an error interrupt if the SET FE INT bit SCISETINT 26 is set The framing error flag is cleared by the following Setting of the SW nRST bit...

Page 1352: ...ect 12 RXWAKE Receiver wakeup detect flag The SCI sets this bit to indicate that the data currently in SCIRD is an address RXWAKE is cleared by the following Setting of the SW nRST bit Setting of the...

Page 1353: ...e TXRDY flag cannot be cleared by reading the corresponding interrupt offset in the SCIINTVECT0 1 register 3 The transmit interrupt request can be eliminated until the next series of data written into...

Page 1354: ...is set when the SCI detects a break condition on the SCIRX pin A break condition occurs when the SCIRX pin remains continuously low for at least 10 bits after a missing first stop bit that is after a...

Page 1355: ...e flags for the receive SCIFLR 9 and the transmit SCIFLR 8 interrupt cannot be cleared by reading the corresponding offset vector in this register see detailed description in SCIFLR register 26 7 9 SC...

Page 1356: ...s Bit Field Value Description 31 3 Reserved 0 Reads return 0 Writes have no effect 2 0 CHAR Character length control bits These bits set the SCI character length from 1 to 8 bits When data of fewer th...

Page 1357: ...24 Reserved 0 Reads return 0 Writes have no effect 23 0 BAUD 0 FF FFFFh SCI 24 bit baud selection The SCI has an internally generated serial clock determined by the VCLK and the prescalers BAUD in th...

Page 1358: ...tor that must continually read the data buffer without affecting the RXRDY flag 26 7 12 2 Receiver Data Buffer SCIRD This register provides a location for the receiver data Figure 26 20 and Table 26 1...

Page 1359: ...the SCITD register The transfer of data from this register to the transmit shift register SCITXSHF sets the TXRDY flag which indicates that SCITD is ready to be loaded with another byte of data Note I...

Page 1360: ...he SCITX pin control with this bit and others 0 SCITX is a general purpose input pin 1 SCITX is a general purpose output pin 1 RX DIR Receive pin direction This bit determines the data direction on th...

Page 1361: ...ved TX IN RX IN Reserved R 0 R x R x R x LEGEND R Read only n value after reset x Indeterminate Table 26 25 SCI Pin I O Control Register 2 SCIPIO2 Field Descriptions Bit Field Value Description 31 3 R...

Page 1362: ...g conditions are met TX FUNC 0 SCITX pin is a general purpose I O TX DIR 1 SCITX pin is a general purpose output See Table 26 23 for an explanation of this bit s effect in combination with other bits...

Page 1363: ...c to be output on pin SCITX if the following conditions are met TX FUNC 0 SCITX pin is a general purpose I O TX DIR 1 SCITX pin is a general purpose output See Table 26 23 for an explanation of this b...

Page 1364: ...t 2 TX CLR Transmit pin clear This bit clears the logic to be output on pin SCITX if the following conditions are met TX FUNC 0 SCITX pin is a general purpose I O TX DIR 1 SCITX pin is a general purpo...

Page 1365: ...pability in the output pin SCITX if the following conditions are met TX FUNC 0 SCITX pin is a general purpose I O TX DIR 1 SCITX pin is a general purpose output 0 Open drain functionality is disabled...

Page 1366: ...TX pin is disabled 1 RX PD Receive pin pull control disable This bit disables pull control capability on the input pin SCIRX 0 Pull control on the SCIRX pin is enabled 1 Pull control on the SCIRX pin...

Page 1367: ...Output Error Enable Register IODFTCTRL Field Descriptions Bit Field Value Description 31 27 Reserved 0 Reads return 0 Writes have no effect 26 FEN Frame error enable This bit is used to create a fram...

Page 1368: ...12 Reserved 0 Reads return 0 Writes have no effect 11 8 IODFTENA IODFT enable key Write access permitted in Privilege mode only Ah IODFT is enabled All Others IODFT is disabled 7 2 Reserved 0 Reads re...

Page 1369: ...ments Incorporated Serial Communication Interface SCI Module 26 8 GPIO Functionality The following sections apply to all device pins that can be configured as functional or general purpose I O pins 26...

Page 1370: ...n as an output pin if the TX DIR bit is set in the pin direction control register SCIPIO1 Section 26 7 14 AND the open drain feature is not enabled in the SCIPIO6 register Section 26 7 19 26 8 4 Open...

Page 1371: ...master communication module providing an interface between the Texas Instruments TI microcontroller and devices compliant with Philips Semiconductor I2 C bus specification version 2 1 and connected by...

Page 1372: ...nable disable capability Seven interrupts that can be used by the CPU Operates with VBUS frequency from 6 7 MHz up Operates with module frequency between 6 7 MHz to 13 3 MHz Module enable disable capa...

Page 1373: ...compliant I2C devices that are incapable of generating an ACK The I2C module consists of the following primary blocks A serial Interface one data pin SDA and one clock pin SCL The device register inte...

Page 1374: ...C I2CDSET I2CDCLR I2CPDR I2CPDIS I2CSRS SDA I2CEMDR Filter Noise Filter Clock synchronizer I2CPDIR I2CPDR I2CPDIS I2CSRS I2CPFNC I2CDOUT I2CDSET I2CDCLR TX DMA REQ I2CDMACR RX DMA REQ I2CSTR I2CPSEL I...

Page 1375: ...frequency at which the I2C module operates A programmable prescaler in the I2C module divides down the input clock to produce the module clock To specify the divide down value initialize the I2CPSC f...

Page 1376: ...is generated by the master device for each data bit transferred Because of a variety of different technology devices that can be connected to the I2C bus the levels of logic 0 low and logic 1 high ar...

Page 1377: ...I2CMDR must both be set to 1 For the I2C module to end a data transfer with a STOP condition the STOP condition bit STP must be set to 1 When the BB bit is set to 1 and the STT bit is set to 1 a repe...

Page 1378: ...anded address enable XA bit of I2CMDR and make sure the free data format mode is off FDF 0 in I2CMDR Figure 27 7 I2C Module 7 Bit Addressing Format 27 2 5 2 10 Bit Addressing Format The 10 bit address...

Page 1379: ...nore any new bits the I2C module must send a no acknowledge NACK bit during the acknowledge cycle on the bus Table 27 1 summarizes the various ways a NACK can be generated Table 27 1 Ways to Generate...

Page 1380: ...k pulses are inhibited and the SCL is held low when the intervention of the device is required RSFULL 1 after a byte has been received At the end of the transfer the master receiver signals the end of...

Page 1381: ...free run mode when the FREE bit I2CMDR 14 is set to 1 This bit is primarily used on an emulator when encountering a breakpoint while debugging software When the FREE bit is set to 0 the I2C responds d...

Page 1382: ...rocedure gives priority to the device that transmits the serial data stream with the lowest binary value The master transmitter that loses the arbitration switches to the slave receiver mode sets the...

Page 1383: ...ines the length of the low period and the fastest device determines the length of the high period If a device pulls down the clock line for a longer time the result is that all clock generators must e...

Page 1384: ...2C registers are ready to be accessed RXRDY Receive data ready interrupt Generated when the received data in the receive shift register I2CSR has been copied into the data receive register I2CDRR The...

Page 1385: ...nt occurs soon after the start condition but before the first bit of the address is transmitted In this event no DMA activity should be initiated without the slave ACK being received 27 5 3 I2C Enable...

Page 1386: ...ctive pull down function by writing to the corresponding bit in I2CPSEL register The pull up pull down function is active on the pin only when the pull enabled is programmed in the I2CPDIS register Th...

Page 1387: ...7 1Ch I2CSAR I2C Slave Address Register Section 27 6 8 20h I2CDXR I2C Data Transmit Register Section 27 6 9 24h I2CMDR I2C Mode Register Section 27 6 10 28h I2CIVR I2C Interrupt Vector Register Secti...

Page 1388: ...er I2COAR Field Descriptions Bit Field Value Description 15 10 Reserved 0 Reads return 0 Writes have no effect 9 0 OA 0 3FFh Own address These bits reflect the bus address of the I2C module When the e...

Page 1389: ...ons Bit Field Value Description 15 7 Reserved 0 Reads return 0 Writes have no effect 6 AASEN Address As Slave Interrupt Enable 0 The AASEN interrupt is disabled 1 The AASEN interrupt is enabled 5 SCDE...

Page 1390: ...ge sent This bit is set to 1 to indicate that a no acknowledgement NACK has been sent because the NACKMOD bit was set to 1 Writing a 1 to this bit will clear it 0 A NACK has not been sent 1 A NACK was...

Page 1391: ...general call was detected 1 An address of all zeros general call was detected 7 6 Reserved 0 Reads return 0 Writes have no effect 5 SCD Stop condition detect interrupt flag This bit is set to 1 when...

Page 1392: ...ers are not ready to be accessed 1 Nonrepeat mode RM 0 ICCNT passes 0 if STP bit has not been set Repeat mode RM 1 The end of each byte was transmitted from I2CDXR 1 NACK No acknowledgement interrupt...

Page 1393: ...te the low time portion of the master clock signal that will appear on the SCL pin 62 where d is the value that depends on the I2CPSC see Section 27 1 3 This register must be configured while the I2C...

Page 1394: ...iptions Bit Field Value Description 15 0 CNT 0 FFFFh Data counter This down counter is used to generate a stop condition if a stop condition is specified STP 1 Note ICCNT is a don t care when RM is se...

Page 1395: ...ect 9 0 SA 7 or 10 bit programmable slave address In either mode all 10 bits are readable and writable Bits 7 8 and 9 should only be used in 10 bit address mode Table 27 13 lists the correct mode for...

Page 1396: ...CL becomes low and then stops If the I2C is a slave it will stop when the transmission reception completes 1 The I2C runs free 13 STT Start condition The start condition bit works with the STP bit mas...

Page 1397: ...ter transmitter mode 0 Digital loop back mode is disabled 1 Digital loop back mode is enabled In digital loop back mode data transmitted out of the I2CDXR will be received in the I2CDRR The address of...

Page 1398: ...Activities 1 Mode 0 0 0 Idle None N A 0 0 1 Stop P N A 0 1 0 Repeat Start S A D n D Repeat n 0 1 1 Repeat Start Stop S A D n D P Repeat n 1 0 0 Idle none N A 1 0 1 Stop P N A 1 1 0 Repeat Start S A D...

Page 1399: ...If there is more than one interrupt pending reading I2CIVR provides the vector for the highest priority interrupt that is pending Reading the I2CIVR will clear the corresponding flags in I2CSTR for AL...

Page 1400: ...t and the I2C needs more data to transmit This behavior causes an extra TXRDY interrupt to be generated because the I2C recognizes the end of transfer after generating an interrupt for the next byte o...

Page 1401: ...iptions Bit Field Value Description 15 8 CLASS 0 FFh Peripheral class These bits identify the class of peripheral 7 0 REVISION 0 FFh Revision level of the I2C These bits identify the revision level of...

Page 1402: ...smit event is disabled Writing a 1 to this bit will send a TXDMA request to the DMA module if PINFUNC is also set to 0 0 The transmit DMA is disabled 1 The transmit DMA is enabled 0 RXDMAEN Receive DM...

Page 1403: ...ve no effect 1 SDADIR SDA direction This bit controls the direction of the I2C SDA pin when configured as a GPIO 0 SDA pin functions as an input 1 SDA pin functions as an output 0 SCLDIR SCL direction...

Page 1404: ...function is only active if the SCL pin is configured as an I O pin with PINFUNC 1 This bit contains the value sent to the SCL pin 0 SCL pin is driven low 1 SCL pin is driven high 27 6 21 I2C Data Set...

Page 1405: ...clear the SCL GPIO pin 0 Read Reads return value of SCLOUT Write Writing a 0 to this bit has no effect 1 Read Reads return value of SCLOUT Write SCLOUT is cleared to logic low 0 27 6 23 I2C Pin Open D...

Page 1406: ...APDIS SDA pull disable 0 The pull function is enabled 1 The pull function is disabled 0 SCLPDIS SCL pull disable 0 The pull function is enabled 1 The pull function is disabled 27 6 25 I2C Pull Select...

Page 1407: ...X Enabled Disabled Enabled No 0 0 0 Pull down Disabled Enabled No 0 0 1 Pull up Disabled Enabled No 0 1 0 Disabled Disabled Enabled No 0 1 1 Disabled Disabled Enabled No 1 X X Disabled Enabled Enable...

Page 1408: ...2018 Texas Instruments Incorporated Inter Integrated Circuit I2C Module 27 7 Sample Waveforms Figure 27 40 provides waveforms to illustrate the difference between normal operation and backward compati...

Page 1409: ...SPNU503C March 2018 EMAC MDIO Module This chapter describes the Ethernet Media Access Controller EMAC and physical layer PHY device Management Data Input Output MDIO module Topic Page 28 1 Introducti...

Page 1410: ...col 28 1 2 Features The EMAC MDIO has the following features Synchronous 10 100 Mbps operation Standard Media Independent Interface MII and or Reduced Media Independent Interface RMII to physical laye...

Page 1411: ...nfigure required parameters in the EMAC module for correct operation The module is designed to allow almost transparent operation of the MDIO interface with very little maintenance from the core proce...

Page 1412: ...ication software or driver must control the divide down value The transmit and receive clock sources are provided by the external PHY to the MII_TXCLK and MII_RXCLK pins or to the RMII reference clock...

Page 1413: ...this bit Please refer to the I O Multiplexing and Control Module IOMM chapter for more details on the procedure to configure the PINMMR registers Each of the EMAC and MDIO signals for the MII and RMII...

Page 1414: ...rk is not idle in either transmit or receive The pin is deasserted when both transmit and receive are idle This signal is not necessarily synchronous to MII_TXCLK nor MII_RXCLK In full duplex operatio...

Page 1415: ...ynchronous to RMII_MHZ_50_CLK RMII_MHZ_50_CLK I RMII reference clock RMII_MHZ_50_CLK The reference clock is used to synchronize all RMII signals RMII_MHZ_50_CLK must be continuous and fixed at 50 MHz...

Page 1416: ...MDIO Signal MDIO_CLK PINMMR7 15 8 0b00000100 MDIO_D PINMMR8 15 8 0b00000100 Table 28 4 MII RMII Multiplexing Control MII RMII Signal Name Control for Selecting MII Signal Control for Selecting RMII Si...

Page 1417: ...he Ethernet MAC address of the EMAC port for which the frame is intended It may be an individual or multicast including broadcast address When the destination EMAC port receives an Ethernet frame with...

Page 1418: ...sence of signal energy coming from other ports If the port transmits the entire frame without detecting signal energy from other Ethernet devices the port is done with the frame 4 If the port detects...

Page 1419: ...inter The buffer pointer refers to the actual memory buffer that contains packet data during transmit operations or is an empty buffer ready to receive packet data during receive operations 2 Buffer O...

Page 1420: ...EMAC descriptor queue for the first time the software application simply writes the pointer to the descriptor or first descriptor of a list to the corresponding HDP register Note that the last descri...

Page 1421: ...ET YES SET SOFTWARE TX QUEUE ACTIVE TX PACKET S ADDED WRITE TX QUEUE HEAD DESCRIPTOR POINTER NO NO www ti com Architecture 1421 SPNU503C March 2018 Submit Documentation Feedback Copyright 2018 Texas I...

Page 1422: ...OWNERSHIP BIT CLEAR CURRENT BD EOQ BIT GET NEW NOW CURRENT BD ADDRESS CLEAR CURRENT BD EOP BIT YES ZERO CURRENT BD NEXT DESC POINTER TX PACKET COMPLETE WRITE CURRENT BD NEXT DESC POINTER SET CURRENT...

Page 1423: ...TX QUEUE ACTIVE WRITE NEXT DESC POINTER VALUE TO QUEUE HEAD DESC POINTER MISQUEUED PACKET NO PROCESS MORE PACKET S RECLAIM BUFFER DESCRIPTOR BD NO YES NO RECLAIM BUFFER DESCRIPTOR BD www ti com Archit...

Page 1424: ...nterrupts are enabled by setting the mask registers RXINTMASKSET and TXINTMASKSET 2 Global interrupts are set in the EMAC control module C0RXEN and C0TXEN 3 The VIM is configured to accept C0_RX_PULSE...

Page 1425: ...smit Buffer Descriptor in C Structure Format EMAC Descriptor The following is the format of a single buffer descriptor on the EMAC typedef struct _EMAC_Desc struct _EMAC_Desc pNext Pointer to next des...

Page 1426: ...indicates that the first 15 bytes of the buffer are to be ignored by the EMAC and that valid buffer data starts on byte 16 of the buffer The software application must set this value prior to adding th...

Page 1427: ...to detect when the EMAC transmitter for the corresponding channel has halted This is useful when the application appends additional packet descriptors to a transmit queue list that is already owned by...

Page 1428: ...newly appended descriptor The EMAC will use the new pointer value and proceed to the next descriptor unless the pNext value has already been read In this latter case the receiver will halt the receiv...

Page 1429: ...00u define EMAC_DSC_FLAG_OVERRUN 0x00100000u define EMAC_DSC_FLAG_CODEERROR 0x00080000u define EMAC_DSC_FLAG_ALIGNERROR 0x00040000u define EMAC_DSC_FLAG_CRCERROR 0x00020000u define EMAC_DSC_FLAG_NOMAT...

Page 1430: ...flag set This flag is initially cleared by the software application before adding the descriptor to the receive queue This bit is set by the EMAC on EOP descriptors 28 2 6 5 8 Ownership OWNER Flag Whe...

Page 1431: ...s not discarded because the RXCSFEN bit was set in the RXMBPENABLE 28 2 6 5 16 Control Flag This flag is set by the EMAC in the SOP buffer descriptor if the received packet is an EMAC control frame an...

Page 1432: ...bytes of internal memory CPPI buffer descriptor memory The internal memory block is essential for allowing the EMAC to operate more independently of the CPU It also prevents memory underflow condition...

Page 1433: ...r EMAC The device supports a single PHY being connected to the EMAC at any given time The MDIO module is designed to allow almost transparent operation of the MDIO interface with little maintenance fr...

Page 1434: ...in order to enumerate the PHY devices in the system The module tracks whether or not a PHY on a particular address has responded and whether or not the PHY currently has a link Using this information...

Page 1435: ...tus register ALIVE and MDIO PHY link status register LINK The corresponding bit for the connected PHY 0 31 is set in ALIVE if the PHY responded to the read request The corresponding bit is set in LINK...

Page 1436: ...PHY register you want to write 3 The write operation to the PHY is scheduled and completed by the MDIO module Completion of the write operation can be determined by polling the GO bit in USERACCESSn...

Page 1437: ...Example 28 3 USERACCESS0 is assumed Note that this implementation does not check the ACK bit in USERACCESSn on PHY register reads does not follow the procedure outlined in Section 28 2 8 2 3 Since the...

Page 1438: ...face between the EMAC module and the system core is provided through the EMAC control module The EMAC consists of the following logical components The receive path includes receive DMA engine receive...

Page 1439: ...for both transmit and receive channels 28 2 9 1 9 EMAC Interrupt Controller The interrupt controller contains the interrupt related registers and logic The 26 raw EMAC interrupts are input to this su...

Page 1440: ...their associated memory buffer Thus it is possible to delay servicing of the EMAC interrupt if there are real time tasks to perform Eight channels are supplied for both transmit and receive operation...

Page 1441: ...ve flow control does not depend on the value of the incoming frame destination address A collision is generated for any incoming packet regardless of the destination address if any EMAC enabled channe...

Page 1442: ...outgoing CRC 28 2 10 2 3 Adaptive Performance Optimization APO The EMAC incorporates adaptive performance optimization APO logic that may be enabled by setting the TXPACE bit in the MAC control regis...

Page 1443: ...w pause time value is 0 then the transmit pause timer immediately expires else The EMAC transmit pause timer immediately is set to the new pause frame pause time value Any remaining pause time from th...

Page 1444: ...ts determine whether the given channel is enabled when set to 1 to receive frames with a matching unicast or multicast destination address The RXBROADEN bit in the receive multicast broadcast promiscu...

Page 1445: ...dcast promiscuous channel enable register RXMBPENABLE 28 2 11 5 Host Free Buffer Tracking The host must track free buffers for each enabled channel including unicast multicast broadcast and promiscuou...

Page 1446: ...RC bytes If the frame length is 1520 there are 1518 bytes transferred to memory regardless of the RXPASSCRC bit value The last two bytes are the first two CRC bytes If the frame length is 1521 there a...

Page 1447: ...roper oversize jabber code align CRC data and control frames transferred to promiscuous channel No undersized frames are transferred 0 1 1 1 1 All nonaddress matching frames with and without errors tr...

Page 1448: ...is filtered and the appropriate statistic s are incremented however the RXCEFEN bit in the receive multicast broadcast promiscuous channel enable register RXMBPENABLE affects overrun frame treatment T...

Page 1449: ...trol register TXCONTROL Write the appropriate TXnHDP with the pointer to the first descriptor to start transmit operations 28 2 12 2 Transmit Channel Teardown The host commands a transmit channel tear...

Page 1450: ...fer descriptor reads for the cell data Latency to system s internal and external RAM can be controlled through the use of the transfer node priority allocation register available at the device level L...

Page 1451: ...software to verify that there are no pending frames to be transferred After writing a 1 to the SOFTRESET bit it may be polled to determine if the reset has occurred If a 1 is read the reset has not y...

Page 1452: ...t is mapped to a CPU interrupt general masking and unmasking of interrupts to control reentrancy should be done at the chip level by manipulating the interrupt core enable mask registers 28 2 16 3 MDI...

Page 1453: ...nel n free buffer count registers RXnFREEBUFFER receive channel n flow control threshold register RXnFLOWTHRESH and receive filter low priority frame threshold register RXFILTERLOWTHRESH 7 Most device...

Page 1454: ...e s associated transmit completion pointer in the transmit DMA state RAM The data written by the host buffer descriptor address of the last processed buffer is compared to the data in the register wri...

Page 1455: ...y acknowledge interrupts for every packet The application software must acknowledge the EMAC control module after processing packets by writing the appropriate C0TX key to the EMAC End Of Interrupt Ve...

Page 1456: ...threshold logic as does flow control but the interrupts are independently enabled from flow control The threshold interrupts are intended to give the host an indication that resources are running low...

Page 1457: ...edge or pulse triggered signal the application software must make use of the interrupt control logic contained in the EMAC control module Section 28 2 7 3 discusses the interrupt control contained in...

Page 1458: ...chnical Reference Manual to identify the causes of a system reset Upon a system reset the registers are reset to their default value When powering up after a system reset all the EMAC submodules need...

Page 1459: ...egister Section 28 3 4 14h C0RXEN EMAC Control Module Receive Interrupt Enable Register Section 28 3 5 18h C0TXEN EMAC Control Module Transmit Interrupt Enable Register Section 28 3 6 1Ch C0MISCEN EMA...

Page 1460: ...fies the EMAC Control Module revision 4EC8 0100h Current revision of the EMAC Control Module 28 3 2 EMAC Control Module Software Reset Register SOFTRESET The EMAC Control Module Software Reset Registe...

Page 1461: ...18 17 16 Reserved C0TXPACEEN C0RXPACEEN R 0 R W 0 R W 0 15 12 11 0 Reserved INTPRESCALE R 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 28 13 EMAC Control Module Interrupt Contr...

Page 1462: ...PULSE interrupt generation for RX Channel 6 0 C0RXTHRESHPULSE generation is disabled for RX Channel 6 1 C0RXTHRESHPULSE generation is enabled for RX Channel 6 5 RXCH5THRESHEN Enable C0RXTHRESHPULSE in...

Page 1463: ...PULSE interrupt generation for RX Channel 6 0 C0RXPULSE generation is disabled for RX Channel 6 1 C0RXPULSE generation is enabled for RX Channel 6 5 RXCH5EN Enable C0RXPULSE interrupt generation for R...

Page 1464: ...TXPULSE interrupt generation for TX Channel 6 0 C0TXPULSE generation is disabled for TX Channel 6 1 C0TXPULSE generation is enabled for TX Channel 6 5 TXCH5EN Enable C0TXPULSE interrupt generation for...

Page 1465: ...3 STATPENDEN Enable C0MISCPULSE interrupt generation when EMAC statistics interrupts are generated 0 C0MISCPULSE generation is disabled for EMAC STATPEND interrupts 1 C0MISCPULSE generation is enabled...

Page 1466: ...tions to generate a C0RXTHRESHPULSE interrupt 5 RXCH5THRESHSTAT Interrupt status for RX Channel 5 masked by the C0RXTHRESHEN register 0 RX Channel 5 does not satisfy conditions to generate a C0RXTHRES...

Page 1467: ...to generate a C0RXPULSE interrupt 5 RXCH5STAT Interrupt status for RX Channel 5 masked by the C0RXEN register 0 RX Channel 5 does not satisfy conditions to generate a C0RXPULSE interrupt 1 RX Channel...

Page 1468: ...s to generate a C0TXPULSE interrupt 5 TXCH5STAT Interrupt status for TX Channel 5 masked by the C0TXEN register 0 TX Channel 5 does not satisfy conditions to generate a C0TXPULSE interrupt 1 TX Channe...

Page 1469: ...d 3 STATPENDSTAT Interrupt status for EMAC STATPEND masked by the C0MISCEN register 0 EMAC STATPEND does not satisfy conditions to generate a C0MISCPULSE interrupt 1 EMAC STATPEND satisfies conditions...

Page 1470: ...scription 31 6 Reserved 0 Reserved 5 0 RXIMAX 2h 3Fh RXIMAX is the desired number of C0RXPULSE interrupts generated per millisecond when C0RXPACEEN is enabled in INTCONTROL The pacing mechanism can be...

Page 1471: ...Description 31 6 Reserved 0 Reserved 5 0 TXIMAX 2h 3Fh TXIMAX is the desired number of C0TXPULSE interrupts generated per millisecond when C0TXPACEEN is enabled in INTCONTROL The pacing mechanism can...

Page 1472: ...te Interrupt Unmasked Register Section 28 4 7 24h USERINTMASKED MDIO User Command Complete Interrupt Masked Register Section 28 4 8 28h USERINTMASKSET MDIO User Command Complete Interrupt Mask Set Reg...

Page 1473: ...state machine 1 Enable the MDIO state machine 29 Reserved 0 Reserved 28 24 HIGHEST_USER_CHANNEL 0 1Fh Highest user channel that is available in the module It is currently set to 1 This implies that M...

Page 1474: ...of the presence or not of a PHY with the corresponding address Writing a 1 to any bit will clear it writing a 0 has no effect 0 The PHY fails to acknowledge the access 1 The most recent access to the...

Page 1475: ...d Value Description 31 2 Reserved 0 Reserved 1 USERPHY1 MDIO Link change event raw value When asserted the bit indicates that there was an MDIO link change event that is change in the LINK register co...

Page 1476: ...asserted the bit indicates that there was an MDIO link change event that is change in the LINK register corresponding to the PHY address in USERPHYSEL1 and the corresponding LINKINTENB bit was set Wr...

Page 1477: ...USERINTRAW Field Descriptions Bit Field Value Description 31 2 Reserved 0 Reserved 1 USERACCESS1 MDIO User command complete event bit When asserted the bit indicates that the previously scheduled PHY...

Page 1478: ...USERACCESS1 Masked value of MDIO User command complete interrupt When asserted The bit indicates that the previously scheduled PHY read or write command using that particular USERACCESS1 register has...

Page 1479: ...MDIO user interrupt mask set for USERINTMASKED 1 Setting a bit to 1 will enable MDIO user command complete interrupts for the USERACCESS1 register MDIO user interrupt for USERACCESS1 is disabled if t...

Page 1480: ...iptions Bit Field Value Description 31 2 Reserved 0 Reserved 1 USERACCESS1 MDIO user command complete interrupt mask clear for USERINTMASKED 1 Setting the bit to 1 will disable further user command co...

Page 1481: ...do so this is not an instantaneous process Writing a 0 to this bit has no effect This bit is writeable only if the MDIO state machine is enabled This bit will self clear when the requested access has...

Page 1482: ...ter 0 USERPHYSEL0 Field Descriptions Bit Field Value Description 31 8 Reserved 0 Reserved 7 LINKSEL Link status determination select bit Default value is 0 which implies that the link status is determ...

Page 1483: ...do so this is not an instantaneous process Writing 0 to this bit has no effect This bit is writeable only if the MDIO state machine is enabled This bit will self clear when the requested access has be...

Page 1484: ...iptions Bit Field Value Description 31 8 Reserved 0 Reserved 7 LINKSEL Link status determination select bit Default value is 0 which implies that the link status is determined by the MDIO state machin...

Page 1485: ...Interrupt Mask Clear Register Section 28 5 20 100h RXMBPENABLE Receive Multicast Broadcast Promiscuous Channel Enable Register Section 28 5 21 104h RXUNICASTSET Receive Unicast Enable Set Register Se...

Page 1486: ...HDP Transmit Channel 6 DMA Head Descriptor Pointer Register Section 28 5 46 61Ch TX7HDP Transmit Channel 7 DMA Head Descriptor Pointer Register Section 28 5 46 620h RX0HDP Receive Channel 0 DMA Head D...

Page 1487: ...ansmit Frames Register Section 28 5 50 16 240h TXPAUSEFRAMES Pause Transmit Frames Register Section 28 5 50 17 244h TXDEFERRED Deferred Transmit Frames Register Section 28 5 50 18 248h TXCOLLISION Tra...

Page 1488: ...ision ID Register TXREVID Field Descriptions Bit Field Value Description 31 0 TXREV Transmit module revision 4EC0 020Dh Current transmit revision value 28 5 2 Transmit Control Register TXCONTROL The t...

Page 1489: ...transmit channel teardown is commanded by writing the encoded value of the transmit channel to be torn down The teardown register is read as 0 0 Teardown transmit channel 0 1h Teardown transmit chann...

Page 1490: ...ceive Teardown Register RXTEARDOWN The receive teardown register RXTEARDOWN is shown in Figure 28 47 and described in Table 28 45 Figure 28 47 Receive Teardown Register RXTEARDOWN 31 16 Reserved R 0 1...

Page 1491: ...TX4PEND TX3PEND TX2PEND TX1PEND TX0PEND R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 LEGEND R Read only n value after reset Table 28 46 Transmit Interrupt Status Unmasked Register TXINTSTATRAW Field Descriptions...

Page 1492: ...6 5 4 3 2 1 0 TX7PEND TX6PEND TX5PEND TX4PEND TX3PEND TX2PEND TX1PEND TX0PEND R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 LEGEND R Read only n value after reset Table 28 47 Transmit Interrupt Status Masked Regist...

Page 1493: ...Bit Field Value Description 31 8 Reserved 0 Reserved 7 TX7MASK 0 1 Transmit channel 7 interrupt mask set bit Write 1 to enable interrupt a write of 0 has no effect 6 TX6MASK 0 1 Transmit channel 6 int...

Page 1494: ...Field Value Description 31 8 Reserved 0 Reserved 7 TX7MASK 0 1 Transmit channel 7 interrupt mask clear bit Write 1 to disable interrupt a write of 0 has no effect 6 TX6MASK 0 1 Transmit channel 6 int...

Page 1495: ...lue after reset Table 28 50 MAC Input Vector Register MACINVECTOR Field Descriptions Bit Field Value Description 31 28 Reserved 0 Reserved 27 STATPEND 0 1 EMAC module statistics interrupt STATPEND pen...

Page 1496: ...Of Interrupt Vector Register MACEOIVECTOR Field Descriptions Bit Field Value Description 31 5 Reserved 0 Reserved 4 0 INTVECT Acknowledge EMAC Control Module Interrupts 0h Acknowledge C0RXTHRESH Inte...

Page 1497: ...Descriptions Bit Field Value Description 31 16 Reserved 0 Reserved 15 RX7THRESHPEND 0 1 RX7THRESHPEND raw interrupt read before mask 14 RX6THRESHPEND 0 1 RX6THRESHPEND raw interrupt read before mask 1...

Page 1498: ...able 28 53 Receive Interrupt Status Masked Register RXINTSTATMASKED Field Descriptions Bit Field Value Description 31 16 Reserved 0 Reserved 15 RX7THRESHPEND 0 1 RX7THRESHPEND masked interrupt read 14...

Page 1499: ...shold mask set bit Write 1 to enable interrupt a write of 0 has no effect 12 RX4THRESHMASK 0 1 Receive channel 4 threshold mask set bit Write 1 to enable interrupt a write of 0 has no effect 11 RX3THR...

Page 1500: ...k clear bit Write 1 to disable interrupt a write of 0 has no effect 12 RX4THRESHMASK 0 1 Receive channel 4 threshold mask clear bit Write 1 to disable interrupt a write of 0 has no effect 11 RX3THRESH...

Page 1501: ...Reserved 0 Reserved 1 HOSTPEND 0 1 Host pending interrupt HOSTPEND raw interrupt read before mask 0 STATPEND 0 1 Statistics pending interrupt STATPEND raw interrupt read before mask 28 5 18 MAC Inter...

Page 1502: ...bit Write 1 to enable interrupt a write of 0 has no effect 0 STATMASK 0 1 Statistics interrupt mask set bit Write 1 to enable interrupt a write of 0 has no effect 28 5 20 MAC Interrupt Mask Clear Reg...

Page 1503: ...er descriptor packet length 29 RXQOSEN Receive quality of service enable bit 0 Receive QOS is disabled 1 Receive QOS is enabled 28 RXNOCHAIN Receive no buffer chaining bit 0 Received frames can span m...

Page 1504: ...ect channel 1 to receive promiscuous frames 2h Select channel 2 to receive promiscuous frames 3h Select channel 3 to receive promiscuous frames 4h Select channel 4 to receive promiscuous frames 5h Sel...

Page 1505: ...CH0EN R W1S 0 R W1S 0 R W1S 0 R W1S 0 R W1S 0 R W1S 0 R W1S 0 R W1S 0 LEGEND R W Read Write R Read only W1S Write 1 to set writing a 0 has no effect n value after reset Table 28 61 Receive Unicast Ena...

Page 1506: ...no effect 4 RXCH4EN 0 1 Receive channel 4 unicast enable clear bit Write 1 to clear the enable a write of 0 has no effect 3 RXCH3EN 0 1 Receive channel 3 unicast enable clear bit Write 1 to clear the...

Page 1507: ...bytes at the beginning of the data and that valid data begins on the first byte of the buffer A value of Fh 15 indicates that the first 15 bytes of the buffer are to be ignored by the EMAC and that v...

Page 1508: ...egister RXnFREEBUFFER is shown in Figure 28 69 and described in Table 28 67 Figure 28 69 Receive Channel n Free Buffer Count Register RXnFREEBUFFER 31 16 Reserved R 0 15 0 RXnFREEBUF WI 0 LEGEND R Rea...

Page 1509: ...Block all EMAC DMA controller writes to the receive buffer descriptor offset buffer length words during packet processing When this bit is set the EMAC will never write the third word to any receive...

Page 1510: ...ess of this bit setting The RXMBPENABLE bits determine whether or not received pause frames are transferred to memory 0 Transmit flow control is disabled Full duplex mode incoming pause frames are not...

Page 1511: ...d host errors The host should read this field after a host error interrupt HOSTPEND to determine the error Host error interrupts require hardware reset in order to recover A 0 packet length is an erro...

Page 1512: ...e channel 3 4h The host error occurred on receive channel 4 5h The host error occurred on receive channel 5 6h The host error occurred on receive channel 6 7h The host error occurred on receive channe...

Page 1513: ...onjunction with SOFT bit to determine the emulation suspend mode 0 Free running mode is disabled During emulation halt SOFT bit determines operation of EMAC 1 Free running mode is enabled During emula...

Page 1514: ...in the receive FIFO 15 8 ADDRESSTYPE 2h Address type 7 0 MACCFIG 2h MAC configuration value 28 5 34 Soft Reset Register SOFTRESET The soft reset register SOFTRESET is shown in Figure 28 75 and descri...

Page 1515: ...8 MACSRCADDR0 0 FFh MAC source address lower 8 0 bits byte 0 7 0 MACSRCADDR1 0 FFh MAC source address bits 15 8 byte 1 28 5 36 MAC Source Address High Bytes Register MACSRCADDRHI The MAC source addres...

Page 1516: ...64 bit hash table stored in MACHASH1 and MACHASH2 that indicates whether a particular address should be accepted or not The MAC hash address register 1 MACHASH1 is shown in Figure 28 78 and described...

Page 1517: ...be observed for test purposes This field is loaded automatically according to the backoff algorithm and is decremented by one for each slot time after the collision 28 5 40 Transmit Pacing Algorithm...

Page 1518: ...outgoing pause frame with pause time of FFFFh The receive pause timer is decremented at slot time intervals If the receive pause timer decrements to 0 then another outgoing pause frame is sent and the...

Page 1519: ...egister MACADDRLO Field Descriptions Bit Field Value Description 31 21 Reserved 0 Reserved 20 VALID Address valid bit This bit should be cleared to zero for unused address channels 0 Address is not va...

Page 1520: ...bits 47 40 byte 5 Bit 40 is the group bit It is forced to 0 and read as 0 Therefore only unicast addresses are represented in the address table 28 5 45 MAC Index Register MACINDEX The MAC index regist...

Page 1521: ...in the queue for the selected channel Writing to these locations when they are nonzero is an error except at reset Host software must initialize these locations to 0 on reset 28 5 47 Receive Channel...

Page 1522: ...uffer descriptor address for the last buffer processed by the host during interrupt processing The EMAC uses the value written to determine if the interrupt should be deasserted 28 5 49 Receive Channe...

Page 1523: ...W Read Write WD Write to decrement n value after reset 28 5 50 1 Good Receive Frames Register RXGOODFRAMES The total number of good frames received on the EMAC A good frame is defined as having all of...

Page 1524: ...romiscuous mode Was of length 64 to RXMAXLEN bytes inclusive Had no alignment or code error Had a CRC error A CRC error is defined as having all of the following A frame containing an even number of n...

Page 1525: ...e EMAC An undersized frame is defined as having all of the following Was any data frame that matched a unicast broadcast or multicast address or matched due to promiscuous mode Was less than 64 bytes...

Page 1526: ...estination channel flow control threshold register RXnFLOWTHRESH value was greater than or equal to the channel s corresponding free buffer register RXnFREEBUFFER value Was of length 64 to RXMAXLEN RX...

Page 1527: ...e only transmitted in full duplex mode carrier loss and collisions have no effect on this statistic Transmitted pause frames are always 64 byte multicast frames so appear in the multicast transmit fra...

Page 1528: ...es when transmission was abandoned due to excessive collisions Such a frame is defined as having all of the following Was any data or MAC control frame destined for any unicast broadcast or multicast...

Page 1529: ...t experience late collisions excessive collisions underrun or carrier sense error Was exactly 64 bytes long If the frame was being transmitted and experienced carrier loss that resulted in a frame of...

Page 1530: ...EN Octet Frames Register FRAME1024TUP The total number of 1024 byte to RXMAXLEN byte frames received and transmitted on the EMAC Such a frame is defined as having all of the following Any data or MAC...

Page 1531: ...ame is defined as having all of the following Was any data or MAC control frame that matched a unicast broadcast or multicast address or matched due to promiscuous mode Was of any size including less...

Page 1532: ...porated Universal Serial Bus USB Chapter 29 SPNU503C March 2018 Universal Serial Bus USB This chapter describes the universal serial bus USB controller on the microcontroller Topic Page 29 1 Overview...

Page 1533: ...accesses these registers via the module s peripheral bus To reduce processor software and interrupt overhead the USB host controller generates USB traffic based on data structures and data buffers sto...

Page 1534: ...A register always reports two available USB host ports regardless of the top level pin multiplexing settings Table 29 1 USB Host Device Interface Signal Multiplexing and Control USB Host Device Interf...

Page 1535: ...ompletion codes marked as Device Not Responding TDs on any of the lists periodic control bulk and isochronous can cause such an occurrence The USB specification requires that system software must prov...

Page 1536: ...C interrupt disable Section 29 2 4 6 FCF7 8B18h HCHCCA Physical address of HCCA 2 Section 29 2 4 7 FCF7 8B1Ch HCPERIODCURRENTED Physical address of current periodic endpoint descriptor 2 Section 29 2...

Page 1537: ...Mode Register HCCONTROL The HC operating mode register Figure 29 2 controls the operating mode of the USB host controller Figure 29 2 HC Operating Mode Register HCCONTROL address FCF78B04h 31 16 Reser...

Page 1538: ...ust point to a valid ED or be 0 before setting this bit 4 CLE Control list enable 0 Control ED list is not processed in the next 1 ms frame Host controller driver can modify the control ED list If dri...

Page 1539: ...ver to gain ownership of the host controller The device does not support SMI interrupts so no ownership change interrupt occurs 2 BLF 0 1 Bulk list filled The host controller driver must set this bit...

Page 1540: ...effect 1 Write of 1 clears this bit 5 FNO Frame number overflow When 1 indicates a frame number overflow has occurred 0 Write of 0 has no effect 1 Write of 1 clears this bit 4 UE Unrecoverable error W...

Page 1541: ...ager VIM 0 Write of 0 has no effect 1 Write of 1 sets this bit 30 OC 0 Ownership change This bit has no effect on the device 29 7 Reserved 0 Reserved 6 RHSC Root hub status change When 1 and MIE is 1...

Page 1542: ...o propagate to the Vectored Interrupt Manager VIM When 0 or when MIE is 0 scheduling overrun interrupts do not propagate 0 Write of 0 has no effect 1 Write of 1 sets this bit 29 2 4 6 HC Interrupt Dis...

Page 1543: ...RD bit 2 SF Start of frame Read always returns 0 0 Write of 0 has no effect 1 Write of 1 clears the HCINTERRUPTENABLE SF bit 1 WDH Write done head Read always returns 0 0 Write of 0 has no effect 1 Wr...

Page 1544: ...List EDs are assumed to begin at 16 byte aligned address so bits 3 0 of this pointer are assumed to be 0 See Section 29 2 9 for the restrictions on physical addresses 3 0 Reserved 0 Reserved 29 2 4 9...

Page 1545: ...r the restrictions on physical addresses A value of 0x0000000 indicates that the USB host controller has reached the end of the control ED list without finding any transfers to process This register i...

Page 1546: ...trictions on physical addresses A value of 0x0000000 indicates that the USB host controller has reached the end of the bulk ED list without finding any transfers to process This register is automatica...

Page 1547: ...erved 13 0 FI 0 3FFFh Frame interval Number of 12 MHz clocks in the USB frame Nominally this is set to 11 999 to give a 1 ms frame The host controller driver can make minor changes to this field to at...

Page 1548: ...r frame number is incremented its new value is written to the HCCA and the USB host controller sets the SOF interrupt status bit and begins processing the ED lists 29 2 4 17 HC Periodic Start Register...

Page 1549: ...4 19 HC Root Hub A Register HCRHDESCRIPTORA The HC root hub A register defines several aspects of the USB host controller root hub functionality Figure 29 19 HC Root Hub A Register HCRHDESCRIPTORA add...

Page 1550: ...per the power switching mode field 1 Indicates that VBUS power switching is not supported and that power is available to all downstream ports when the USB host controller is powered This is the defaul...

Page 1551: ...t has port power controlled by the global power control If set per port power control is implemented for the corresponding port If clear global power control is implemented for the corresponding port...

Page 1552: ...power status bits for all ports if power switching mode is 0 A write of 1 sets port power status bits for ports with their corresponding port power control mask bits cleared if power switching mode is...

Page 1553: ...clears this bit 19 OCIC Port 0 overcurrent indicator change This bit indicates when 1 that the port 0 port overcurrent indicator has changed 0 Write of 0 has no effect 1 Write of 1 clears this bit 18...

Page 1554: ...naling on port 0 A write of 1 when port 0 port suspend status is 0 has no effect 2 PSS SPS Port 0 port suspend status set port suspend When read as 0 indicates that port 0 is not in the USB suspend st...

Page 1555: ...this bit 19 OCIC Port 1 overcurrent indicator change This bit indicates when 1 that the port 1 port overcurrent indicator has changed 0 Write of 0 has no effect 1 Write of 1 clears this bit 18 PSSC P...

Page 1556: ...gnaling on port 1 A write of 1 when port 1 port suspend status is 0 has no effect 2 PSS SPS Port 1 port suspend status set port suspend When read as 0 indicates that port 1 is not in the USB suspend s...

Page 1557: ...eveloper determine why the USB host issued an access to a physical address that resulted in an unrecoverable error 29 2 4 25 Host UE Status Register HOSTUESTATUS The host UE status register reports th...

Page 1558: ...ller signals an unrecoverable error 1 When 1 the USB host controller bus time out counter is disabled and the host controller waits indefinitely for completion of a USB host controller access to syste...

Page 1559: ...ransitions out of reset After system software turns on the clock to the USB host controller and removes it from reset it is necessary to wait until the USB host controller internal reset completes To...

Page 1560: ...points to the most recent transfer descriptor that has been retired 29 2 11 NULL Pointers The OHCI Specification for USB uses NULL pointers to indicate the end of a list The USB host controller compar...

Page 1561: ...Section 29 3 1 8 FCF7 8A10h DEVSTAT Device status Section 29 3 1 9 FCF7 8A12h SOF Start of frame Section 29 3 1 10 FCF7 8A14h IRQ_EN Interrupt enable Section 29 3 1 11 FCF7 8A16h DMA_IRQ_EN DMA interr...

Page 1562: ...denied Device reset and USB controller reset have no effect on this register Figure 29 28 Revision Register REV address FCF78A00h 15 8 Reserved R 0 7 0 REV_NB R 61h LEGEND R Read only n value at rese...

Page 1563: ...e after system reset or USB reset is low 5 EP_SEL Set by the CPU to access the status STAT_FLG RXFSTAT and data DATA registers for the endpoint selected If the EP_NUM EP_DIR bit is set to 0 the CPU ca...

Page 1564: ...d to this register is denied Figure 29 30 Data Register DATA address FCF78A04h 15 0 DATA R W 0 LEGEND R W Read Write n value after reset Table 29 33 Data Register DATA Field Descriptions Bit Field Des...

Page 1565: ...controller must disable the DMA channel before setting halt condition for this endpoint 0 No action 1 Halt endpoint Always read 0 5 3 Reserved 0 Reserved Reads return zeros writes have no effect 2 SET...

Page 1566: ...NOTE The updates for non ISO transactions are done at the end of each non transparent and valid transaction to a given endpoint if no non handled interrupt is pending on the endpoint The definition of...

Page 1567: ...rrectly This happens when the core detects an error in the data packet CRC bit stuffing PID check or when there is an overrun condition in the FIFO When this bit is set the FIFO contents are automatic...

Page 1568: ...t 1 A NAK handshake packet was returned and SYSCON1 NAK_EN bit is set Value after system reset or USB reset is low 3 ACK The transaction acknowledge non ISO bit only concerns non ISO endpoints This bi...

Page 1569: ...the EP_NUM EP_SEL bit is not set for the endpoint No receive FIFO status exists for the setup FIFO because 8 bytes are always expected Figure 29 33 Receive FIFO Status Register RXFSTAT address FCF78A...

Page 1570: ...it can be set by the USB device controller to select little or big endian format on data access read or write See Table 29 38 0 Little endian 1 Big endian The value after USB device controller hardwar...

Page 1571: ...USB reset it is unchanged 1 SOFF_DIS When the shutoff disable bit is set it disables the power shutoff circuitry 0 Power shutoff circuitry is enabled 1 Power shutoff circuitry is disabled The value af...

Page 1572: ...sponse to a USB command where either the command itself or its data is invalid Asserting this bit forces the non autodecoded command to complete with a STALL handshake It has no effect for autodecoded...

Page 1573: ...alue at reset Table 29 40 Device Status Register DEVSTAT Field Descriptions Bit Field Value Description 15 10 Reserved 0 Reserved 9 B_HNP_ENABLE The HNP enable for B device bit is used for On The Go f...

Page 1574: ...ed 1 Suspended Value after system reset or USB reset is low 3 CFG Configured state bit the device is attached to the USB powered has been reset has a unique address and is configured The host can use...

Page 1575: ...K is set and the frame timer is locked to the timing TF a local SOF is generated if no valid SOF has been received in an interval of TF since the last valid SOF The SOF FT_LOCK bit is cleared if a val...

Page 1576: ...e controller 0 Interrupt is disabled 1 Interrupt is enabled The value after system reset or USB reset is low for all bits except IRQ_EN DS_CHG_IE bit which remains unchanged after a reset from the USB...

Page 1577: ...5 4 3 2 1 0 Reserved TX1_DONE_IE RX1_CNT_IE RX1_EOT_IE Reserved TX0_DONE_IE RX0_CNT_IE RX0_EOT_IE R 0 R W 0 R W 0 R W 0 R 0 R W 0 R W 0 R W 0 LEGEND R W Read Write R Read only n value at reset Table...

Page 1578: ...ever set for ISO DMA transfer The core automatically sets this bit when a transmit DMA channel has completed the programmed transfer by servicing the last IN transaction from the USB host This is when...

Page 1579: ...he SOF bit location clears the flag Writing a 0 has no effect In accordance with the USB1 1 specification if SOF is received corrupted or is not received the core still sets this flag at the same rate...

Page 1580: ...y sets the EP0_RX bit when a handshake sequence occurs for a non autodecoded OUT transaction to control endpoint NAK with SYSCON1 NAK_EN set ACK or STALL 0 No action 1 OUT transaction on EP0 Value aft...

Page 1581: ...Read only n value at reset Table 29 45 Non ISO Endpoint Interrupt Status Register EPN_STAT Field Descriptions Bit Field Value Description 15 12 Reserved 0 Reserved 11 8 EPn_RX_IT_SRC The receive endpo...

Page 1582: ...errupt is asserted and the core received an odd number of bytes during the last transaction It is used to know the exact number of bytes received in case of a 16 bit read access from DATA_DMA register...

Page 1583: ...0 R W 0 LEGEND R W Read Write R Read only n value at reset Table 29 47 DMA Receive Channels Configuration Register RXDMA_CFG Field Descriptions Bit Field Value Description 15 13 Reserved 0 Reserved 12...

Page 1584: ...st channel TXDMA0_EP If the your ISO endpoint is configured on the channel 2 and it can never be serviced with low software and a fast USB host USB device controller transmit endpoint DMA channels 0 1...

Page 1585: ...used in a DMA transfer through DMA channel 0 1 or 2 Figure 29 45 DMA FIFO Data Register DATA_DMA address FCF78A24h 15 8 DATA_DMA R W 0 7 0 DATA_DMA R W 0 LEGEND R W Read Write n value at reset Table...

Page 1586: ...MA transfer size is in bytes Value after system reset or USB reset is low 14 TXn_START Transmit DMA channel n start The USB device controller sets this bit to tell the device that the main DMA system...

Page 1587: ...ce controller expects a given amount of data for the transfer Note At end of transfer the DMA channel is disabled and all OUT transactions received to the assigned endpoint are sent NAK by the core Th...

Page 1588: ...RIPTOR request preceding configuration phase Status flags STAT_FLG NON_ISO_FIFO_EMPTY and STAT_FLG NON_ISO_FIFO_FULL and overrun and underrun conditions are based on this value for all IN and OUT tran...

Page 1589: ...set Table 29 53 Receive Endpoint n Configuration Register EPn_RX Field Descriptions Bit Field Value Description 15 EPn_RX_VALID The receive endpoint n valid bit must be set by the USB device controlle...

Page 1590: ...es are unknown until first write access 11 EPn_RX_ISO The receive ISO endpoint n field must be set if the receive endpoint n type is isochronous in the desired device configuration If not set the endp...

Page 1591: ...it Field Value Description 15 EPn_TX_VALID The transmit endpoint n valid bit must be set by the USB device controller to allow transmit endpoint n to be used for USB transfers as part of the device co...

Page 1592: ...hat values are unknown until first write access 11 EPn_TX_ISO The transmit ISO endpoint n field must be set if the transmit endpoint n type is isochronous in the desired device configuration If not se...

Page 1593: ...s only on a specific style of transaction without adding in the confusion of special cases related to other styles 29 3 3 Non Isochronous Non Setup OUT USB HOST CPU Transactions Non isochronous non se...

Page 1594: ...t SYSCON1 Nak_En 1 ACK NAK STALL EP_Halted 0 1 0 0 STAT_FLG bits after interrupt ACK NAK STALL EP_Halted 0 0 1 1 0 0 1 0 or After interrupt EP s TX FIFO is empty EP TX FIFO is unchanged by this USB tr...

Page 1595: ...the endpoint causing the interrupt then write a 1 to the interrupt bit to clear it The CPU must then set EP_NUM EP_NUM to the endpoint number and EP_NUM EP_SEL to 1 and then read the endpoint status...

Page 1596: ...ansaction to the endpoint to be placed into the RX FIFO If STAT_FLG EP_HALTED has been set in response to a SET_FEATURE request sent by the USB host or if the bit is cleared control transaction only t...

Page 1597: ...ansactions It diagrams the three phases of the IN transaction the direction of information flow for each phase when endpoint specific interrupts are generated and the resulting STAT_FLG bits for the e...

Page 1598: ...terrupt SYSCON1 Nak_En 1 ACK NAK STALL EP_Halted 0 1 0 0 STAT_FLG bits after interrupt ACK NAK STALL EP_Halted 0 0 1 1 0 0 1 0 or After interrupt EP s TX FIFO is empty EP TX FIFO is unchanged by this...

Page 1599: ...Signaling NAK handshake for several endpoint transactions in a row can cause the PC host to discard the transaction so NAK is not necessarily a good mechanism in cases where the CPU is not able to ser...

Page 1600: ...tion The CPU is responsible for handling isochronous OUT data at each start of frame SOF interrupt At every SOF interrupt for each isochronous OUT endpoint CPU code must select the endpoint by writing...

Page 1601: ...ransaction Error Conditions If the CPU fails to read all of the data in the ISO OUT endpoint foreground FIFO by the time the foreground and background FIFOs are switched at the next SOF the endpoint F...

Page 1602: ...In response to the SOF interrupt for each isochronous IN endpoint CPU code selects the endpoint via the EP_NUM register and then fills the endpoint TX FIFO via the DATA register Once all the transmit...

Page 1603: ...re 29 55 and Figure 29 56 An IN or an OUT transaction is received out of a control request This transaction is automatically stalled by the core Non autodecoded control read and control write transfer...

Page 1604: ...s stage No interrupt occurs staus flags are not updated due to wrong setup or command data Setup Token Command ACK In Token Stall Status Token 0 length data Data stage Setup stage Status stage Stall A...

Page 1605: ...ta stage Occurs 1 or more times depending on the command and amount of data Setup stage Status stage EP0 RX Interrupt STAT_FLG STALL bit set Stall EP0 TX Interrupt STAT_FLG STALL bit set one per In tr...

Page 1606: ...n If the IRQ_SRC SETUP flag is asserted the CPU must discard the previously read data and handle the new setup packet as explained above Thus the CPU never misses a new occurring setup transaction per...

Page 1607: ...ds a GET_ENDPOINT DEVICE_STATUS request with a bad parameter If the autodecode mechanism senses a bad parameter in the setup stage data phase the autodecode mechanism causes a STALL handshake to be si...

Page 1608: ...the interface set by setting CTRL RESET_EP control bits and then set halt conditions for endpoints not used by this interface Other CPU required actions are specific to the request and not detailed in...

Page 1609: ...any time without the status stage and resend another SETUP command The CPU code must be able to operate correctly in this situation After completion of the data stage a status stage OUT transaction oc...

Page 1610: ...SET_ADDRESS autodecoded command only the seven LSBs are significant for the new address decimal value from 0 to 127 all others are discarded Table 29 55 Autodecoded Versus Non Autodecoded Control Req...

Page 1611: ...f interface setting number is not correct If the request is SET_INTER FACE the CPU must reset endpoints used by the interface and halt endpoints not used by the interface setting before allowing statu...

Page 1612: ...B Device Controller www ti com 1612 SPNU503C March 2018 Submit Documentation Feedback Copyright 2018 Texas Instruments Incorporated Universal Serial Bus USB For each endpoint the CPU must write on the...

Page 1613: ...d interrupt signals After a USB reset all IRQ_EN registers except DS_CHG are cleared They must be re enabled SELF_PWR SOFF_DIS PULLUP_EN www ti com USB Device Controller 1613 SPNU503C March 2018 Submi...

Page 1614: ...O 1 EPn_RX_PTR PTR_FLAG Another OUT endpoint to configure EPn Another IN endpoint to configure EPn Yes Yes No Yes No Yes No No Yes Yes No No Yes Yes No No Double buffering is activated in DMA mode onl...

Page 1615: ...uble buffering is allowed or not is transparent to the CPU unless both FIFOs are cleared through a CTRL CLR_EP or CTRL RESET_EP In that case and in the case where the CPU finishes to handle an interru...

Page 1616: ...An START is set by the LH End of prepare for USB TX transfer for endpoint n routine At this point TX data is written in response to EPn_TX interrupts Write EP_NUM register 6 wait states EP_NUM EP_NUM...

Page 1617: ...irection 29 3 11 Important Note on USB Device Interrupts When an endpoint interrupt is asserted the CPU writes the EP_NUM register with the EP_NUM EP_SEL bit set to 1 The CPU must finish the interrupt...

Page 1618: ...Yes No Yes Yes Must be IRQ_SRC DS_CHG USB Device Controller www ti com 1618 SPNU503C March 2018 Submit Documentation Feedback Copyright 2018 Texas Instruments Incorporated Universal Serial Bus USB Fig...

Page 1619: ...NUM 0 EP_NUM EP_DIR 1 EP_NUM EP_SEL 1 EP_NUM SETUP_SEL 0 No Write EP_NUM register EP_NUM EP_NUM 0 EP_NUM EP_DIR 1 EP_NUM EP_SEL 0 EP_NUM SETUP_SEL 0 Write EP_NUM register EP_NUM EP_NUM 0 EP_NUM EP_DIR...

Page 1620: ...CMD to 1 Yes Enable NAK interrupt by setting SYSCON1 NAK_EN to 1 if not already enabled No Write EP_NUM register EP_NUM EP_NUM 0 EP_NUM EP_DIR 0 EP_NUM EP_SEL 1 EP_NUM SETUP_SEL 0 Yes Write EP_NUM reg...

Page 1621: ...lly stalled by the core Yes wlength_count is 0 OUT transactions with more bytes than expected are automatically stalled by the core Yes No No Yes Yes No Must be STAT_FLG STALL Write EP_NUM register EP...

Page 1622: ..._SEL 0 Write EP_NUM register EP_NUM EP_NUM 0 EP_NUM EP_DIR 1 EP_NUM EP_SEL 0 EP_NUM SETUP_SEL 0 USB Device Controller www ti com 1622 SPNU503C March 2018 Submit Documentation Feedback Copyright 2018 T...

Page 1623: ...ol or write status stage are automatically stalled by the core application s TX buffer based on amount previously put into TX FIFO 0 or other data to send Write non ISO TX data No Write EP_NUM registe...

Page 1624: ...STALL_CMD to 1 Yes Enable NAK interrupt by setting SYSCON1 NAK_EN to 1 if not already enabled No Write EP_NUM register EP_NUM EP_NUM 0 EP_NUM EP_DIR 0 EP_NUM EP_SEL 1 EP_NUM SETUP_SEL 0 Yes Write EP_...

Page 1625: ...powered Default The device is attached to the USB is powered and has been reset Addressed The device is attached to the USB is powered has been reset and an address has been assigned The device moves...

Page 1626: ...not specified by USB 1 1 specifications Remote enabled SET_ADDRESS 0 or SET_CONFIGURATION USB Reset wake up Remote enabled wake up Remote enabled wake up A A A A B B USB Device Controller www ti com 1...

Page 1627: ...upt No Yes Yes No Device state must be at least default at this point Yes No Yes No Yes No Yes No Yes No Must be not configured yet Yes No IRQ_SRC DS_CHG interrupt flag is cleared inside the attached...

Page 1628: ...ce Controller www ti com 1628 SPNU503C March 2018 Submit Documentation Feedback Copyright 2018 Texas Instruments Incorporated Universal Serial Bus USB 29 3 17 Device States Attached Unattached Handler...

Page 1629: ...gured state to default state transition Yes No Yes No www ti com USB Device Controller 1629 SPNU503C March 2018 Submit Documentation Feedback Copyright 2018 Texas Instruments Incorporated Universal Se...

Page 1630: ...ed handler performs the operations shown in Figure 29 73 Figure 29 73 Address Changed Handler 29 3 20 USB Device Reset Interrupt Handler When a USB reset occurs the USB module generates a general USB...

Page 1631: ...ler 1631 SPNU503C March 2018 Submit Documentation Feedback Copyright 2018 Texas Instruments Incorporated Universal Serial Bus USB Figure 29 74 USB Device Reset Handler Flowchart 29 3 21 Suspend Resume...

Page 1632: ...CPU can modify its value at suspend interrupt time if necessary A USB reset is also a valid way to exit suspend mode But the suspend resume handler and the USB reset handler do not have to take this...

Page 1633: ...yright 2018 Texas Instruments Incorporated Universal Serial Bus USB Figure 29 76 Non ISO Endpoint Specific Except EP 0 ISR Flowchart 29 3 23 Non ISO Non Control OUT Endpoint Receive Interrupt Handler...

Page 1634: ...ol write data stage OUT transactions on EP0 is out of control write data stage and control read status stage are automatically stalled by the core Yes wlength_count is 0 OUT transactions with more byt...

Page 1635: ...tion STAT_FLG NON_ISO_FIFO_FULL 1 Set RXBYTE counter to EP buffer size Yes Read received bytes count in RXFSTAT RXF_COUNT Set RXBYTE counter to RXF_COUNT value No No EPn_RX EPn_RX_SIZE or DB 1 Set FIF...

Page 1636: ...t Documentation Feedback Copyright 2018 Texas Instruments Incorporated Universal Serial Bus USB 29 3 24 Non ISO Non Control IN Endpoint Transmit Interrupt Handler Figure 29 79 shows the operations nec...

Page 1637: ...ount to TX ISO packet length max is endpoint size When a Missed_in occurs missed data are from TWO frames previous Application specific actions to handle missed in data Reload TX byte count Must put m...

Page 1638: ...NUM SETUP_SEL 0 6 wait states ISO RX handler Write EP_NUM register EP_NUM EP_NUM n EP_NUM EP_DIR 1 EP_NUM EP_SEL 0 EP_NUM SETUP_SEL 0 USB Device Controller www ti com 1638 SPNU503C March 2018 Submit D...

Page 1639: ...c actions to handle case for data flush No Yes STAT_FLG ISO_ERROR 1 Application specific actions to handle unrecovered ISO packet Yes No STAT_FLG ISO_FIFO_EMPTY 1 Application specific actions to handl...

Page 1640: ..._count to TX ISO packet length max is endpoint size When a Missed_in occurs missed data are from TWO frames previous Application specific actions to handle missed in data Reload TX byte count Must put...

Page 1641: ...ce state changed X RX DMA EOT non_ISO X RX DMA trans count non_ISO X TX DMA done non_ISO X 29 3 26 1 USB Device Controller Clock Control The device global clock module GCM provides a single 48 MHz clo...

Page 1642: ...ous OUT USB HOST CPU DMA Transactions During non ISO transfers to a DMA operated OUT endpoint a request to the CPU DMA controller is generated when data have been placed into endpoint FIFO and must be...

Page 1643: ...r LH DMA read access must point to DATA_DMA register in response to DMA channel n request EP number RXDMA_CFG RXDMAn_EP 1 Host message System DMA read DMA_REQUEST 1 2 2 3 3 4 4 Rx Count IT Rx EOT IT 5...

Page 1644: ...umber n in DMAN_STAT DMAn_RX_IT_SRC register the RX DMA transfer on channel n has sent RXDMAn RXn_TC transaction count without detecting an EOT USB Device Controller www ti com 1644 SPNU503C March 201...

Page 1645: ...ti com USB Device Controller 1645 SPNU503C March 2018 Submit Documentation Feedback Copyright 2018 Texas Instruments Incorporated Universal Serial Bus USB Figure 29 87 Non ISO RX DMA Transactions Coun...

Page 1646: ...A2 registers operate for non ISO endpoints in the following manner The transfer size counter TXDMAn TXN_TSC corresponds to either the number of bytes to transmit EOT bit set or the number of buffers t...

Page 1647: ...f max transactions count IT is enabled DMA_IRQ_EN RXn_CNT_IE 1 RXDMA_CFG RXDMAn_EP LH wants to be interrupted with EOT after a given number of transactions Nt Set RXDMAn RXn_TC to Nt 1 and set RXDMAn...

Page 1648: ...new DMA transfer of EOTBn bytes could be null packet End of non ISO TX DMA handler Set IRQ_SRC TXn_DONE 1 to clear the interrupt Read the endpoint number n in DMAN_STAT DMAn_TX_IT_SRC register Initia...

Page 1649: ...tes to Transfer via 32 Bytes IN Bulk Endpoint This gives XSWL 0x3 FBT 0x47 EOTB 0x1b which means five passes of DMA transfer signaled by 5 TXn_DONE interrupts are required 1 EOT 0 FBT 0 loop 3 32768 b...

Page 1650: ...8 Isochronous IN USB HOST CPU DMA Transactions For ISO endpoints the transfer size counter TXDMAn TXn_TSC corresponds to the number of bytes to transmit The programmed size must not exceed the program...

Page 1651: ...ing with both buffers full No TX_DONE interrupt is asserted even if TXDMAn TSC bit value is 0 after the transaction If the TX DMA request is inactive when the endpoint is unselected deconfiguration is...

Page 1652: ...ed PUEN_O 1 SUSPEND_O 0 SHUTOFF_O 0 DS_WAKE_REQ_ON 0 USB reset PUEN_O 1 SUSPEND_O 1 SHUTOFF_O 1 DS_WAKE_REQ_ON 1 after DS_CHG interrupt handling Idle for more Reset or resume SHUTOFF_O value is 0 if t...

Page 1653: ...wake up the clocks Clear the GENI DS_CHG interrupt bit Wait for the GENI DS_CHG interrupt and check that DEVSTAT SUS is set www ti com USB Device Controller 1653 SPNU503C March 2018 Submit Documentati...

Page 1654: ...troller and the external USB transceiver for monitoring and controlling the differential USB signal is done via a 6 wire signaling interface with two or more additional control signals provided either...

Page 1655: ...ZO is low Ignored when GZO is high GZO DAT SE0 D D 0 0 0 0 1 1 0 1 0 X 1 0 0 1 X X Undriven Undriven RCV Input Output Output from transceiver differential receiver D D RCV 0 0 X 0 1 0 1 0 1 1 1 X VP I...

Page 1656: ...Submit Documentation Feedback Copyright 2018 Texas Instruments Incorporated Universal Serial Bus USB 29 4 4 Host Controller Connectivity With USB Transceivers To provide a robust USB solution a system...

Page 1657: ...resistor to the D or D line USB compatible upstream port transceiver Optional weak pulldown resistors can be used to hold the D and D signals at voltages below the USB transceiver VIL level when ther...

Page 1658: ...the upstream USB host controller The device provides the input pin USB_VBUS which is provided to the USB function controller This input is a CMOS input that is not rated for the full VBUS range define...

Page 1659: ...18 Data Modification Module DMM This chapter describes the functionality of the Data Modification Module DMM which provides the capability to modify data in the entire 4 GB address space of the device...

Page 1660: ...g features Acts as a bus master thus enabling direct writes to the 4GB address space without CPU intervention Writes to memory locations specified in the received packet leverages packets defined by t...

Page 1661: ...er is completely full the data will be moved to the output buffer register A two level buffer is implemented to avoid overflow conditions if the internal bus is occupied by other transactions In addit...

Page 1662: ...tting hardware module has occurred If this is the case the SRC_OVF flag Section 30 3 5 will be set and the received data will be written to the address specified in the packet The size information of...

Page 1663: ...ceived before the expected number of bits 30 2 2 Data Port The packet will be received in several subpackets depending on the width of the external data bus DMMDATA y 0 and the amount of data to be tr...

Page 1664: ...the start of a packet and will flag a PACKET_ERR_INT Section 30 3 5 DMMCLK The clock is externally generated and can be suspended between two packets For this feature CONTCLK must be set to 0 Section...

Page 1665: ...e detection of the first DMMSYNC signal after the DMM is turned on or comes out of suspend mode with COS 0 Section 30 3 1 that is before the reception of first DMMSYNC the toggling of DMMCLK would be...

Page 1666: ...on 30 3 6 18h DMMOFF2 DMM Interrupt Offset 2 Register Section 30 3 7 1Ch DMMDDMDEST DMM Direct Data Mode Destination Register Section 30 3 8 20h DMMDDMBL DMM Direct Data Mode Blocksize Register Sectio...

Page 1667: ...ts internal buffers 23 19 Reserved 0 Reads returns 0 Writes have no effect 18 CONTCLK Continuous DMMCLK input User and privilege mode read privilege mode write 0 DMMCLK is expected to be suspended bet...

Page 1668: ...other The DMM module does not receive data Ah The DMM module receives data and writes it to the buffer Privilege mode write All other Disable receive write operations Packets in reception will still b...

Page 1669: ...le Buffer Interrupt Set This enables the interrupt generation in case the buffer pointer equals the programmed value in the DMMINTPT register Section 30 3 11 This bit is only relevant in Direct Data M...

Page 1670: ...e mode read 0 No interrupt will be generated 1 An interrupt will be generated on a write to the start address of this region Privilege mode write 0 No influence on bit 1 Enable interrupt sets correspo...

Page 1671: ...erflow This enables the interrupt generation in case new data is received while the previous data still has not been transmitted User and privilege mode read 0 No interrupt will be generated 1 An inte...

Page 1672: ...0 or a reserved value the interrupt will still be generated the write to the internal RAM however will not take place User and privilege mode read 0 No interrupt will be generated 1 An interrupt will...

Page 1673: ...n value after reset Table 30 9 DMM Interrupt Clear Register DMMINTCLR Field Descriptions Bit Field Value Description 31 18 Reserved 0 Reads returns 0 Writes have no effect 17 PROG_BUFF Programmable B...

Page 1674: ...EG2 Destination 2 Region 2 Interrupt Set This disables the interrupt generation in case data was accessed at the start address of Destination 2 Region 2 This bit is only relevant in Trace Mode User an...

Page 1675: ...te 0 No influence on bit 1 Disable interrupt clears corresponding bit in DMMINTCLR DMM Interrupt Level Register DMMINTLVL 8 DEST0REG1 Destination 0 Region 1 Interrupt Set This disables the interrupt g...

Page 1676: ...e 0 No influence on bit 1 Disable interrupt clears corresponding bit in DMMINTCLR DMM Interrupt Level Register DMMINTLVL 3 DEST2_ERR Destination 2 Error Interrupt Set This disables the interrupt gener...

Page 1677: ...rupt will still be generated the write to the internal RAM however will not take place User and privilege mode read 0 No interrupt will be generated 1 An interrupt will be generated Privilege mode wri...

Page 1678: ...returns 0 Writes have no effect 17 PROG_BUFF Programmable Buffer Interrupt Level User and privilege mode read privilege mode write 0 Interrupt mapped to level 0 1 Interrupt mapped to level 1 16 EO_BU...

Page 1679: ...BUFF_OVF Write Buffer Overflow Interrupt Level User and privilege mode read privilege mode write 0 Interrupt mapped to level 0 1 Interrupt mapped to level 1 5 SRC_OVF Source Overflow Interrupt Level U...

Page 1680: ...d Write R Read only WP Write in privilege mode only C Clear n value after reset Table 30 11 DMM Interrupt Flag Register DMMINTFLG Field Descriptions Bit Field Value Description 31 18 Reserved 0 Reads...

Page 1681: ...0 No influence on bit 1 Bit will be cleared 11 DEST1REG2 Destination 1 Region 2 Interrupt Flag User and privilege mode read 0 No interrupt occurred 1 Interrupt occurred Privilege mode write 0 No influ...

Page 1682: ...0 No influence on bit 1 Bit will be cleared 5 SRC_OVF Source Overflow Interrupt Flag User and privilege mode read 0 No interrupt occurred 1 Interrupt occurred Privilege mode write 0 No influence on bi...

Page 1683: ...criptions continued Bit Field Value Description 1 DEST0_ERR Destination 0 Error Interrupt Flag User and privilege mode read 0 No interrupt occurred 1 Interrupt occurred Privilege mode write 0 No influ...

Page 1684: ...DMMOFF1 Field Descriptions Bit Field Value Description 31 5 Reserved 0 Read returns 0 Writes have no effect 4 0 OFFSET User and privilege mode read Bit Encoding Interrupt 0 Phantom All interrupt flag...

Page 1685: ...DMMOFF1 Field Descriptions Bit Field Value Description 31 5 Reserved 0 Read returns 0 Writes have no effect 4 0 OFFSET User and privilege mode read Bit Encoding Interrupt 0 Phantom All interrupt flag...

Page 1686: ...f the blocksize chosen in DMMDDMBL Section 30 3 9 User and privilege mode read current start address Privilege mode write sets start address to value written 30 3 9 DMM Direct Data Mode Blocksize Regi...

Page 1687: ...in 32 bit DDM mode bit 0 and 1 will be 0 User and privilege mode read next data entry Privilege mode write writes have no effect 30 3 11 DMM Direct Data Mode Interrupt Pointer Register DMMINTPT This r...

Page 1688: ...ion x Region 1 DMMDESTxREG1 offset 2Ch 3Ch 4Ch 5Ch 31 18 17 16 BASEADDR BLOCKADDR R WP 0 R WP 0 15 0 BLOCKADDR R WP 0 LEGEND R W Read Write WP Write in privilege mode only n value after reset Table 30...

Page 1689: ...L1 DMMDEST3BL1 Figure 30 19 DMM Destination x Blocksize 1 DMMDESTxBL1 offset 30h 40h 50h 60h 31 16 Reserved R 0 15 4 3 0 Reserved BLOCKSIZE R 0 R WP 0 LEGEND R W Read Write R Read only WP Write in pri...

Page 1690: ...ion x Region 2 DMMDESTxREG2 offset 34h 44h 54h 64h 31 18 17 16 BASEADDR BLOCKADDR R WP 0 R WP 0 15 0 BLOCKADDR R WP 0 LEGEND R W Read Write WP Write in privilege mode only n value after reset Table 30...

Page 1691: ...L2 DMMDEST3BL2 Figure 30 21 DMM Destination x Blocksize 2 DMMDESTxBL2 offset 38h 48h 58h 68h 31 16 Reserved R 0 15 4 3 0 Reserved BLOCKSIZE R 0 R WP 0 LEGEND R W Read Write R Read only WP Write in pri...

Page 1692: ...ND R W Read Write R Read only WP Write in privileged mode only n value after reset Table 30 22 DMM Pin Control 0 DMMPC0 Field Descriptions Bit Field Value Description 31 19 Reserved 0 Reads returns 0...

Page 1693: ...DIR R 0 R WP 0 R WP 0 R WP 0 15 14 13 12 11 10 9 8 DATA13DIR DATA12DIR DATA11DIR DATA10DIR DATA9DIR DATA8DIR DATA7DIR DATA6DIR R WP 0 R WP 0 R WP 0 R WP 0 R WP 0 R WP 0 R WP 0 R WP 0 7 6 5 4 3 2 1 0 D...

Page 1694: ...DMMCLK pin This bit defines whether the pin is used as input or output in GIO mode User and privilege mode read 0 Pin is used as input 1 Pin is used as output Privilege mode write 0 Pin is set to inp...

Page 1695: ...n Control 2 DMMPC2 Field Descriptions Bit Field Value Description 31 19 Reserved 0 Reads returns 0 Writes have no effect 18 ENAIN DMMENA input This bit reflects the state of the pin in all modes User...

Page 1696: ...tions Bit Field Value Description 31 19 Reserved 0 Reads returns 0 Writes have no effect 18 ENAOUT Output state of DMMENA pin This bit sets the pin to logic low or high level User and privilege mode r...

Page 1697: ...SET DATA8SET DATA7SET DATA6SET R WP 0 R WP 0 R WP 0 R WP 0 R WP 0 R WP 0 R WP 0 R WP 0 7 6 5 4 3 2 1 0 DATA5SET DATA4SET DATA3SET DATA2SET DATA1SET DATA0SET CLKSET SYNCSET R WP 0 R WP 0 R WP 0 R WP 0...

Page 1698: ...User and privilege mode read 0 Logic low output voltage is V OL or lower 1 Logic high output voltage is V OH or higher Privilege mode write 0 State of the pin is unchanged 1 Logic high output voltage...

Page 1699: ...ads returns 0 Writes have no effect 18 ENACLR Sets output state of DMMENA pin to logic low Value in the ENACLR bit clears the data output control register bit to 0 regardless of the current value in t...

Page 1700: ...pin to pull it high when the pin is in high impedance mode Figure 30 28 DMM Pin Control 6 DMMPC6 offset 84h 31 24 Reserved R 0 23 19 18 17 16 Reserved ENAPDR DATA15PDR DATA14PDR R 0 R WP 0 R WP 0 R WP...

Page 1701: ...the pin as open drain 1 CLKPDR Open Drain enable Enables open drain functionality on pin if pin is configured as GIO output DMMPC0 1 0 DMMPC1 1 1 If the pin is configured as a functional pin DMMPC0 1...

Page 1702: ...nly n value after reset Table 30 29 DMM Pin Control 7 DMMPC7 Field Descriptions Bit Field Value Description 31 19 Reserved 0 Reads returns 0 Writes have no effect 18 ENAPDIS Pull disable Removes inter...

Page 1703: ...12 11 10 9 8 DATA13PSEL DATA12PSEL DATA11PSEL DATA10PSEL DATA9PSEL DATA8PSEL DATA7PSEL DATA6PSEL R WP 1 R WP 1 R WP 1 R WP 1 R WP 1 R WP 1 R WP 1 R WP 1 7 6 5 4 3 2 1 0 DATA5PSEL DATA4PSEL DATA3PSEL...

Page 1704: ...p or pulldown functionality if DMMPC7 1 0 User and privilege mode read 0 Pulldown functionality is enabled 1 Pullup functionality is enabled Privilege mode write 0 Enables pulldown functionality 1 Ena...

Page 1705: ...U503C March 2018 RAM Trace Port RTP This chapter describes the functionality of the RAM trace port RTP module It allows the capability to perform data trace of a CPU or other master accesses to the in...

Page 1706: ...ration Trace Mode and Direct Data Mode Trace Mode Section 31 2 1 Non intrusive data trace on write or read operation Visibility of RAM content at any time on external capture hardware Trace of periphe...

Page 1707: ...a round robin scheme This means if data is available in multiple FIFOs the sequence for shifting data into the serializer is FIFO1 FIFO2 and then FIFO4 Only one entry in the respective FIFO is provide...

Page 1708: ...acket will be split up into several subpackets when transmitted over the RTP port pins depending on the port width configured The port width is configured with bits PW 1 0 in the RTPGLBCTRL register S...

Page 1709: ...into a valid trace region the data will be traced into the corresponding FIFO for this RAM block Since no address information is transmitted in Direct Data Mode the executing program has to make sure...

Page 1710: ...ss range should be excluded from the trace either the address range has to be covered by both regions for example excluding 1kB range with two 512B regions or both regions have to be programmed with t...

Page 1711: ...the read operation the RTP cannot determine the correct data value If the RAM is protected by ECC only 64 bit write accesses can be traced Every 64 bit word in the RAM is protected by a corresponding...

Page 1712: ...e generated for each new packet RTPENA This signal is an input and can be used by external hardware to stop the data transmission between packets When the RTPENA signal goes high the RTP will finish t...

Page 1713: ...unctionality when they are configured as output pins This is done by writing a 1 into the corresponding bit of the RTPPC6 register When the open drain functionality is enabled a zero written to the da...

Page 1714: ...28 bit boundary See Table 31 8 for a listing of the FIFOs and their corresponding addresses User and privilege mode read 0 The FIFO RAM is not accessible in the memory map 1 The FIFO RAM is mapped to...

Page 1715: ...e and the registers to their reset value This reset ensures that no data left in the FIFOs is shifted out after switching on the module with the ON OFF bit User and privilege mode read 0 The RTP modul...

Page 1716: ...ON Off switch User and privilege mode read Ah Tracing of data is enabled All Others Tracing of data is disabled Privilege mode write Ah Enable Tracing of data If there is any previous captured data re...

Page 1717: ...ilege mode read 0 Tracing is disabled 1 Tracing is enabled Privilege mode write 0 Disable tracing If RTPGLBCTRL ON OFF Ah data already captured in FIFO4 will still be transmitted Section 31 4 1 1 Enab...

Page 1718: ...data left in the serializer 0 Serializer holds data that is shifted out 1 Serializer is empty 11 EMPTYPER Peripheral FIFO empty This bit determines if there are entries left in the FIFO 0 FIFO4 contai...

Page 1719: ...the FIFO is emptied again The bit will stay set until the CPU clears it User and privilege mode read 0 No overflow occurred 1 An overflow occurred Privilege mode write 0 Writing a zero to this bit has...

Page 1720: ...oming from the other master 3h Reserved 28 RW Read Write This bit indicates if read or write operations are traced in Trace Mode or Direct Data Mode read operation If configured for write in Direct Da...

Page 1721: ...oming from the other master 3h Reserved 28 RW Read Write This bit indicates if read or write operations are traced in Trace Mode or Direct Data Mode read operation If configured for write in Direct Da...

Page 1722: ...ege mode write 0 Read or write operations are traced when coming from the CPU and the other master 1h Read or write operations are traced only when coming from the CPU 2h Read or write operations are...

Page 1723: ...2Ch 31 16 DATA R W 0 15 0 DATA R W 0 LEGEND R W Read Write R Read only n value after reset Table 31 15 RTP Direct Data Mode Write Register RTPDDMW Field Descriptions Bit Field Value Description 31 0 D...

Page 1724: ...tes have no effect 18 ENAFUNC Functional mode of RTPENA pin User and privilege mode read 0 Pin is used in GIO mode 1 Pin is used in functional mode User and privilege mode write 0 Configure pin to GIO...

Page 1725: ...d as output User and privilege mode write 0 Configure pin to input mode 1 Configure pin to output mode 17 CLKDIR Direction of RTPCLK pin This bit defines whether the pin is used as input or output in...

Page 1726: ...fect User and privilege mode read 0 The pin is at logic low 0 input voltage is V IL or lower 1 The pin is at logic high 1 input voltage is V IH or higher 17 CLKIN RTPCLK input This bit reflects the st...

Page 1727: ...tage is V OL or lower 1 Set pin to logic high 1 output voltage is V OH or higher 17 CLKOUT RTPCLK output This pin sets the output state of the RTPCLK pin User and privilege mode read 0 The pin is conf...

Page 1728: ...ut voltage is V OH or higher 17 CLKSET Sets the output state of RTPCLK pin to logic high Value in the CLKSET bit sets the data output control register bit to 1 regardless of the current value in the C...

Page 1729: ...tput voltage is V OL or lower 17 CLKCLR Sets output state of RTPCLK pin to logic low Value in the CLKCLR bit sets the data output control register bit to 0 regardless of the current value in the CLKOU...

Page 1730: ...18 0 RTPPC1 18 1 If the pin is configured as a functional pin RTPPC0 18 1 the open drain functionality is disabled User and privilege mode read 0 Pin behaves as normal push pull pin 1 Pin operates in...

Page 1731: ...0 Open drain enable These bits enable open drain functionality on the pins if they are configured as GIO output RTPPC0 15 0 0 RTPPC1 15 0 1 If the pins are configured as functional pins RTPPC0 15 0 1...

Page 1732: ...onality is disabled User and privilege mode write 0 Enables pullup pulldown functionality 1 Disables pullup pulldown functionality 17 CLKDIS RTPCLK Pull disable This bit removes the internal pullup pu...

Page 1733: ...Pullup functionality is enabled User and privilege mode write 0 Enables pulldown functionality 1 Enables pullup functionality 17 CLKPSEL RTPCLK Pull select This bit configures pullup or pulldown funct...

Page 1734: ...18 Texas Instruments Incorporated eFuse Controller Chapter 32 SPNU503C March 2018 eFuse Controller This chapter describes the eFuse controller Topic Page 32 1 Overview 1735 32 2 Introduction 1735 32 3...

Page 1735: ...roup one channel 40 error is sent to the ESM If an error occurs during the eFuse controller self test then a group one channel 41 error and a group one channel 40 error are sent to the ESM After reset...

Page 1736: ...01C with 0x003C0000 to clear the error signals Verify that ESM group 1 channel 41 and group 3 channel 1 are set then clear them If the system cannot support a test which causes the ERROR pin to go low...

Page 1737: ...self test Class 2 error routine Y N Test bits 4 0 of eFuse Error status register Are all 5 bits zero Are the 5 bits 0x15 Class 3 error routine Run eFuse self test Did self test pass www ti com eFuse C...

Page 1738: ...egister is also used to initiate an eFuse controller ECC self test Figure 32 2 EFC Boundary Control Register EFCBOUND offset 1Ch 31 24 Reserved R 0 23 22 21 20 19 18 17 16 Reserved EFC Self Test Error...

Page 1739: ...Single Bit Error OE The single bit error output enable signal determines if the EFC Single Bit Error signal comes from the eFuse controller or from bit 20 of the boundary register 0 EFC Single Bit Err...

Page 1740: ...ete 14 EFC Selftest Error This bit indicates the pass fail status of the EFC ECC Selftest once the EFC Selftest Done bit bit 15 is set 0 EFC ECC Selftest passed 1 EFC ECC Selftest failed 13 Reserved 0...

Page 1741: ...instruction executed by the eFuse Controller 0 No error 5h An uncorrectable multibit error was detected during the power on autoload sequence 15h At least one single bit error was detected and correc...

Page 1742: ...0 LEGEND R W Read Write n value after power on reset nPORRST Table 32 7 EFC Self Test Cycles Register EFCSTSIG Field Descriptions Bit Name Description 31 0 Signature This register is used to hold the...

Page 1743: ...ECLK 119 Section 2 4 5 Added Embedded Trace Macrocell ETM R4 subsection Subsequent subsections figures and tables renumbered 120 Section 2 5 1 Updated paragraph 123 Table 2 31 Changed Description of b...

Page 1744: ...ription of DIEIDH2 bit Added last sentence 184 Section 2 5 3 Updated paragraph 185 Figure 2 73 Changed register bit name to PS 7 0 QUAD 3 0 PROTSET 188 Table 2 89 Changed register bit name to PS 7 0 Q...

Page 1745: ...2 Added Reserved bits 31 9 239 Table 4 12 Changed FAULT_ADDR bits to 8 0 239 Table 4 13 Changed Description of FAULT_TYPE bit for Value 4h 8h and 10h 240 Table 4 16 Corrected Control Register at addre...

Page 1746: ...on 5 7 30 Deleted paragraph 293 Figure 5 40 Corrected name of FSM_SECTOR register figure heading 295 Table 5 45 Corrected name of FSM_SECTOR register table heading 295 Section 5 7 35 Changed paragraph...

Page 1747: ...h to clock source 5 371 Section 10 4 6 Changed frequency in first paragraph 373 Section 10 5 Updated third paragraph Changed f HCLK to f GCLK 374 Table 10 1 Updated Frequency Limit value to f GCLK for...

Page 1748: ...e ESMIEPSR4 426 Table 12 22 Changed Description of INTENCLR bit corresponding set bit in the ESMIESR4 427 Figure 12 33 Updated Read Write value of bits to R W1CP X 0 429 Chapter 13 Real Time Interrupt...

Page 1749: ...ed last sentence to paragraph 543 Section 16 2 2 Changed second bullet 543 Section 16 2 3 Deleted last sentence in second paragraph 544 Figure 16 5 Updated figure changed Index Pointer to Offset Value...

Page 1750: ...11h 3Fh Reserved 588 Table 16 48 Updated Value column of FTCB bit Added 11h 3Fh Reserved 590 Table 16 49 Updated Value column of LFSB bit Added 11h 3Fh Reserved 590 Table 16 50 Updated Value column of...

Page 1751: ...is only applicable when the ADC module is configured to be a 10 bit ADC module 727 Table 19 10 Changed Description of FRZ_EV bit The Event Group conversion is kept frozen while the Group1 or Group2 co...

Page 1752: ...paragraph 766 Figure 19 63 Corrected register bit names 766 Table 19 44 Deleted Bit column 766 Table 19 44 Changed Value column range of the G2_CHID bit to 1h 1Fh 766 Section 19 11 40 Added first para...

Page 1753: ...1 24 Corrected bit range of the Reserved bit to 31 10 and the INTTYPE0 bit to 9 8 992 Table 21 25 Corrected bit range of the Reserved bit to 31 10 and the INTTYPE1 bit to 9 8 993 Figure 21 31 Changed...

Page 1754: ...e 23 13 Updated Description of Message Number bit Only values 1h 40h are valid Values 41h FFh are invalid 1089 Section 23 17 8 Added subsection Subsequent subsections figures and tables renumbered 108...

Page 1755: ...ponding to TG number 1191 Table 24 36 Changed Description of CLRINTENRDY and CLRINTENSUS bits for Value 1 Write The interrupt does not get generated 1191 Table 24 37 Updated bit Descriptions to clarif...

Page 1756: ...nged Baud Clock Generator bullet to VCLK 1325 Figure 26 1 Changed signals to SCITX and SCIRX 1326 Equation 53 Updated equation Changed VBUSPCLK to VCLK 1329 Equation 54 Updated equation Changed VBUSPC...

Page 1757: ...igure 30 27 Updated Read Write value of all bits to R WP 0 1699 Figure 30 27 Updated LEGEND to include WP 1699 Table 30 27 Changed Description of all bits to Privilege mode write 1699 Table 30 27 Chan...

Page 1758: ...evision History www ti com 1758 SPNU503C March 2018 Submit Documentation Feedback Copyright 2018 Texas Instruments Incorporated Revision History Table 32 4 Changed Description of Reserved bits 9 0 174...

Page 1759: ...TI Resource NO OTHER LICENSE EXPRESS OR IMPLIED BY ESTOPPEL OR OTHERWISE TO ANY OTHER TI INTELLECTUAL PROPERTY RIGHT AND NO LICENSE TO ANY TECHNOLOGY OR INTELLECTUAL PROPERTY RIGHT OF TI OR ANY THIRD...

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Summary of Contents for RM48 series

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Texas Instruments RM48 series, Technical Reference Manual

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Summary of Contents for RM48 series

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