Memory Test Algorithms on the On-chip ROM
325
SPNU503C – March 2018
Copyright © 2018, Texas Instruments Incorporated
Programmable Built-In Self-Test (PBIST) Module
NOTE:
Memory test fail information is reported in terms of RGS:RDS and not RAM GROUP. Check
for information on the RGS:RDS information applicable to each memory being
tested.
7.4
Memory Test Algorithms on the On-chip ROM
This section provides a brief description for some of the test algorithms used for memory self-test.
1.
March13N:
•
March13N is the baseline test algorithm for SRAM testing. It provides the highest overall coverage.
The other algorithms provide additional coverage of otherwise missed boundary conditions of the
SRAM operation.
•
The concept behind the general march algorithm is to indicate:
–
The bit cell can be written and read as both a 1 and a 0.
–
The bits around the bit cell do not affect the bit cell.
•
The basic operation of the march is to initialize the array to a know pattern, then march a different
pattern through the memory.
•
Type of faults detected by this algorithm:
–
Address decoder faults
–
Stuck-At faults
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Coupled faults
–
State coupling faults
–
Parametric faults
–
Write recovery faults
–
Read/write logic faults
2.
Map Column:
•
The MAP COLUMN algorithm is used to identify bit line sensitivities in the memory array. The
memory array is loaded with a row stripe pattern of all 1s in the first row followed by all 0s in the
second row and repeated throughout the array. Then the values are read down each column on
consecutive cycles. The pattern in memory is inverted and run the column reads again.
•
This particular pattern is looking for the following SRAM failure mechanisms:
–
Leakage due to a low resist path in a bit
–
An Open in the bit cell
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Leakage on a BIT or BITN line
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Miss-balance in the sense amp
–
Leakage in the sense
–
High resist in the sense amp
–
Failure of the pre-charge circuits after read operations
3.
Pre-Charge:
•
The Pre-Charge algorithm exercises the pre-charge capability within the SRAM array. It is
important to specifically target this issue as it is the only part of the analog portion of the SRAM
that is frequency sensitive.
•
Similar to the MAP COLUMN algorithm, this algorithm works its way down the columns of the
SRAM. However, unlike the MAP COLUMN, this algorithm sandwiches a write between two reads
to force the worst-case conditions for the pre-charge circuits in the array.
•
This test will fail when an increase in system frequency nears the minimum access time of the
array, at this boundary:
–
High voltage should operate better than low voltage.
–
Likewise, low temperature should operate better than high temperature.
