Control Registers
292
SPNU503C – March 2018
Copyright © 2018, Texas Instruments Incorporated
F021 Flash Module Controller (FMC)
5.7.29 Uncorrected Raw ECC Register (FRAW_ECC)
Figure 5-36. Uncorrected Raw ECC Register (FRAW_ECC) [offset = 78h]
31
16
Reserved
R-0
15
9
8
7
0
Reserved
PIPE BUF
RAW_ECC[7:0]
R-0
RC-0
R/WD-u
LEGEND: R/W = Read/Write; R = Read only; WP = Write in Privilege mode; C = Clear by writing a 1; -
n
= value after reset -u = unchanged
value on internal reset, cleared on power up
Table 5-41. Uncorrected Raw ECC Register (FRAW_ECC) Field Descriptions
Bit
Field
Value
Description
31-9
Reserved
0
Reserved
8
PIPE BUF
Error came from pipeline buffer hit
When this bit is a 1, latest error came from a pipeline buffer hit and the FRAW_DATH,
FRAW_DATL, and RAW_ECC fields will not contain information that matches the error address nor
error status bits. This bit is cleared when the RAW_ECC field is updated with new valid information
or by writing a 1 to this bit.
7-0
RAW_ECC[7:0]
Uncorrected Raw ECC
This register contains the ECC data used in diagnostic testing of the ECC logic.
NOTE:
Raw Data and Raw ECC registers can loaded with diagnostic
values only in a used diagnostic mode with
DIAG_EN_KEY=0101. This mode must be set for at least one
clock cycle before writing to any FRAW* register.
