syndromeX
Raw ECC
register
FRAW_ECC
Raw Data
register
FRAW_DATAx
bank_dout
ECCx
correction
Malfunction Logic
ECCx
MAL
ERR
GOOD
MAL
COMx
Diag_En_Key
Diag_Mode=4
= 0?
diag_mode=4
1
0
0
1
1
0
A=B
A ¹ not B
0
1
diag_mode
=(3 or 4)
64
Diag_ECC_Sel
64
64
Diag_trig
compare
A
B
64
SECDED
corrected
Not Multi bit error
Zero means no correction
Diag_Mode=0
(Diag_En_Key and
Diag_Trig)
(Diag_Mode=3 or 4) and
Diag En key
¹
0101
D
Enter_Diag4
Zero when not
in diag mode 4
Q
Set when mode
4 is entered.
Clears on
errors. (bad)
Emulation and SIL3 Diagnostic Modes
259
SPNU503C – March 2018
Copyright © 2018, Texas Instruments Incorporated
F021 Flash Module Controller (FMC)
5.6.2.3
ECC Malfunction Test Mode 1: DIAG_MODE = 3
There are three inputs to the malfunction detection logic: the resulting syndrome, the original uncorrected
data, and the final corrected data. See
.
In normal function, the malfunction detection logic will detect an error if the syndrome is 0 and if the data
before the correction and the data after the correction is not equal; or if the syndrome is not 0 and if the
data before the correction and data after the correction is equal to each other. During diagnostic mode 3
or 4, user supplied values are sent to the malfunction logic. No functional checking is done by the
ecc_malfunction logic while the mode is 3 or 4.
Diagnostic mode 3 is also known as “same data” mode. A diagnostic value can be stored in the ECC
checkbit register. The value stored in the 64-bit Raw data register will be supplied to the two inputs of the
malfunction comparator logic. If a non-zero value is stored in the Raw ECC checkbit register
(FRAW_ECC), then the malfunction logic should detect it as an error and set the ECC_B2_MAL_ERR bit
(ECC malfunction error). There is one ECC_B2_MAL_ERR bit for each SECDED block and they are
called ECC1_MAL_ERR and ECC0_MAL_ERR and are selectable with the DIAG_ECC_SEL bit. The
DIAG_TRIG is set to initiate this mode.
The FRAW_DATAx, FRAW_ECC, and FUNC_ERR_ADD will load on an ECC_MAL ERR but will not
contain useful information during Diag mode 3.
5.6.2.4
ECC Malfunction Test Mode 2: DIAG_MODE = 4
Diagnostic mode 4 is also known as “inverted data” mode. A diagnostic value can be stored in the ECC
checkbit register. A value stored in the 64-bit Raw data register and its bit-wise inverted counterpart will be
supplied to the two inputs of the malfunction comparator logic. If a zero value is stored in the Raw ECC
checkbit register (FRAW_ECC), then the malfunction logic should detect it as an error and set the
ECC_B2_MAL_ERR bit (diagnostic ECC malfunction). See
In this mode only, the EE_CMG bit (Compare Malfunction Good) is cleared if any one of the 64 XOR
gates is malfunctioning. There is one EE_CMG bit for each SECDED block and they are called
COM1_MAL_GOOD and COM0_MAL_GOOD. The EE_CMG bits go high when entering diagnostic mode
4 and go low and stay low if an error is detected. These bits are only valid in diagnostic mode 4 and
outside of this mode the bits are 0.
Set the DIAG_ECC_SEL bits before entering mode 4 or enter mode 4 from a non-mode 4 and set the
DIAG_ECC_SEL bits at the same time. Do not just change the DIAG_ECC_SEL bits or the corresponding
MAL_GOOD will not get set because it did not enter mode 4 correctly.
The FRAW_DATAx, FRAW_ECC, and FUNC_ERR_ADD will load on an ECC_MAL ERR but will not
contain useful information during Diag mode 4.
Figure 5-7. ECC Malfunction Test Logic
