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3.8
Reset Operations
U9
To RST of U7
From DIT
VDD
SW4
N.O.
U8
Hardware Description and Configuration
Table 8. Digital Interface Transmitter Configuration
DIT
DIGITAL INTERFACE TRANSMITTER
LO
Enabled
HI
Disabled
The audio data format for the transmitters is hardwired for 24-bit Left Justified data format. Only one
channel (Channel A of the AES3 stream) will carry 24-bit linear PCM audio data.
Like the PCM4201, the DIT4096 transmitters must be configured for the proper Master (or System) clock
frequency. The transmitter master clock is driven by the same source as the PCM4201 system clock, as
described in Section 3.3 of this document. The transmitter master clock rate selection must match the
system clock rate selection for the PCM4201.
summarizes the master clock rate options for the
DIT4096 transmitter using the DITCLK element of switch SW1.
Table 9. Transmitter Master Clock Configuration
DITCLK
TRANSMITTER MASTER CLOCK RATE
LO
256f
S
HI
512f
S
The PCM4201EVM includes two reset switches, SW2 and SW3. Both are momentary contact, normally
open pushbutton switches. Switch SW2 provides the manual reset for the PCM4201, while switch SW3
provides the manual reset the DIT4096 digital interface transmitter.
The PCM4201 may be reset at any time by momentarily pressing and then releasing switch SW2. This
generates a reset pulse and initiates a reset sequence for the device.
For the transmitter reset function, the output of the reset circuit is connected to the RST pin of the
DIT4096 transmitter. The DIT4096 may be reset only when the DIT switch of SW1 is set LO by
momentarily pressing and then releasing switch SW3. If the DIT switch is set HI, the output of the AND
gate in the reset circuit is forced low, which will force the transmitter into power down mode. The
transmitter reset circuit is shown in
Figure 3. Transmitter Reset Circuitry
PCM4201EVM User's Guide
SBAU108A – January 2005 – Revised February 2005
9
