SPI Register (PCM2705/7)
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SLES081F – JUNE 2003 – REVISED JANUARY 2009
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
0
0
0
0
ST
0
ADDR
0
D0
D1
D2
D3
D4
D5
D6
D7
D[7:0]
Function of the lower 8 bits depends on the value of the ST (B11) bit.
ST = 0 (HID status write)
D7
Reports MUTE HID status to the host (active high)
D6
Reports volume-up HID status to the host (active high)
D5
Reports volume-down HID status to the host (active high)
D4
Reports next-track HID status to the host (active high)
D3
Reports previous-track HID status to the host (active high)
D2
Reports stop HID status to the host (active high)
D1
Reports play/pause HID status to the host (active high)
D0
Reports extended command status to the host (active high)
ST = 1 (ROM data write)
D[7:0] Internal descriptor ROM data, D0:LSB, D7:MSB
The content of power attribute and max power must be consistent with the actual application circuit
configuration (PSEL setting and actual power usage from VBUS of USB connector); otherwise, it may cause
improper or unexpected PCM2705/7 operation.
ADDR
Starts write operation for internal descriptor reprogramming (active high)
This bit resets descriptor ROM address counter and indicates following words should be ROM data (described
in the
External ROM Example
section). 456 bits of ROM data must be continuously followed after this bit has
been asserted. The data bits must be sent from LSB (D0) to MSB (D7).
To set ADDR high, ST must be set low. Note that the lower 8 bits are still active as an HID status write when
ST is set low.
ST
Determines the function of the lower 8-bit data as follows
:
0: HID status write
1: Descriptor ROM data write
Table 6. Functionality of ST and ADDR Bit Combinations
ST
ADDR
FUNCTION
0
0
HID status write
0
1
HID status write and descriptor ROM address reset
1
0
Descriptor ROM data write
1
1
Reserved
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PCM2704 PCM2705 PCM2706 PCM2707