Clock Generation and Reset Control Registers
15-74
Table 15–26. ULPD Registers – MPU Base Address: FFFE:0800 (Continued)
Name
Reset
Value
Offset
Size
R/W
Descriptions
LOCK_TIME_REGISTER
Defines lock time when APLL
is selected
R/W
16 bits
0x48
0x960
APLL_CTRL_REG
This register allows switch
between APLL and DPLL
and controls all input of
APLL.
R/W
16 bits
0x4C
U
POWER_CTRL_REG
Power control register
R/W
16 bits
0x50
0x8
The counter 32 LSB register (COUNTER_32_LSB_REG) represents the
lower value of the number of ticks from the 32-kHz clock during gauging time.
Table 15–27. Counter 32 LSB Register (COUNTER_32_LSB_REG)
Bit
Name
Type
Reset
Value
15–0
COUNTER_32_LSB
R
0x0001
The counter 32 MSB register (COUNTER_32_MSB_REG) represents the
upper value of the number of ticks from the 32-kHz clock during gauging time.
Table 15–28. Counter 32 MSB Register (COUNTER_32_MSB_REG)
Bit
Name
Type
Reset
Value
15–0
COUNTER_32_LSB
R
0x0000
The counter high frequency LSB register (COUNTER_HIGH_FREQ_LSB_REG)
represents the lower value of the number of ticks of the high-frequency clock
during gauging time.
Table 15–29. Counter High Frequency LSB Register (COUNTER_HIGH_FREQ_LSB_REG)
Bit
Name
Type
Reset
Value
15–0
COUNTER_HIGH_FREQ_LSB
R
0x0001
