Texas Instruments OMAP36 Series, Technical Reference Manual, Page: 950 / 3738

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IVA2.2 Subsystem Register Manual
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Bits Field Name Description Type Reset
0x4: FIFO width is 128-bit
0x5: FIFO width is 256-bit
7:4 Reserved Write 0s for future compatibility. RW 0x-
Read returns 0.
3 STATIC Static Entry: RW -
0: Entry is updated as normal
1: Entry is static, Count and Address updates are not updated after
TRP is submitted. Linking is not performed.
2 SYNCDIM Transfer Synchronization Dimension: RW -
0: A-Sync, Each event triggers the transfer of ACNT elements.
1: AB-Sync, Each event triggers the transfer of BCNT arrays of
ACNT elements
1 DAM Destination Address Mode: RW -
Destination Address Mode within an array. Pass-thru to TC.
0: INCR, Dst addressing within an array increments. Dst is not a
FIFO.
1: FIFO, Dst addressing within an array wraps around upon reaching
FIFO width.
0 SAM Source Address Mode: RW -
Source Address Mode within an array. Pass-thru to TC.
0: INCR, Src addressing within an array increments. Source is not a
FIFO.
1: FIFO, Src addressing within an array wraps around upon reaching
FIFO width.
Table 5-387. Register Call Summary for Register TPCC_OPTm
IVA2.2 Subsystem Functional Description
• EDMA : [0]
IVA2.2 Subsystem Register Manual
• TPCC Register Mapping Summary : [1]
Table 5-388. TPCC_SRCm
Address Offset (0x20*m)
Physical address 0x01C0 4004 + (0x20*m)4 Instance IVA2.2 TPCC
Description Source Address
Type RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SRC
Bits Field Name Description Type Reset
31:0 SRC Source Address: The 32-bit source address parameters specify the RW 0x--------
starting byte address of the source. If SAM is set to FIFO mode then
the user should program the Source address to be aligned to the
value specified by the OPT.FWID field. No errors are recognized
here but TC will assert error if this is not true.
Table 5-389. Register Call Summary for Register TPCC_SRCm
IVA2.2 Subsystem Register Manual
• TPCC Register Mapping Summary : [0]
950 IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010
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