Texas Instruments OMAP36 Series, Technical Reference Manual

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IVA2.2 Subsystem Register Manual
Bits Field Name Description Type Reset
0 E32 DMA Region Access enable for Region i, bit #32 RW 0
Table 5-237. Register Call Summary for Register TPCC_DRAEHj
IVA2.2 Subsystem Register Manual
• TPCC Register Mapping Summary : [0]
Table 5-238. TPCC_QRAEj
Address Offset (0x4*j)
Physical address 0x01C0 0380 + (0x4*j) Instance IVA2.2 TPCC
Description QDMA Region Access enable for bit N in Region i:
En = 0: Accesses through Region i address space to Bit N in any QDMA Channel Register are not allowed. Reads
will return b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute
to the generation of the TPCC region i interrupt.
En = 1: Accesses through Region i address space to Bit N in any QDMA Channel Register are allowed. Reads will
return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to
the generation of the TPCC region i interrupt.
Type RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
E7 E6 E5 E4 E3 E2 E1 E0
Bits Field Name Description Type Reset
31:8 Reserved Write 0s for future compatibility. RW 0x000000
Read returns 0.
7 E7 QDMA Region Access enable for Region i, bit #7 RW 0
6 E6 QDMA Region Access enable for Region i, bit #6 RW 0
5 E5 QDMA Region Access enable for Region i, bit #5 RW 0
4 E4 QDMA Region Access enable for Region i, bit #4 RW 0
3 E3 QDMA Region Access enable for Region i, bit #3 RW 0
2 E2 QDMA Region Access enable for Region i, bit #2 RW 0
1 E1 QDMA Region Access enable for Region i, bit #1 RW 0
0 E0 QDMA Region Access enable for Region i, bit #0 RW 0
Table 5-239. Register Call Summary for Register TPCC_QRAEj
IVA2.2 Subsystem Register Manual
• TPCC Register Mapping Summary : [0]
Table 5-240. TPCC_Q0Ek
Address Offset (0x4*k)
Physical address 0x01C0 0400 + (0x4*k) Instance IVA2.2 TPCC
Description Event Queue Entry Diagram for Queue j - Entry i (j =0 to1 and i=0 to 15)
Type R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved ENUM
ETYPE
883 SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem
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