Texas Instruments OMAP36 Series, Technical Reference Manual

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IVA2.2 Subsystem Register Manual
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Table 5-235. Register Call Summary for Register TPCC_DRAEj
IVA2.2 Subsystem Register Manual
• TPCC Register Mapping Summary : [0]
Table 5-236. TPCC_DRAEHj
Address Offset (0x8*j)
Physical address 0x01C0 0344 + (0x8*j) Instance IVA2.2 TPCC
Description DMA Region Access enable for bit N in Region M:
En = 0: Accesses through Region i address space to Bit N in any DMA Channel Register are not allowed. Reads
will return b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute
to the generation of the TPCC region i interrupt.
En = 1: Accesses through Region i address space to Bit N in any DMA Channel Register are allowed. Reads will
return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to
the generation of the TPCC region i interrupt.
Type RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
E63 E62 E61 E60 E59 E58 E57 E56 E55 E54 E53 E52 E51 E50 E49 E48 E47 E46 E45 E44 E43 E42 E41 E40 E39 E38 E37 E36 E35 E34 E33 E32
Bits Field Name Description Type Reset
31 E63 DMA Region Access enable for Region i, bit #63 RW 0
30 E62 DMA Region Access enable for Region i, bit #62 RW 0
29 E61 DMA Region Access enable for Region i, bit #61 RW 0
28 E60 DMA Region Access enable for Region i, bit #60 RW 0
27 E59 DMA Region Access enable for Region i, bit #59 RW 0
26 E58 DMA Region Access enable for Region i, bit #58 RW 0
25 E57 DMA Region Access enable for Region i, bit #57 RW 0
24 E56 DMA Region Access enable for Region i, bit #56 RW 0
23 E55 DMA Region Access enable for Region i, bit #55 RW 0
22 E54 DMA Region Access enable for Region i, bit #54 RW 0
21 E53 DMA Region Access enable for Region i, bit #53 RW 0
20 E52 DMA Region Access enable for Region i, bit #52 RW 0
19 E51 DMA Region Access enable for Region i, bit #51 RW 0
18 E50 DMA Region Access enable for Region i, bit #50 RW 0
17 E49 DMA Region Access enable for Region i, bit #49 RW 0
16 E48 DMA Region Access enable for Region i, bit #48 RW 0
15 E47 DMA Region Access enable for Region i, bit #47 RW 0
14 E46 DMA Region Access enable for Region i, bit #46 RW 0
13 E45 DMA Region Access enable for Region i, bit #45 RW 0
12 E44 DMA Region Access enable for Region i, bit #44 RW 0
11 E43 DMA Region Access enable for Region i, bit #43 RW 0
10 E42 DMA Region Access enable for Region i, bit #42 RW 0
9 E41 DMA Region Access enable for Region i, bit #41 RW 0
8 E40 DMA Region Access enable for Region i, bit #40 RW 0
7 E39 DMA Region Access enable for Region i, bit #39 RW 0
6 E38 DMA Region Access enable for Region i, bit #38 RW 0
5 E37 DMA Region Access enable for Region i, bit #37 RW 0
4 E36 DMA Region Access enable for Region i, bit #36 RW 0
3 E35 DMA Region Access enable for Region i, bit #35 RW 0
2 E34 DMA Region Access enable for Region i, bit #34 RW 0
1 E33 DMA Region Access enable for Region i, bit #33 RW 0
882 IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010
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