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PRCM Basic Programming Model
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: DPLL2 autoidle mode control
3.6.2.3.6 CM_AUTOIDLE_PLL (DPLL Autoidle Register)
The DPLL autoidle register allows the enabling/disabling of the automatic mode-switching control for
DPLL3 and DPLL4. This automatic mode takes effect only when the DPLLs are locked.
DPLL3 can be configured to automatically switch to either low-power bypass mode or low-power stop
mode when the CORE power domain clock is not required.
DPLL4 can be configured to automatically switch to low-power stop mode when the PER power domain
clock is not required.
3.6.2.3.7 CM_AUTOIDLE1_PLL (DPLL5 Autoidle Register)
The DPLL5 autoidle register allows the enabling/disabling of the automatic mode-switching control. This
automatic mode takes effect only when the DPLL is locked.
When enabled, DPLL5 is automatically switched to low-power stop mode whenever the 120-MHz output
clock is gated.
3.6.2.3.8 CM_IDLEST_CKGEN (Source-Clock Idle-Status Register)
The source-clock idle-status register provides a status of DPLL3 and DPLL4 clock activity. It also provides
the status of the functional clocks derived from DPLL4 output.
The activity status for DPLL3 and DPLL4 can be:
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DPLL is bypassed.
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DPLL is locked.
The activity status for the functional clocks can be:
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The functional 96-MHz clock is active, or not.
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The functional 48-MHz clock is active, or not.
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The functional 12-MHz clock is active, or not.
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The functional 54-MHz clock is active, or not.
The functional 96-MHz clock and all other functional clocks derived from it are active only when DPLL4 is
locked and the clock is required.
The functional 48-MHz and 12-MHz clocks are qualified as active only if the clock is required and when
the external alternate clock is selected as the source clock.
The functional 54-MHz clock (DSS_TV_CLK) is active only when DPLL4 is locked, selected as the source
clock, and required.
3.6.2.3.9 CM_IDLEST2_CKGEN (DPLL5 Source-Clock Idle-Status Register)
The source-clock idle-status register provides the status of DPLL5 clock activity. It also provides the status
of the functional clocks derived from DPLL5 output.
The activity status for DPLL5 can be:
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DPLL is bypassed.
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DPLL is locked.
The activity status for the functional clocks can be:
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The 120-MHz functional clock is active, or not.
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The output stage of the 120-MHz functional clock is active, or not.
3.6.2.3.10 CM_IDLEST_PLL_ <processor_name> (Processor DPLL Idle-Status Register)
The processor DPLL idle-status register indicates the status of the processor DPLL: whether it is in locked
or bypass mode.
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SWPU177N – December 2009 – Revised November 2010
Power, Reset, and Clock Management
Copyright © 2009–2010, Texas Instruments Incorporated
