Interrupt
generator
Sensor
core
Sensor value
sample
VDDx
Min/Max/Avg
Clock
generator
Error
generator
SR_ALWON_FCLK
SR_CLK
VDDx error
VP interrupt
SRx_IRQ
Interrupt clear
PRCM
Power IC
V
o
lt
a
g
e
p
ro
c
e
s
s
o
r
MPU
INTC
Device
SmartReflex module
8
Accumulator
Multiple samples of
sensor values
Error signal
Reference value
prcm-UC-003
value
Accumulator
Min/max
/average
value
Public Version
PRCM Functional Description
www.ti.com
Figure 3-83. SmartReflex Module Functional Overview
3.5.6.5.4.3 SmartReflex Submodules
The SmartReflex module is enabled by setting the SRn
(1)
The SRn
[11] SR_EN bit is composed
of six blocks:
•
Clock generator
•
Sensor core
•
Accumulator
•
Minimum/maximum/average
•
Error generator
•
Interrupt generator
Clock Generator
The clock generator provides the internal SR_CLK sampling clock to the sensor core of the module. The
SRn.
[21:12] SRCLKLENGTH bit field allows the setting of the frequency divider ratio between
the SR_ALWON_FCLK and the SR_CLK. It is calculated using
:
SRn.SRCONFIG[21:12] SRCLKLENGTH = f
SR_ALWON_FCLK
/(2* f
SR_CLK
)
(1)
Where f
SR_ALWON_FCLK
is the frequency of the SR_ALWON_FCLK and f
SR_CLK
is the desired SR_CLK
frequency.
To accurately use the target values programmed for SmartReflex modules in the device, the
SRCLKLENGTH parameter must be set correctly. The target values for the SmartReflex modules are
calculated with the SR_CLK frequency set at 100 kHz. It is thus mandatory that the value of the
SRCLKLENGTH parameter is calculated from Equation 4-1 with f
SR_CLK
set at 100 kHz.
For example, if the system clock has a frequency of 38.4 MHz, and the target SR_CLK frequency is 100
kHz, the SRn.
[21:12] SRCLKLENGTH is 192 (0x0C0).
Sensor Core
(1)
SR1 and SR2 instances of the SmartReflex module in the device; n varies from 1 to 2.
382
Power, Reset, and Clock Management
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated
