Texas Instruments OMAP36 Series, Technical Reference Manual

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Emulation Pin Manager
Table 27-100. EPM Multiplexing
Debug Interface ETM 16 ETM 8 IVA SDTI 4 Data SDTI 4 Data SDTI 2 Data SDTI 1 Data
Control Signals HS-RTDX/Triggers
2-Pin Mode
Function Dir Function Dir Function Dir Function Dir Function Dir Function Dir Function Dir
DBGP19 etk_d15 etk_d15 O – emu3 IO sdti_txd3 O sdti_txd3 O – –
DBGP18 etk_d14 etk_d14 O – emu2 IO sdti_txd2
(1)
O sdti_txd2
(1)
O sdti_clk
(1)
O –
DBGP17 etk_d13 etk_d13 O – – sdti_txd1 O sdti_txd1 O – –
DBGP16 etk_d12 etk_d12 O – – sdti_txd0 O – – –
DBGP15 etk_d11 etk_d11 O – – sdti_clk O – – –
DBGP12 etk_d10 etk_d10 O – – uart1_rx
(2)
I – – –
etk_d9 etk_d9 O – – – – – –
etk_d8 etk_d8 O – – – – – –
DBGP2 etk_d7 etk_d7 O etk_d7 O – – – – –
etk_d6 etk_d6 O etk_d6 O – – – – –
etk_d5 etk_d5 O etk_d5 O – – – – –
etk_d4 etk_d4 O etk_d4 O – – – – –
etk_d3 etk_d3 O etk_d3 O – – – – –
etk_d2 etk_d2 O etk_d2 O – – – – –
etk_d1 etk_d1 O etk_d1 O – – – – –
etk_d0 etk_d0 O etk_d0 O – – – – –
etk_ctl etk_ctl O etk_ctl O – – – – –
etk_clk etk_clk O etk_clk O – – – – –
DBGP1 jtag_emu1 – emu1 IO O sdti_txd0
(3)
O sdti_txd1
(3)
O sdti_txd0 O
(3)
DBGP0 jtag_emu0 – emu0 IO O sdti_clk
(1)
O sdti_txd0
(1)
O sdti_clk O
(1)
(1)
Two SDTI pins can be mapped to the same etk_#; SDTI_CLK selects the sdti_clk pin, and SDTI_DATA selects the sdti_txd# data pin.
(2)
To map the uart1_rx pin, configuration must be done on the application pin manager (that is,SCM)
(3)
Two SDTI data share the same etk_#; sdti_txd0 is mapped on jtag_emu1 if sdti_clk is mapped on jtag_emu0; and sdti_txd1 is mapped on jtag_emu1 if sdti_txd0 is mapped on jtag_emu0.
All the output pins are controlled by a 4-bit bit field that configures the current mode. Table 27-101 shows the list of modes supported and the
corresponding values to enter in the EPM control bit field in the following registers:
•
DAPC_EPM0
• DAPC_EPM1
• DAPC_EPM2
3641 SWPU177N – December 2009 – Revised November 2010 Debug and Emulation
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