Public Version
Emulation Pin Manager
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Table 27-113. DAPC_EPM0
Address Offset
0x050
Physical address
0x5401 D050
Instance
DAPC_EPM
Description
Emulation pin manager register 0.
Type
RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
RESERVED
DBGP2
DBGP1
DBGP0
Bits
Field Name
Description
Type
Reset
31:12
RESERVED
Read returns reset value.
R
0x00000
11:8
DBGP2
TRACECLK, TRACECTL and TRACEDATA[7:0] pins
RW
0x0
control
7:4
DBGP1
EMU1 pin control
RW
0x0
3:0
DBGP0
EMU0 pin control
RW
0x0
Table 27-114. Register Call Summary for Register DAPC_EPM0
EPM Functional Description
•
:
EPM Register Manual
•
Table 27-115. DAPC_EPM1
Address Offset
0x054
Physical address
0x5401 D054
Instance
DAPC_EPM
Description
Emulation pin manager register 1
Type
RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
DBGP15
RESERVED
DBGP12
RESERVED
Bits
Field Name
Description
Type
Reset
31:28
DBGP15
TRACEDATA[11] pin control
RW
0x0
27:20
RESERVED
Read returns reset value.
R
0x00
19:16
DBGP12
TRACEDATA[10:8] pin control
RW
0x0
15:0
RESERVED
Read returns reset value.
R
0x0000
Table 27-116. Register Call Summary for Register DAPC_EPM1
EPM Functional Description
•
:
EPM Register Manual
•
3646
Debug and Emulation
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated