Public Version
MMC/SD/SDIO Register Manual
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Bits
Field Name
Description
Type
Reset
19
CCCE
Command CRC check enable.
RW
0
This bit must be set to 1 to enable CRC7 check on command
response to protect the response against transmission errors on
the bus. If an error is detected, it is reported as a command CRC
error (MMCi.
[17] CCRC bit set to 1). Note: The
CCCE bit cannot be configured for an Auto CMD12, and then CRC
check is automatically checked when this command is issued.
0x0:
CRC7 check disable
0x1:
CRC7 check enable
18
Reserved
Reserved bit field. Do not write any value.
R
0
17:16
RSP_TYPE
Response type.
RW
0x0
This bits defines the response type of the command.
0x0:
No response
0x1:
Response Length 136 bits
0x2:
Response Length 48 bits
0x3:
Response Length 48 bits with busy after response
15:6
Reserved
Reserved bit field. Do not write any value.
R
0x000
5
MSBS
Multi/Single block select.
RW
0
This bit must be set to 1 for data transfer in case of multi block
command. For any others command this bit shall be set to 0.
0x0:
Single block. If this bit is 0, it is not necessary to set
the register MMCi.
[31:16] NBLK bits.
0x1:
Multi block. When Block Count is disabled
(MMCi.
[1] BCE bit is set to 0) in Multiple
block transfers (MMCi.
[5] MSBS bit is
set to 1), the module can perform infinite transfer.
4
DDIR
Data transfer Direction.
RW
0
Select This bit defines either data transfer will be a read or a write.
0x0:
Data Write (host to card)
0x1:
Data Read (card to host)
3
Reserved
Reserved bit field. Do not write any value.
R
0
2
ACEN
Auto CMD12 Enable. (SD cards only).
RW
0
When this bit is set to 1, the host controller issues a CMD12
automatically after the transfer completion of the last block. The
Host Driver shall not set this bit to issue commands that do not
require CMD12 to stop data transfer.
For CE-ATA commands (MMCi.
[12] CEATA bit set
to 1), auto CMD12 is useless; therefore when this bit is set the
mechanism to detect command completion signal, named CCS,
interrupt is activated.
0x0:
Auto CMD12 disable
0x1:
Auto CMD12 enable or CCS detection enabled.
1
BCE
Block Count Enable (Multiple block transfers only).
RW
0
This bit is used to enable the block count register
(
[31:16] NBLK bits). When Block Count is disabled
[1] BCE bit is set to 0) in Multiple block transfers
[5] MSBS bits is set to 1), the module can perform
infinite transfer.
0x0:
Block count disabled for infinite transfer.
0x1:
Block count enabled for multiple block transfer with
known number of blocks
0
DE
DMA Enable.
RW
0
This bit is used to enable DMA mode for host data access.
0x0:
DMA mode disable
0x1:
DMA mode enable
3438
MMC/SD/SDIO Card Interface
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated