Texas Instruments OMAP36 Series, Technical Reference Manual, Page: 3422 / 3738

Public Version
MMC/SD/SDIO Use Cases and Tips
www.ti.com
Table 24-30. Setting Number of Blocks
Register Name Register Address Value Value Description
MMCHS1. MMCHS_CON 0x4809C02C 0x00000000 MMC bus is in push-pull mode.
MMCHS1. MMCHS_HCTL 0x4809C128 0x00000002 MMCHS controller's data bus width is set to 4.
MMCHS1. MMCHS_IE 0x4809C134 0x100f0001 Enables CERR, CIE, CCRC, CC, CTO and CEB
events to occur.
MMCHS1. MMCHS_ISE 0x4809C138 0x100f0001 Enables CERR, CIE, CCRC, CC, CTO and CEB
interrupts to rise.
MMCHS1. MMCHS_CMD 0x4809C10C 0x171a0000 Sends CMD23 whose opcode is 23, response type is
48 bits, with CICE and CCCE enabled.
MMCHS1. MMCHS_ARG 0x4809C108 0x00000008 Number of 512-byte blocks in 4 KB buffer is 8.
24.6.1.3.5.3 Send CMD25
Issuing CMD25 starts the finite, multiple block write transfer. Before the transfer starts, DMA controller
should be configured for this operation. For more details about DMA configuration see
Chapter 11 , SDMA.
Table 24-31. CMD25 Issuing
Register Name Register Address Value Value Description
MMCHS1. MMCHS_CON 0x4809C02C 0x00000000 MMC bus is in push-pull mode.
MMCHS1. MMCHS_HCTL 0x4809C128 0x00000002 MMCHS controller's data bus width is set to 4.
MMCHS1. MMCHS_IE 0x4809C134 0x107f0013 Enables CERR, CIE, CCRC, CC, TC, BWR, CTO, DTO,
DCRC, DEB and CEB events to occur.
MMCHS1. MMCHS_ISE 0x4809C138 0x107f0013 Enables CERR, CIE, CCRC, CC, TC, BWR, CTO, DTO,
DCRC, DEB and CEB interrupts to rise.
MMCHS1. MMCHS_CMD 0x4809C10C 0x193a0023 Sends CMD25 whose opcode is 25, response type is 48
bits, with CICE, DP, MSBS, BCE, DE and CCCE
enabled.
MMCHS1. MMCHS_ARG 0x4809C108 0x00000000 Not used
MMCHS1. MMCHS_BLK 0x4809C104 0x00080200 (number_blocks << 16) | (block_length)
24.6.1.3.6 MMC Read Transfer
Either data read or data write transfer uses DMA controller to perform memory (DDRAM) to/from MMCHS
controller transfers. The DMA part is not described in this document, it is described in
Chapter 11 , SDMA.
Before any data transfer begins, the card must selected by issuing CMD7 command ( Table 24-24 ).
A read transfer is a finite multiple block write transfer. To perform a read transfer, the following steps must
performed.
24.6.1.3.6.1 Send CMD16
Issuing CMD16 allows to set the block length. For our use case we decided to use a static block length of
512 bytes. The block length value is passed to the MMC card via MMCHS1.
MMCHS_ARG register. See
Table 24-29 .
24.6.1.3.6.2 Send CMD23
Issuing CMD23 allows to set the number of how many 512-byte blocks the MMC card should expect from
the MMCHS controller. The number of blocks is passed to MMC card via MMCHS1.
MMCHS_ARG
register. See Table 24-30 .
24.6.1.3.6.3 Send CMD18
Issuing CMD18 starts the finite, multiple block read transfer. Before the transfer starts, DMA controller
should be configured for this operation. For more details about DMA configuration see
Chapter 11 , SDMA.
3422 MMC/SD/SDIO Card Interface SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated