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MMC/SD/SDIO Use Cases and Tips
Table 24-27. Enabling High-Speed With CMD6
Register Name
Register Address
Value
Value Description
MMCHS1.
0x4809C02C
0x00000000
MMC bus is in push-pull mode.
MMCHS1.
0x4809C128
0x00000002
MMCHS controller's data bus width is set to 4.
MMCHS1.
0x4809C134
0x100f0001
Enables CERR, CIE, CCRC, CC, CTO and CEB
events to occur.
MMCHS1.
0x4809C138
0x100f0001
Enables CERR, CIE, CCRC, CC, CTO and CEB
interrupts to rise.
MMCHS1.
0x4809C10C
0x061b0000
Sends CMD6 whose opcode is 6, response type is 48
bits with busy, with CICE and CCCE enabled.
MMCHS1.
0x4809C108
0x03b90100
(3 << 24) | (byte_address << 16) | (byte_value << 8).
byte_address is the byte address in ext_csd register.
After issuing CMD6 completes successfully and MMC card leaves busy state, MMCHS controller should
now change its output clock to bring it to 48 MHz. 52 MHz, max frequency value supported by MMC card
version 4 and above, is not supported because 96 MHz, MMCHS controller functional clock, is not a
multiple of 52 MHz. We fall off to 48 MHz.
Table 24-28. MMCHS_SYSCTL Value
Register Name
Register Address
Value
Value Description
MMCHS1.
0x4809C12C
0x00000087
MMCHS controller's internal clock is stable and
enabled, MMC card's clock is on. Divider value is 2
which means that MMCHS controller is supplying a 48
MHz clock.
24.6.1.3.5 MMC Write Transfer
Either data read or data write transfer uses DMA controller to perform memory (DDRAM) to/from MMCHS
controller transfers. The DMA part is not described in this chapter, it is described in
, SDMA.
Before any data transfer begins, the card must selected by issuing CMD7 command (
A write transfer is a finite multiple block write transfer. To perform a write transfer, the following steps must
performed.
24.6.1.3.5.1 Send CMD16
Issuing CMD16 allows to set the block length. For our use case we decided to use a static block length of
512 bytes. The block length value is passed to the MMC card via MMCHS1.
register. The
registers impacted by this operation are as follows:
Table 24-29. Setting Block Length
Register Name
Register Address
Value
Value Description
MMCHS1.
0x4809C02C
0x00000000
MMC bus is in push-pull mode.
MMCHS1.
0x4809C128
0x00000002
MMCHS controller's data bus width is set to 4.
MMCHS1.
0x4809C134
0x100f0001
Enables CERR, CIE, CCRC, CC, CTO and CEB
events to occur.
MMCHS1.
0x4809C138
0x100f0001
Enables CERR, CIE, CCRC, CC, CTO and CEB
interrupts to rise.
MMCHS1.
0x4809C10C
0x101a0000
Sends CMD16 whose opcode is 16, response type is
48 bits, with CICE and CCCE enabled.
MMCHS1.
0x4809C108
0x00000200
Block length is 512 = 0x200
24.6.1.3.5.2 Send CMD23
Issuing CMD23 allows to set the number of how many 512-byte blocks the MMC card should expect from
the MMCHS controller. The number of blocks is passed to MMC card via MMCHS1.
register. The registers impacted by this operation are as follows:
3421
SWPU177N – December 2009 – Revised November 2010
MMC/SD/SDIO Card Interface
Copyright © 2009–2010, Texas Instruments Incorporated