mmchs-061
clk
cmd
CMD1
CMD2
CMD3
RESP
RESP
RESP
dat0
S
S
S
E
E
E
010
512 bytes
+ CRC
512 bytes
+ CRC
1 sec. max
50ms max
Boot terminated
Min 8 48 clocks = 56 clocks required from
CMD signal high to next MMC command
t1
t2
t3
t4
t5
t6
mmchs-062
clk
cmd
ACMD12
dat
S
S
E
E
Data
+ CRC
CRC
status
S
E
Host ACMD12 margin
Ncrc in range 2 to 8 cycles
Public Version
www.ti.com
MMC/SD/SDIO Functional Description
Figure 24-28. Boot Acknowledge Timeout When CMD Line Tied To 0
t1 - Data timeout counter is loaded and starts after cmd line is tied to 0.
t2 - Data timeout counter stops and if it is 0,
[DCRC] is generated.
t3 - Data timeout counter is loaded and starts.
t4 - Data timeout counter stops and if it is 0,
[DCRC] is generated.
t5 - Data timeout counter is loaded and starts after Data + CRC transmission.
t6 - Data timeout counter stops and if it is 0,
[DCRC] is generated.
24.4.6 Autocommand 12 Timings
With the UHS definition of SD cards with higher frequency for MMC clock up to 208, SD standard imposes
a specific timing for Auto CMD12 'end bit' arrival.
24.4.6.1 Autocommand 12 Timings During Write Transfer
A margin named Ncrc in range of 2 to 8 cycles has been defined for SDR50 and SDR104 card
components for write data transfers, as autocommand 12 'end bit' shall arrive after the CRC status 'end
bit'.
shows auto CMD12 timings during write transfer.
Figure 24-29. Autocommand 12 Timings During Write Transfer
The Host controller has a margin of 18 clock cycles to make sure that auto CMD12 'end bit' arrives after
the CRC status. This margin does not depend on MMC bus configuration, DDR or standard transfer, 1,4
or 8 bus width.
3393
SWPU177N – December 2009 – Revised November 2010
MMC/SD/SDIO Card Interface
Copyright © 2009–2010, Texas Instruments Incorporated