Texas Instruments OMAP36 Series, Technical Reference Manual

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MMC/SD/SDIO Functional Description
In the L4 clock domain, the user can:
• Control the transfer (configure parameters for the transfer)
• Control clock activities and reset
• Manage interrupts and hardware requests
• Consult different status:
– Bus
– Buffer
– Interrupts
– Errors
• Transmit and receive data through the buffer
In the functional clock domain, the internal mechanisms perform the transfers of data and commands.
For more detail see the command response registers (MMCi.MMCHS_RSPn registers: Table 24-53 ,
Table 24-55 , Table 24-57 , and Table 24-59 ).
CAUTION
Read access to the command response registers is allowed only when the
command process is completed.
24.4.2 Mode Selection
The MMC/SD/SDIO host controller can be use in two modes: MMC and SD/SDIO modes. It has been
designed to be the most transparent with the type of card.
The type of the card connected is differentiated by the software initialization procedure. Software identifies
the type of card connected during software initialization. For each given card type, there are
corresponding commands. Some commands are not supported by all cards. See the Multimedia Card
System Specification, v4.2, the SD Memory Card Specifications, v2.0, and the SDIO Card Specification,
Part E1, v1.10, for more details.
The purpose of the module is to transfer commands and data, to whatever card is connected, respecting
the protocol of the connected card.
Writes and reads to the card must respect the appropriate protocol of that card.
24.4.3 Buffer Management
24.4.3.1 Data Buffer
The MMC/SD/SDIOi host controller uses a data buffer divided into two 512-byte portions that are 32 bits
wide by 128 words deep. This buffer transfers data from one data bus (Interconnect) to another data bus
(SD SDIO or MMC card bus) and vice versa.
The buffer is the heart of the interface and ensures the transfer between the two interfaces (L4 and the
card).
To enhance performance, the data buffer is completed by a prefetch register and a post-write buffer that
are not accessible by the host controller.
The read access time of the prefetch register is faster than the one of the data buffer. The prefetch
register allows data to be read from the data buffer at an increased speed by preloading data into the
prefetch register.
The entry point of the data buffer for the two portions, the prefetch buffer and the post-write buffer, is the
32-bit register MMCi.
MMCHS_DATA . A write access to the MMCi. MMCHS_DATA register followed by a
read access from the MMCi. MMCHS_DATA register corresponds to a write access to the post-write buffer
followed by a read access to the prefetch buffer. As a consequence, it is normal that the data of the write
access to the MMCi.
MMCHS_DATA register and the data of the read access to the MMCi. MMCHS_DATA
register are different.
3385 SWPU177N – December 2009 – Revised November 2010 MMC/SD/SDIO Card Interface
Copyright © 2009–2010, Texas Instruments Incorporated