Texas Instruments OMAP36 Series, Technical Reference Manual

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Public Version
High-Speed USB Host Subsystem
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Bits Field Name Description Type Reset
RS bit is a 1. The host controller sets this bit to 1 after it
has stopped executing as a result of the RS bit being set
to 0, either by software or by the host controller
hardware.
11:6 RESERVED Reserved R 0x00
5 IAA Interrupt on Async Advance RW 0
System software can force the host controller to issue an
interrupt the next time the host controller advances the
asynchronous schedule by writing a 1 in the
USBHOST.
USBCMD [6] IAAD bit. This status bit indicates
the assertion of that interrupt source.
4 HSE Host System Error RW 0
The host controller sets this bit to 1 when a serious error
occurs during a host system access involving the host
controller module.
3 FLR Frame List Rollover RW 0
The host controller sets this bit to 1 when the
USBHOST.
FRINDEX rolls over from its maximum value
to 0. The exact value at which the rollover occurs
depends on the frame list size.
2 PCD Port Change Detect RW 0
The host controller sets this bit to 1 when any port for
which the USBHOST.
PORTSC_i [13] PO bit is set to 0
has a change bit transition from a 0 to a 1 or a
USBHOST.
PORTSC_i [6] FPR bit transition from a 0 to a
1.
This bit is also set as a result of the
USBHOST.
PORTSC_i [1] CSC bit being set to 1 after
system software has relinquished ownership of a
connected port by writing a 1 to a
USBHOST.
PORTSC_i [13] PO bit.
1 USBEI USB Error Interrupt RW 0
The host controller sets this bit to 1 when completion of a
USB transaction results in an error condition.
0 USBI USB Interrupt RW 0
The host controller sets this bit to 1 on completion of a
USB transaction, which results in the retirement of a
transfer descriptor that had its IOC bit set.
The host controller also sets this bit to 1 when a short
packet is detected (actual number of bytes received was
less than the expected number of bytes).
Table 22-221. Register Call Summary for Register USBSTS
High-Speed USB Host Subsystem
• High-Speed USB Host Subsystem Register Summary : [0]
• High-Speed USB Host Subsystem Register Description : [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13]
Table 22-222. USBINTR
Address Offset 0x0000 0018
Physical Address 0x4806 4818 Instance EHCI
Description USB interrupt enable
Type RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED
IAAE PCIE
FLRE
HSEE
USBIE
USBEIE
3350 High-Speed USB Host Subsystem and High-Speed USB OTG Controller SWPU177N – December 2009 – Revised November 2010
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