Interrupt initialization:
− Reset status bits in SPIm.MCSPI_IRQSTATUS
− Enable interrupts in SPIm.MCSPI_IRQENABLE
Channel configuration:
Write SPIm.MCSPI_CHxCONF
Start the channel:
Set SPIm.MCSPI_CHxCTRL[0] EN bit to 1
Stop the channel:
Set SPIm.MCSPI_CHxCTRL[0] EN bit to 0
Next command
Main process
Host event for the
First transmit word:
Write SPIm.MCSPI_TXx
First write request
(TX empty or DMA write)
end of transfer
The end of transfer
depends on the
transfer mode.
In multichannel master
mode, do not overwrite
the bits of other channels
when initializing
SPIm.MCSPI_IRQSTATUS and
SPIm.MCSPI_IRQENABLE.
mcspi-030
Public Version
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McSPI Basic Programming Model
•
spi1_csx line assertion/deassertion: Automatic, manual
For these flows, the host process contains the main process and the interrupt routines. The interrupt
routines are called on the interrupt signals or by an internal call if the module is used in polling mode.
20.6.2.1 Common Transfer Procedure
shows the main sequence common to all transfers. In multichannel master mode, the flows
of different channels can be run simultaneously.
Figure 20-27. Common Transfer Sequence: Main Process
20.6.2.2 End-of-Transfer Procedure
For transfers carried out with DMA or interrupt mode, the end of transfer must be achieved by following
the steps shown in the flowcharts corresponding to
, which summarizes the end-of-transfer
types per transfer mode and provides cross-references for further information.
3013
SWPU177N – December 2009 – Revised November 2010
Multichannel SPI
Copyright © 2009–2010, Texas Instruments Incorporated
