Public Version
UART/IrDA/CIR Register Manual
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Bits
Field Name
Description
Type
Reset
0x0:
Event is not allowed to wake up the system.
0x1:
Event can wake up the system.
1
RESERVED
Read returns 1. Must be set to 1 for correct behavior.
RW
1
0
EVENT_0_CTS_ ACTIVITY
UART mode only
RW
1
0x0:
Event is not allowed to wake up the system.
0x1:
Event can wake up the system.
Table 19-118. Register Call Summary for Register WER_REG
UART/IrDA/CIR Functional Description
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UART/IrDA (SIR, MIR, FIR)/CIR Mode Selection
[6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] [20] [21] [22] [23]
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UART/IrDA/CIR Register Manual
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UART/IrDA/CIR Register Summary
Table 19-119. CFPS_REG
Address Offset
0x060
Physical Address
See
to
Description
Carrier frequency prescaler
Type
RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
RESERVED
CFPS
Bits
Field Name
Description
Type
Reset
31:8
Reserved
Read returns 0.
R
0x000000
7:0
CFPS
Because the consumer IR works at modulation rates of 30-56.8 kHz, the
RW
0x69
48-MHz clock must be prescaled before the clock can drive the IR logic. This
register sets the divisor rate to give a range to accommodate remote-control
requirements in BAUD multiples of 12x. The value of the CFPS at reset is
0105 (decimal), which equates to a 38.1-kHz output from starting conditions.
The 48-MHz carrier is prescaled by the CFPS, which is then divided by the 12x
BAUD multiple.
Example:
Target Freq (kHz)
CFPS (decimal)
Actual Freq(kHz)
30
133
30.08
32.75
122
32.79
36
111
36.04
36.7
109
36.69
38
105
38.1
40
100
40
56.8
70
57.14
CFPS = 0 is not supported.
Table 19-120. Register Call Summary for Register CFPS_REG
UART/IrDA/CIR Functional Description
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•
UART/IrDA (SIR, MIR, FIR)/CIR Mode Selection
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UART/IrDA/CIR Register Manual
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UART/IrDA/CIR Register Summary
2970UART/IrDA/CIR
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated