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General-Purpose Timers
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16.2.4 GP Timers Functional Description
Each GP timer contains a free-running upward counter with autoreload capability on overflow. The timer
counter can be read and written on-the-fly (while counting). Each GP timer includes compare logic to allow
an interrupt event on a programmable counter matching value. A dedicated output signal can be pulsed or
toggled on either an overflow or a match event. This offers time-stamp trigger signaling or PWM signal
sources. A dedicated input signal can be used to trigger an automatic timer counter capture or an interrupt
event on a programmable input signal transition type. A programmable clock divider (prescaler) allows
reduction of the timer input clock frequency. All internal timer interrupt sources are merged into one
module interrupt line and one wake-up line. Each internal interrupt source can be independently
enabled/disabled with a dedicated bit of the GPTi.
register for the interrupt features and a dedicated
bit of the GPTi.
register for the wakeup. In addition, GPTIMER1, GPTIMER2, and GPTIMER10
have implemented a mechanism to generate an accurate tick interrupt.
For each GP timer implemented in the device, there are two possible clock sources:
•
32-kHz clock
•
System clock
Selection of the input clock source is done in the registers in the PRCM configuration (see
GP Timers Overview).
Each GP timer supports three functional modes:
•
Timer mode
•
Capture mode
•
Compare mode
By default, after core reset, the capture and compare modes are disabled.
16.2.4.1 GP Timers Block Diagram
shows the block diagram of common GP timers, and
shows the block diagram of
GP timers with 1-ms tick generation module.
2712
Timers
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated