timers-004
PRCM
CM_CLKSEL_WKUP
GPT1_FCLK
L4 I/F
GPT1_EVENT_CAPTURE
GPT1_PWM_OUT
GPT1_IRQ
32 kHz
12/13/19.2/26/38.4 MHz
IVA2.2
subsystem
Modem interrupt
MPU
subsystem
L4 interconnect
gpt11_pwm_evt
gpt10_pwm_evt
gpt9_pwm_evt
4
4
11
MD_IRQ_[9:6]
M_IRQ_47
M_IRQ_46
M_IRQ_45
M_IRQ_44
M_IRQ_43
M_IRQ_42
M_IRQ_41
M_IRQ_40
M_IRQ_39
M_IRQ_38
M_IRQ_37
6
CM_CLKSEL_PER
6
IVA2_IRQ[6:9]
handler
GPT2_FCLK
L4 I/F
GPT2_EVENT_CAPTURE
GPT2_PWM_OUT
GPT2_IRQ
GPT3_FCLK
L4 I/F
GPT3_EVENT_CAPTURE
GPT3_PWM_OUT
GPT3_IRQ
GPT4_FCLK
L4 I/F
GPT4_EVENT_CAPTURE
GPT4_PWM_OUT
GPT4_IRQ
GPT5_FCLK
L4 I/F
GPT5_EVENT_CAPTURE
GPT5_PWM_OUT
GPT5_IRQ
GPT6_FCLK
L4 I/F
GPT6_EVENT_CAPTURE
GPT6_PWM_OUT
GPT6_IRQ
GPT7_FCLK
L4 I/F
GPT7_EVENT_CAPTURE
GPT7_PWM_OUT
GPT7_IRQ
GPT8_FCLK
L4 I/F
GPT8_EVENT_CAPTURE
GPT8_PWM_OUT
GPT8_IRQ
GPT9_FCLK
L4 I/F
GPT9_EVENT_CAPTURE
GPT9_PWM_OUT
GPT9_IRQ
GPT10_FCLK
L4 I/F GPT10_EVENT_CAPTURE
GPT10_PWM_OUT
GPT10_IRQ
GPT11_FCLK
L4 I/F GPT11_EVENT_CAPTURE
GPT11_PWM_OUT
GPT11_IRQ
gpt8_pwm_evt
2
CM_CLKSEL_CORE
sys_32k
Public Version
General-Purpose Timers
www.ti.com
16.2.3 GP Timers Integration
shows the GP timer integration in the device.
Figure 16-4. GP Timer Integration
16.2.3.1 Clocking, Reset, and Power-Management Scheme
16.2.3.1.1 Clock Management
There are two clock domains in the GP timers:
•
Functional clock domain: GPTi_FCLK is the GP timer functional clock. It is used to clock the GP timer
internal logic.
•
Interface clock domain: GPTi_ICLK is the GP timer interface clock. It is used to synchronize the GP
timer L4 port to the L4 interconnect. All accesses from the interconnect are synchronous to
GPTi_ICLK.
lists the source clocks for each GP timer in the device. For more information on clock control
and domains, see
, Power, Reset, and Clock Management.
2706
Timers
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated