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General-Purpose Timers
Table 16-2. Clock, Power, and Reset Domains for GP Timers
Timer
Interface Clock
Functional Clock
Power Domain
GPTIMER1
WKUP_L4_ICLK
GPT1_FCLK
WKUP
GPTIMER2 through
PER_L4_ICLK
GPTx_ALWON_FCLK (x = 2
PER
GPTIMER9
through 9)
GPTIMER10 and 11
CORE_L4_ICLK
GPTx_FCLK (x = 10 or 11)
CORE
GP timers can be selected as the source of GPTi_FCLK (32-kHz clock or 12, 13, 16.8, 19.2, 26, or 38.4
MHz) at the PRCM level in the corresponding registers. For more information, see
, Power,
Reset, and Clock Management.
lists the GP timer PRCM clock selection bits.
Table 16-3. GP Timer PRCM Clock Selection Bits
Name
Associated PRCM Clock Output
Selection Bit
GPT1_FCLK
GPT1_FCLK
PRCM.CM_CLKSEL_WKUP[0]
CLKSEL_GPT1
PRCM.CM_CLKSEL_PER [0:7]
GPT[2:9]_FCLK
GPT[2:9]_ALWON_FCLK
CLKSEL_GPT[2:9]
PRCM.CM_CLKSEL_CORE [6]
GPT10_FCLK
GPT10_FCLK
CLKSEL_GPT10
PRCM.CM_CLKSEL_CORE [7]
GPT11_FCLK
GPT11_FCLK
CLKSEL_GPT11
From a global system power-management perspective, when one or both of the GP timer clocks is no
longer required, the GP timers can be deactivated at the PRCM level in the corresponding registers.
lists the GP timer PRCM clock control bits.
Table 16-4. GP Timer PRCM Clock Control Bits
Name
Associated PRCM Clock
Enable Bit
Autoidle Bit
Output
GPT1_FCLK
GPT1_FCLK
PRCM.CM_FCLKEN_WKUP[0]
N/A
EN_GPT1 bit
PRCM.CM_FCLKEN_PER [3:10]
GPT[2:9]_FCLK
GPT[2:9]_ALWON_FCLK
N/A
EN_GPT[2:9] bit
PRCM.CM_FCLKEN1_CORE [11]
GPT10_FCLK
GPT10_FCLK
N/A
EN_GPT10 bit
PRCM.CM_FCLKEN1_CORE [12]
GPT11_FCLK
GPT11_FCLK
N/A
EN_GPT11 bit
GPT1_ICLK
PRCM.CM_ICLKEN_WKUP[0]
PRCM.CM_AUTOIDLE_WKUP[0]
WKUP_L4_ICLK
EN_GPT1 bit
AUTO_GPT1 bit
GPT[2:9]_ICLK
PER_L4_ICLK
PRCM.CM_ICLKEN_PER[3:10]
PRCM.CM_AUTOIDLE_PER[3:10]
EN_GPT[2:9] bit
AUTO_GPT[2:9] bit
GPT10_ICLK
PRCM.CM_ICLKEN1_CORE[11]
PRCM.CM_AUTOIDLE1_CORE[11]
EN_GPT10 bit
AUTO_GPT10 bit
CORE_L4_ICLK
GPT11_ICLK
PRCM.CM_ICLKEN1_CORE[12]
PRCM.CM_AUTOIDLE1_CORE[12]
EN_GPT11 bit
AUTO_GPT11 bit
2707
SWPU177N – December 2009 – Revised November 2010
Timers
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