Texas Instruments OMAP36 Series, Technical Reference Manual

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SCM Programming Model
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13.5.2 Extended-Drain I/Os and PBIAS Cells Programming Guide
NOTE: The device can be supplied by an external power IC. TI provides such a global solution to
its customers with the TWL50xx power IC.
If the device is associated with the TWL50xx power IC, before using an extended-drain I/O interface, the
software must program the TWL50xx to enable the VMMC1 (for the MMC/SD/SDIO1 module or muxed
GPIO I/Os ) or VIO for (gpio126, gpio127, and gpio129 I/Os), and the LDO and to provide a 1.8-V/3.0-V
voltage. This is done by software through the inter-integrated circuit (I
2
C™) interface that links the device
and TWL50xx IC.
If the application does not want the interface running at 3.0 V, software users must then assert the
VMODE signal to low for 1.8-V activity: in this case, the PBIAS is connected to ground. (See
Figure 13-24 .)
Table 13-66 lists the control signal with the corresponding control bits from the
CONTROL. CONTROL_PBIAS_LITE , CONTROL. CONTROL_PROG_IO1 and
CONTROL. CONTROL_WKUP_CTRL registers to configure the PBIAS and the extended-drain I/O cells.
These signals can be software-controlled.
Table 13-66. Control Signals
Control Signal Bit for MMC/SD/SDIO1 Module Using Bit for GPIO I/Os Using PBIAS1 Cell Reset Value
PBIAS0 Cell
PWRDNZ CONTROL. CONTROL_PBIAS_LITE [1] CONTROL. CONTROL_PBIAS_LITE [9]PBIASLIT 0
PBIASLITEPWRDNZ0 EPWRDNZ1;
CONTROL. CONTROL_WKUP_CTRL [6]GPIO_IO
_PWRDNZ
VMODE CONTROL. CONTROL_PBIAS_LITE [0] CONTROL. CONTROL_PBIAS_LITE [8] 1
PBIASLITEVMODE0 PBIASLITEVMODE1
SUPPLY_HIGH CONTROL. CONTROL_PBIAS_LITE [7] CONTROL. CONTROL_PBIAS_LITE [15] 0
PBIASLITESUPPLYHIGH0 PBIASLITESUPPLYHIGH1
SPEEDCTRL CONTROL. CONTROL_PROG_IO1 [20] N/A 0
PRG_SDMMC1_SPEEDCTRL
VMODEERROR CONTROL. CONTROL_PBIAS_LITE [3] CONTROL. CONTROL_PBIAS_LITE [11] 0
PBIASLITEVMODEERROR0 bit PBIASLITEVMODEERROR1
The two PBIAS cells support two ranges of I/O power supply: 1.8 V, typical for low-voltage applications,
and 3.0 V, typical for high-voltage applications. For each supply voltage range, the cell generates suitable
bias voltage (PBIAS) for extended-drain PMOS devices.
NOTE: If SDMMC1_VDDS (or SIM_VDDS) is supplied before the device reset is released, the
voltage must be 3 V. It is not recommended to supply the vdds_mmc1 (or vdds_sim) pad
with 1.8 V unless software has configured the PBIAS cells accordingly.
CAUTION
A PBIAS cell must be programmed according to peripheral power supply
voltage. See
Table 13-67 .
Table 13-67. Voltage Configuration
(1)
PBIASLITEVMODE Configuration SDMMC1_VDDS/SIM_VDDS Voltage Reset Value
1.8 V 1.8 V Normal 1.8-V operation
1.8 V 3.0 V Damaging configuration
(2)
(1)
For damaging configuration, hardware system protection is provided to prevent deterioration of the associated extended-drain
I/Os.
(2)
It is forbidden to use these modes.
2536System Control Module SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated