Texas Instruments OMAP36 Series, Technical Reference Manual

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SCM Functional Description
Table 13-13. MSuspendMux Control Registers
Physical Address Register Name Description Access
0x4800 2290 CONTROL_MSUSPENDMUX_0 Control the use of MSuspend signals at module R/W
level
0x4800 2294 CONTROL_MSUSPENDMUX_1 R/W
0x4800 2298 CONTROL_MSUSPENDMUX_2 R/W
0x4800 229C CONTROL_MSUSPENDMUX_3 R/W
0x4800 22A0 CONTROL_MSUSPENDMUX_4 R/W
0x4800 22A4 CONTROL_MSUSPENDMUX_5 R/W
These registers provide an entry for each module that must consider the MSuspend signals from the
processors (MPU and/or DSP). For each module, the sensitivity to the MSuspend signals is defined within
five possibilities (coded using 3 bits):
•
0b000: No sensitivity; no MSuspend signal reaches the module.
• 0b001: Sensitivity to the MPU MSuspend signal (the DSP signal is ignored)
• 0b010: Sensitivity to the DSP MSuspend signal (the MPU signal is ignored)
• 0b011: Sensitivity to the logical ORed MPU and DSP MSuspend signals
• 0b100: Sensitivity to the logical ANDed MPU and DSP MSuspend signals
• Other values: No sensitivity; no MSuspend signal reaches the module.
The logic used to combine the MSuspend signals from the processors is implemented within the SCM.
MSuspend signals are active low.
CAUTION
Use care when using combined sensitivity settings (ANDing or ORing DSP and
MPU MSuspend signals).
ORing the DSP and MPU MSuspend signals creates a situation where the
module is suspended when at least one processor is under debug; therefore,
when one processor is halted, stepping within the code of the other one does
not change the module suspended state.
Not all modules use the MSUSPEND signal. See the TRM chapter for each
module to determine whether the module supports the MSUSPEND signal.
All MSUSPEND signals coming out of the MPU and DSP are resynchronized
within the SCM by using the control module interface clock.
13.4.7.3 IVA2.2 Boot Registers
Table 13-14 describes the IVA2.2 boot registers.
Table 13-14. IVA2.2 Boot Registers
Physical Address Register Name Description Access
0x4800 2400 CONTROL_IVA2_BOOTADDR IVA2.2 boot loader address register R/W
0x4800 2404 CONTROL_IVA2_BOOTMOD IVA2.2 boot mode register R/W
The CONTROL. CONTROL_IVA2_BOOTADDR register defines the physical address for the IVA2 boot
loader and drives the IVA2_BOOTADDR[21:0] signals out from the control block to the IVA2 subsystem.
The CONTROL. CONTROL_IVA2_BOOTMOD register defines the IVA2 boot mode and drives the
IVA2_BOOTMOD[3:0] signals out from the control block to the IVA2.2 subsystem. Based on the value of
IVA2_BOOTMOD[3:0], the ROM boot loader executes different boot modes of IVA2.2.
Table 13-15 lists the IVA2.2 boot modes.
2475 SWPU177N – December 2009 – Revised November 2010 System Control Module
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