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SCM Integration
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The SCM is connected on the L4-Core interconnect. The power, reset, and clock management (PRCM)
module provides the module interface clock (CORE_L4_ICLK) and the POR signal. The PRCM generates
one global reset per power domain (CORE_RSTPWRON_RET for the CORE power domain and
WKUP_RSTPWRON for the WKUP power domain). The SCM does not respond to a warm reset or to an
L4 reset.
13.3.1 Clocking, Reset, and Power-Management Scheme
13.3.1.1 Clock
The main sequential logic within the SCM is accessible in a register file through the L4-Core. The only
clock provided to the SCM is the interface clock, CORE_L4_ICLK. This clock comes from the PRCM
module and is controlled by the PRCM.CM_ICLKEN1_CORE[6] EN_OMAPCTRL bit (0 = disables the
clock, 1 = enables the clock) and the PRCM.CM_AUTOIDLE1_CORE[6] AUTO_OMAPCTRL bit
(enables/disables automatic control of the interface clock).
For further information, see
, Power, Reset, and Clock Management.
The wake-up control module is configured through the L4-Core interface of the core control module and is
accessed from the core control module through a dedicated interface. This interface uses the L4-Core
interface clock (CORE_L4_ICLK) divided by 4 or 2 according to the
CONTROL.
[2] WKUPCTRLCLOCKDIV bit. Only this wake-up interface clock
(WKUP_ICLK) is propagated to the wake-up control module.
13.3.1.2 Resets
The SCM responds only to the internal POR and to the device type. The
CONTROL.
[1] SOFTRESET bit has no effect; the SCM is not affected by a warm
reset.
The internal POR is not a direct image of the POR input pin (SYS_NRESPWRON). The PRCM module
generates an internal POR signal per power domain and activates the internal POR when the
eFuse-related settings (such as the device type) are initialized. The core control module of the CORE
power domain responds to the CORE POR (CORE_RSTPWRON_RET). The wake-up control module of
the WKUP power domain responds to the POR (WKUP_RSTPWRON).
NOTE:
References in the TRM to the POR refer to the internal POR as seen by the SCM.
On emulator devices, the debugger can also control the internal POR signal though the
JTAG interface.
For further information, see
, Power, Reset, and Clock Management.
13.3.1.3 Power Domain
The SCM is split into two blocks: the core control module, which is attached to the CORE power domain
and can be in either active, retention, or off state, and the wake-up control module, which belongs to the
WKUP power domain.
NOTE:
The SCM is fully built with retention flip-flop.
For further information, see
, Power, Reset, and Clock Management.
2440
System Control Module
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated
