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SDRAM Controller (SDRC) Subsystem
Table 10-135. SMS_INTERCLASS_ARBITER
Address Offset
0x0000 0160
Physical Address
0x6C00 0160
Instance
SMS
Description
This register controls the PWM counter that defines the priority alternation between class 1 and class 2.
Type
RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
RESERVED
CLASS2PRIO
RESERVED
CLASS1PRIO
Bits
Field Name
Description
Type
Reset
31:24
RESERVED
Write 0s for future compatibility. Read returns 0s.
RW
0x00
23:16
CLASS2PRIO
Class 2 high-priority window width (clock cycle count). Do not set to
RW
0x40
0x00.
15:8
RESERVED
Write 0s for future compatibility. Read returns 0s.
RW
0x00
7:0
CLASS1PRIO
Class 1 high-priority window width (clock cycle count). Do not set to
RW
0x40
0x00.
Table 10-136. Register Call Summary for Register SMS_INTERCLASS_ARBITER
SDRAM Controller (SDRC) Subsystem
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Table 10-137. SMS_CLASS_ROTATIONm
Address Offset
0x0000 0164 + (0x0000 0004 * m)
Index
m = 0 to 2
Physical Address
0x6C00 0164 + (0x0000 0004 * m)
Instance
SMS
Description
This register controls the number of consecutive services that is allocated to a thread whose transactions have
been split by the rotation engine.
Type
RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
RESERVED
NOFSERVICES
Bits
Field Name
Description
Type
Reset
31:5
RESERVED
Write 0s for future compatibility. Read returns 0s.
RW
0x0000000
4:0
NOFSERVICES
Number of RE split transactions serviced consecutively when the
RW
0x01
thread gets granted by the arbitration logic.
Table 10-138. Register Call Summary for Register SMS_CLASS_ROTATIONm
SDRAM Controller (SDRC) Subsystem
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2309
SWPU177N – December 2009 – Revised November 2010
Memory Subsystem
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