Texas Instruments OMAP36 Series, Technical Reference Manual

Page: 2261 / 3738

CLK
CLK
CMD WRITE
READ CMD
DQ
DQ
DQS
DQS
DDR data-write
DDR data-read
CAS latency
sdrc-014
DQ
DQ
DQS
DQS
Data and data strobe from DDR-SDRAM
Data strobe is internally delayed
to respect data setup and hold time
sdrc-015
Public Version
www.ti.com
SDRAM Controller (SDRC) Subsystem
Figure 10-57. Generic DDR Data-Write and Data-Read Waveforms
Figure 10-58 shows the DDR SDRAM data and data strobe DQS signals exiting synchronously and in
phase during a data read. DQS signals are used to sample incoming data internally and, hence, must be
delayed to create data-setup and data-hold time at the synchronization flip-flop inputs, as shown in the
bottom waveforms of
Figure 10-58 . This is the goal of the DLL/CDL module.
Figure 10-58. Required Synchronization DFF Input Signals
10.2.4.4.11.2 DLL/CDL Module Architecture
Figure 10-59 shows how the DLL/CDL interacts with the synchronization flip-flops. See Table 10-102 for
more information on device pins and SDRC data-lane configurations regarding DQS.
2261 SWPU177N – December 2009 – Revised November 2010 Memory Subsystem
Copyright © 2009–2010, Texas Instruments Incorporated