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General-Purpose Memory Controller
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PFPWENROUNDROBIN bit. When a request to another chip-select is received while the prefetch and
write-posting engine is active, priority is given to the new request. The request processed thereafter is the
prefetch and write-posting engine request, even if another interconnect request is passed in the mean
time. The engine keeps control of the bus for an additional number of requests programmed in the
GPMC.
[19:16] PFPWWEIGHTEDPRIO bit field. Control is then passed to
the direct interconnect request.
As an example, the round-robin arbitration scheme is selected with PFPWWEIGHTEDPRIO set to 0x2.
Considering the prefetch and write-posting engine and the interconnect interface are always requesting
access to the external interface, the GPMC grants priority to the direct interconnect access for one
request. The GPMC then grants priority to the engine for three requests, and finnaly back to the direct
interconnect access, until the arbiter is reset when one of the two initiators stops initiating requests.
10.1.6 GPMC Use Cases and Tips
10.1.6.1 How to Set GPMC Timing Parameters for Typical Accesses
10.1.6.1.1 External Memory Attached to the GPMC Module
As discussed in the introduction to this chapter, the GPMC module supports the following external
memory types:
•
Asynchronous or synchronous, 8-bit or 16-bit-width memory or device
•
16-bit address/data-multiplexed or not multiplexed NOR flash device
•
8- or 16-bit NAND flash device
The following examples show how to calculate GPMC timing parameters by showing a typical parameter
setup for the access to be performed.
The example is based on a 512-Mb multiplexed NOR flash memory with the following characteristics:
•
Type: NOR flash (address/data-multiplexed mode)
•
Size: 512M bits
•
Data Bus: 16 bits wide
•
Speed: 104-MHz clock frequency
•
Read access time: 80 ns
10.1.6.1.2 Typical GPMC Setup
lists some of the I/Os of the GPMC module.
Table 10-17. GPMC Signals
Signal Name
I/O
Description
GPMC_FCLK
Internal
Functional and interface clock. Acts as the time reference.
gpmc_clk
I/O
External clock provided to the external device for synchronous operations
gpmc_a[11: 1]
O
Address
gpmc_d[15: 0]
I/O
Data-multiplexed with addresses A[16:1] on memory side
gpmc_ncs
O
Chip-select
gpmc_nadv_ale
O
Address valid enable
gpmc_noe_nre
O
Output enable (read access only)
gpmc_nwe
O
Write enable (write access only)
gpmc_wait[3:0]
I
Ready signal from memory device. Indicates when valid burst data is ready to be read
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Memory Subsystem
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated
