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General-Purpose Memory Controller
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Table 10-16. Write-Posting Mode Configuration (continued)
Bit Field
Register
Value
Comments
ENABLEENGINE
1
Engine enabled
STARTENGINE
[0]
1
Starts the prefetch engine
10.1.5.14.4.5 FIFO Control in Write-Posting Mode
The FIFO can be filled directly by the MPU or by an sDMA channel.
In MPU filling mode, the FIFO status can be monitored through the FIFOPOINTER or through the
GPMC.
[16] FIFOTHRESHOLDSTATUS bit. FIFOPOINTER indicates the
current number of available free byte places in the FIFO, and the FIFOTHRESHOLDSTATUS bit, when
set, indicates that at least FIFOTHRESHOLD free byte places are available in the FIFO.
An interrupt can be issued by the GPMC if the GPMC.
[0] FIFOEVENTENABLE bit is
set. When the interrupt is fired, the GPMC.
[0] FIFOEVENTSTATUS bit is set. To
clear the interrupt, the MPU must write enough bytes to fill the FIFO, or enough bytes to get below the
programmed threshold, and the FIFOEVENTSTATUS bit must be cleared to get further interrupt events.
The FIFOEVENTSTATUS bit must always be cleared prior to asserting the FIFOEVENTENABLE bit to
clear any out-of-date logged interrupt event. This interrupt must be enabled after enabling the
STARTENGINE bit.
The posting completion can be monitored through the GPMC.
COUNTVALUE field. COUNTVALUE indicates the current number of remaining data to be written based
on the TRANSFERCOUNT value. An interrupt is issued by the GPMC when the write-posting process
completes (that is, COUNTVALUE equal to 0) if the GPMC.
TERMINALCOUNTEVENTENABLE bit is set. When the interrupt is fired, the
GPMC.
[1] TERMINALCOUNTSTATUS bit is set. To clear the interrupt, the MPU must
clear the TERMINALCOUNTSTATUS bit. The TERMINALCOUNTSTATUS bit must always be cleared
prior to asserting the TERMINALCOUNTEVENTENABLE bit to clear any out-of-date logged interrupt
event.
NOTE:
The COUNTVALUE value is valid only if the write-posting engine is active and started, and
an interrupt is issued only when COUNTVALUE reaches 0 (that is, when the posting engine
automatically goes from active to inactive).
In DMA filling mode, the DMAMode bit field in the GPMC.
[2] DMAMODE
bit must be set so that the GPMC issues a DMA hardware request when at least FIFOTHRESHOLD
bytes-free places are available in the FIFO. The DMA channel owning this DMA request must be
programmed so that a number of bytes equal to the value programmed in the FIFOTHRESHOLD bit field
are written into the FIFO during the DMA access. The DMA request remains active until the associated
number of bytes has effectively been written into the FIFO, and no other DMA request can be issued until
the ongoing active request has been completed.
Any potentially active DMA request is cleared when the prefetch engine goes from inactive to active
prefetch (STARTENGINE set to 1). The associated DMA channel must always be enabled by the MPU
after setting the STARTENGINE bit so that an out-of-date active DMA request does not trigger spurious
DMA transfers.
In write-posting mode, the DMA or the MPU fill the FIFO with no consideration to the associated byte
enables. Any byte stored in the FIFO is written into the memory device.
10.1.5.14.4.6 Optimizing NAND Access Using the Prefetch and Write-Posting Engine
Access time to a NAND memory device can be optimized for back-to-back accesses if the associated nCS
signal is not deasserted between accesses. The GPMC access engine can track prefetch engine
accesses to optimize the access timing parameter programmed for the allocated chip-select, if no
2184
Memory Subsystem
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated
