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General-Purpose Memory Controller
In prefetch mode, the TERMINALCOUNT event is also a source of DMA requests if the number of bytes
to be prefetched is not a multiple of FIFOTHRESHOLD, the remaining bytes in the FIFO can be read by
the DMA channel using the last DMA request. This assumes that the number of remaining bytes to be
read is known and controlled through the DMA channel programming model.
Any potentially active DMA request is cleared when the prefetch engine goes from inactive to active
prefetch (the STARTENGINE bit is set to 1). The associated DMA channel must always be enabled by the
MPU after setting the STARTENGINE bit so that the out-of-date active DMA request does not trigger
spurious DMA transfers.
10.1.5.14.4.4 Write-Posting Mode
The write-posting mode is selected when the GPMC.
[0] ACCESSMODE bit
is set.
The MCU NAND software driver must issue the correct address pointer initialization command (page
program) before the engine can start writing data into the NAND memory device. The engine starts when
the GPMC.
[0] STARTENGINE bit is set to 1. The STARTENGINE bit
clears automatically when posting completes. When all data have been written to the NAND memory
device, the MCU NAND software driver must issue the second cycle program command and monitor the
status for programming process completion (adding ECC handling, if required).
If used, the ECC calculator engine must be started (configured, reset, and enabled) before the posting
engine is started so that the ECC parities are properly calculated on all data written by the prefetch engine
to the associated chip-select.
In write-posting mode, the GPMC.
[3] SYNCHROMODE bit must be cleared
so that posting starts as soon as the STARTENGINE bit is set and the FIFO is not empty.
If the STARTENGINE bit is set after the NAND address phase (page program command), the
STARTENGINE setting is effective only after the actual NAND command completion. To prevent GPMC
stall during this NAND command phase, set the STARTENGINE bit field before the NAND address
completion and ensure that the associated DMA channel is enabled after the NAND address phase.
The posting engine issues a write request when valid data are available from the FIFO and until the
programmed GPMC.
[13:0] TRANSFERCOUNT accesses have been
completed.
The STARTENGINE bit clears automatically when posting completes. When all data have been written to
the NAND memory device, the MCU NAND software driver must issue the second cycle program
command and monitor the status for programming process completion. The closing program command
phase must only be issued when the full NAND page has been written into the NAND flash write buffer,
including the spare area data and the ECC parities, if used.
Table 10-16. Write-Posting Mode Configuration
Bit Field
Register
Value
Comments
STARTENGINE
[0]
0
Write-posting engine can be configured
only if STARTENGINE is set to 0.
ENGINECSSELECTOR
0 to 7
Selects the chip-select associated with a
NAND device where the prefetch engine is
active
ACCESSMODE
1
Selects write-posting mode
FIFOTHRESHOLD
Selects the maximum number of bytes
read or written by the host on DMA or
interrupt request
TRANSFERCOUNT
Selects the number of bytes to be read or
written by the engine from/to the selected
chip-select
SYNCHROMODE
0
Engine starts the access to chip-select as
soon as STARTENGINE is set.
ENABLEOPTIMIZEDACCESS
0/1
See
.
CYCLEOPTIMIZATION
2183
SWPU177N – December 2009 – Revised November 2010
Memory Subsystem
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