DATA[15:0]
Command
WEONTIME=0
WEOFFTIME
CSWROFFTIME
WRCYCLETIME
CSONTIME=0
nBE0/CLE
nCS
nWE
nADV/ALE
gpmc-022
DATA[15:0]
Address
WEONTIME=0
WEOFFTIME
ADVWROFFTIME = WRCYCLETIME
CSWROFFTIME = WRCYCLETIME
WRCYCLETIME
ADVONTIME=0
CSONTIME=0
nBE0/CLE
nCS
nWE
nADV/ALE
gpmc-023
Public Version
www.ti.com
General-Purpose Memory Controller
Figure 10-22. NAND Command Latch Cycle
NOTE:
CLE is shared with the nBE0 output signal and has an inverted polarity from BE0. The
NAND qualifier deals with this. During the asynchronous NAND data access cycle, nBE0
(also nBE1) must not toggle, because it is shared with CLE.
NAND flash memories do not use byte enable signals.
10.1.5.14.1.4 Address Latch Cycle
Writing data at the GPMC.
location (i = 0 to 7) places the data as the NAND
partial address value on the bus, using a regular asynchronous write access.
•
nCS is controlled by the CSONTIME and CSWROFFTIME timing parameters.
•
ALE is controlled by the ADVONTIME and ADVWROFFTIME timing parameters.
•
nWE is controlled by the WEONTIME and WEOFFTIME timing parameters.
•
CLE and nRE (nOE) are maintained inactive.
shows the NAND address latch cycle.
Figure 10-23. NAND Address Latch Cycle
2159
SWPU177N – December 2009 – Revised November 2010
Memory Subsystem
Copyright © 2009–2010, Texas Instruments Incorporated