GPMC
Device
gpmc_d[15:0]
gpmc_ncs[2]
gpmc_nadv_ale
gpmc_noe
gpmc_nwe
gpmc_nbe0_cle
gpmc_nbe1
gpmc_nwp
gpmc_wait[2]
External device/
memory
D[15:0]
nADV/ALE
R/nB
nWE
nOE/nRE
nWP
nCS
16
A[16:1]/D[15:0]
nCS[2]
nADV/ALE
nOE/nRE
nWE
nBE0/CLE
nBE1
nWP
WAIT[2]
CLK
gpmc_clk
CLE
gpmc−003
Public Version
General-Purpose Memory Controller
www.ti.com
NOTE:
The device does not provide the A0 byte address line required for random-byte addressable
8-bit wide device interfacing (for multiplexed and nonmultiplexed protocol). Hence, an 8-bit
device must be connected to the D[7:0] / gpmc_d[7:0] data bus (rather than D[15:8] /
gpmc_d[15:8]) of the GPMC controller. This limits the use of 8-bit wide device interfacing to
byte-alias access.
Figure 10-3. GPMC to 16-Bit NAND Device
NOTE:
The device does not provide the A0 byte address line required for random-byte addressable
8-bit wide device interfacing (for multiplexed and nonmultiplexed protocol). Hence, an 8-bit
device must be connected to the D[7:0]/gpmc_d[7:0] data bus (rather than
D[15:8]/gpmc_d[15:8]) of the GPMC controller. This limits the use of 8-bit wide device
interfacing to byte-alias accesses.
lists the GPMC subsystem I/O pins.
Table 10-1. GPMC I/O Description
Pin Name
I/O
Description
gpmc_a[11:1]
O
Address
gpmc_d[15:0]
I/O
Data
gpmc_ncs[7:0]
O
Chip-selects (active low)
gpmc_clk
I/O
Clock
(1)
gpmc_nadv_ale
O
Address valid (active low). Also used as address latch enable (active high)
for NAND protocol memories.
gpmc_noe_nre
O
Output enable (active low). Also used as read enable (active low) for NAND
protocol memories.
gpmc_nwe
O
Write enable (active low)
(1)
This output signal is also used as re-timing input
2116Memory Subsystem
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated