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Display Subsystem Functional Description
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received on the video port.
•
Transparent-burst mode The transparent-burst mode is used by increasing the pixel clock frequency
generated by the display controller with in addition an increase of the horizontal blanking period.
7.4.3.3.5 Interleaving Mode
Video mode can output command mode packets, which are provided to DSI through the L4 interconnect,
during the blanking periods of the video stream sequence on the PPI link. These command mode packets
can be programmed as high-speed packets or low-power packets.
During a video stream sequence on the PPI link, four types of gap exist:
•
BLLP gap: Blanking period during VSA, VBP, and VFP lines
•
HSA gap: Blanking period during VACT lines; always between HS and HE short packet
•
HBP gap: Blanking period during VACT lines; always between HS/HE short packet and data pixel long
packet
•
HFP gap: Blanking period during VACT lines; always between data pixel long packet and the end of
the current VACT line
To perform interleaving in a particular gap, video mode must be set to go into low-power state during the
blanking gap. Each type of gap has separate configurable register bits that determine whether a blanking
long packet will be sent or the link will go into low-power state during the gap on the PPI link. If low-power
state is set during a gap, the DSI module performs interleaving during that period.
Two set of registers are available for:
•
High-speed interleaving (when high-speed command mode packets must be sent during a video
stream on the PPI link)
•
Low-power interleaving (when low-power command mode packets must be sent during a video stream
on the PPI link)
7.4.3.3.5.1 HS Command Mode Interleaving Programming Model
shows the various HS mode scenarios in interleaving mode during a blanking gap. For each
type of blanking gap, a dedicated bit field determines the number of TxByteClkHS clock cycles used for
interleaving in HS command mode packets.
•
The BL_HS_INTERLEAVING[31:16]
bit field defines the number of TxByteClkHS
clock cycles used to interleave HS command mode packets during a BLLP gap.
•
The HBP_HS_INTERLEAVING[7:0]
bit field defines the number of TxByteClkHS
clock cycles used to interleave HS command mode packets during an HBP gap.
•
The HFP_HS_INTERLEAVING[15:8]
bit field defines the number of TxByteClkHS
clock cycles used to interleave HS command mode packets during an HFP gap.
•
The HSA_HS_INTERLEAVING[23:16]
bit field defines the number of TxByteClkHS
clock cycles used to interleave HS command mode packets during an HSA gap.
These programmable values must be programmed to satisfy the timings for the clock and data lane to
enter and exit HS mode latency. According to the scenario, different equations must be considered when
calculating the register values.
1666
Display Subsystem
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated
