LCD
controller
output
pins
Pixel clock
Pix1
Pixel data [3:0]
Pix2
Pix4
Pix3
Pixel data
dss_data[0]
dss-005
dss_data[1]
dss_data[2]
dss_data[3]
Public Version
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Display Subsystem Environment
–
In active matrix technology, the ac-bias signal acts as an output-enable signal to indicate when data
must be latched using the pixel clock. This signal is multiplexed on the chip-level boundary with
dss_acbias.
7.2.1.1.3 LCD Output and Data Format for the Parallel Interface
This section describes the pixel data bus and shows timing diagrams of transactions and synchronizations
in both RFBI and bypass modes.
through
show the pixel data bus for bypass mode, depending on the use of 4-, 8-,
12-, 16-, 18-, or 24-pixel data output pins. In RFBI mode, the pixel data bus is reformatted in accordance
with the input and output data bus width.
lists the number of displayed pixels per pixel clock cycle based on the type of display panel.
Table 7-5. Number of Displayed Pixels per Pixel Clock Cycle Based on Display
Type
Display Panel
Number of Displayed
Pixels per Pixel Clock Cycle
Monochrome 4-bit
4
Monochrome 8-bit
8
Passive matrix color
8/3
Active matrix
1
•
Passive matrix technology, Monochrome mode
Monochrome displays use either a 4-bit or 8-bit interface. Each bit represents one pixel (on or off),
which means that either 4 or 8 pixels are sent to the LCD at each pixel clock.
and
show 4- and 8-bit monochrome displays, respectively.
Figure 7-5. LCD Pixel Data Monochrome4 Passive Matrix
1573
SWPU177N – December 2009 – Revised November 2010
Display Subsystem
Copyright © 2009–2010, Texas Instruments Incorporated
