Public Version
Camera ISP Register Manual
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Table 6-679. CSI2_CTx_IRQSTATUS
Address Offset
0x0000 0088 + (x * 0x20)
Index
x = 0 to 7
Physical Address
Instance
See
See
Description
INTERRUPT STATUS REGISTER - Context
This register regroups all the events related to Context.
Type
RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
RESERVED
LE_IRQ
LS_IRQ
FE_IRQ
FS_IRQ
CS_IRQ
RESERVED
LINE_NUMBER_IRQ
FRAME_NUMBER_IRQ
ECC_CORRECTION_IRQ
Bits
Field Name
Description
Type
Reset
31:9
RESERVED
Write 0s for future compatibility. Read returns 0.
R
0x000000
8
ECC_CORRECTION_IRQ
Context - ECC has been used to do the correction of the
RW
0
only 1-bit error status (long packet only).
W1toClr
0x0: READS: Event is false.
WRITES: Status bit unchanged.
0x1: READS: Event is true (pending).
WRITES: Status bit is reset.
7
LINE_NUMBER_IRQ
Contexc - Line number reached status.
RW
0
W1toClr
0x0: READS: Event is false.
WRITES: Status bit unchanged.
0x1: READS: Event is true (pending).
WRITES: Status bit is reset.
6
FRAME_NUMBER_IRQ
Context - Frame counter reached status
RW
0
W1toClr
0x0: READS: Event is false.
WRITES: Status bit unchanged.
0x1: READS: Event is true (pending).
WRITES: Status bit is reset.
5
CS_IRQ
Context - Check-Sum mismatch status.
RW
0
W1toClr
0x0: READS: Event is false.
WRITES: Status bit unchanged.
0x1: READS: Event is true (pending).
WRITES: Status bit is reset.
4
RESERVED
Write 0s for future compatibility. Read returns 0.
R
0
3
LE_IRQ
Context - Line end sync code detection status.
RW
0
W1toClr
0x0: READS: Event is false.
WRITES: Status bit unchanged.
0x1: READS: Event is true (pending).
WRITES: Status bit is reset.
2
LS_IRQ
Context - Line start sync code detection status.
RW
0
W1toClr
0x0: READS: Event is false.
WRITES: Status bit unchanged.
0x1: READS: Event is true (pending).
WRITES: Status bit is reset.
1550
Camera Image Signal Processor
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated