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IVA2.2 Subsystem Register Manual
Bits
Field Name
Description
Type
Reset
5
SEQ_ERROR
SEQ_ERROR IRQ clear
w/1toSet
0x0
4
DMA_ERROR
DMA_ERROR IRQ clear
w/1toSet
0x0
3
SPARE_0
Spare #0 interrupt clear (reserved for future use)
w/1toSet
0x0
Reads returns 0
Write 0 for SW forward compatibility
2
IVLCD
iVLCD IRQ clear
w/1toSet
0x0
1
iLF
iLF IRQ clear
w/1toSet
0x0
0
iME
iME IRQ clear
w/1toSet
0x0
Table 5-680. Register Call Summary for Register SEQ_IRQCLR
IVA2.2 Subsystem Basic Programming Model
•
Video and Sequencer Module interrupt Handling
IVA2.2 Subsystem Register Manual
•
Table 5-681. SEQ_IRQSET
Address Offset
0x0000 0048
Physical Address
0x0009 0048
Instance
SEQ
Description
This register is used to set the interrupt bits (used to test interrupt): write 0: no effect write 1: sets the
corresponding bit in the
register, and triggers the interrupt line if not already active and the
associated event is enabled in
reads always return 0
Type
W
Bits
Field Name
Description
Type
Reset
31:23
RESERVED
Reserved
W
0x0
Reads returns 0
Write 0 for SW forward compatibility
22
TCERRINT1
TCERRINT1 IRQ set
w/1toSet
0x0
21
TCERRINT0
TCERRINT0 IRQ set
w/1toSet
0x0
20
CCERRINT
CCERRINT IRQ set
w/1toSet
0x0
19
CCINT2
CCINT2 IRQ set
w/1toSet
0x0
18
CCINT1
CCINT1 IRQ set
w/1toSet
0x0
17
CCINT8
CCINT8 IRQ set
w/1toSet
0x0
16
CCINT7
CCINT7 IRQ set
w/1toSet
0x0
15
CCINT6
CCINT6 IRQ set
w/1toSet
0x0
14
CCINT5
CCINT5 IRQ set
w/1toSet
0x0
13
CCINT4
CCINT4 IRQ set
w/1toSet
0x0
12
CCINT3
CCINT3 IRQ set
w/1toSet
0x0
11
CCINTG
CCINTG IRQ set
w/1toSet
0x0
10
CCMPINT
CCMPINT IRQ set
w/1toSet
0x0
9
RESERVED
Reserved
R
0x0
8
HOST_MBX
HOST_MBX IRQ set
w/1toSet
0x0
7
SPARE_2
Spare #2 interrupt set (reserved for future use)
w/1toSet
0x0
Reads returns 0
Write 0 for SW forward compatibility
6
SPARE_1
Spare #1 interrupt set (reserved for future use)
w/1toSet
0x0
Reads returns 0
Write 0 for SW forward compatibility
5
SEQ_ERROR
SEQ_ERROR IRQ set
w/1toSet
0x0
4
DMA_ERROR
DMA_ERROR IRQ set
w/1toSet
0x0
3
SPARE_0
Spare #0 interrupt set (reserved for future use)
w/1toSet
0x0
Reads returns 0
Write 0 for SW forward compatibility
1047
SWPU177N – December 2009 – Revised November 2010
IVA2.2 Subsystem
Copyright © 2009–2010, Texas Instruments Incorporated