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SLAU780 – August 2018

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MSP432E411Y-BGAEVM User's Guide

User's Guide

SLAU780 – August 2018

MSP432E411Y-BGAEVM User's Guide

This guide provides an overview on how to get started quickly with the

MSP432E411Y-BGAEVM

,

including power, header pinouts and connections, communication interfaces, and programming interfaces.

Contents

1

Board Overview

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2

2

Power the MSP432E411Y-BGAEVM

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3

2.1

Emulator Power

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3

2.2

External 3.3-V Source Only

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3

2.3

External 5-V Source Only

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3

2.4

External 3.3-V and 5-V Source

...................................................................................

4

2.5

Measure Current Consumption

...................................................................................

4

3

Header Pinouts and Connections

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5

3.1

J11 – External Power Connector

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5

3.2

J6 – Power Rail Header

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5

3.3

J7 – External Peripheral Interface Header

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6

3.4

LCD Interface Header

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7

3.5

J1, J2, J3, J4 – BoosterPack Interface Headers

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9

3.6

J5 – Additional GPIO Pin Header

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10

4

Communication Interfaces

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11

4.1

Ethernet

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11

4.2

USB-OTG

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11

5

Programming Interfaces

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12

5.1

JTAG

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12

5.2

ETM Trace

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12

5.3

BSL

..................................................................................................................

13

6

Software Development

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14

6.1

Software Description

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14

6.2

Source Code

.......................................................................................................

14

6.3

Tool Options

.......................................................................................................

14

7

Schematics

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15

Trademarks

SimpleLink, BoosterPack, Code Composer Studio are trademarks of Texas Instruments.
Arm, Cortex, Keil are registered trademarks of Arm Limited.
IAR Embedded Workbench is a registered trademark of IAR Systems.
All other trademarks are the property of their respective owners.

Summary of Contents for MSP432E411Y-BGAEVM

Page 1: ...t Consumption 4 3 Header Pinouts and Connections 5 3 1 J11 External Power Connector 5 3 2 J6 Power Rail Header 5 3 3 J7 External Peripheral Interface Header 6 3 4 LCD Interface Header 7 3 5 J1 J2 J3 J4 BoosterPack Interface Headers 9 3 6 J5 Additional GPIO Pin Header 10 4 Communication Interfaces 11 4 1 Ethernet 11 4 2 USB OTG 11 5 Programming Interfaces 12 5 1 JTAG 12 5 2 ETM Trace 12 5 3 BSL 13 ...

Page 2: ...pheral Interface EPI hibernation module motion control pulse width modulation and a multitude of simultaneous serial connectivity The MSP432E411Y BGAEVM also features a fully compliant 40 pin BoosterPack plug in module header a user switch two user LEDs and dedicated reset and wake switches The preprogrammed quick start application on the EVM is an application that performs a self test on the onbo...

Page 3: ...shows the location of JP8 Figure 2 Power Selection If USB host functionality is required from the onboard USB OTG connector provide 5 V to the board through the external power header J11 or the BoosterPack header J3 2 2 External 3 3 V Source Only To use an external 3 3 V source to power the EVM connect the 3 3 V and GND lines of the supply to the 3 3V and GND pins of the external power header J11 ...

Page 4: ...3 for 5V Disconnect the onboard 3 3 V LDO U5 from the 3 3 V power rail by removing the jumper on JP8 to prevent back powering the LDO Figure 2 shows the location for JP8 2 5 Measure Current Consumption To measure current consumption remove the JP1 JP2 or JP3 jumpers and place an ammeter across the header pins Connect this jumper when not performing current measurements Figure 3 shows the location ...

Page 5: ...xternal Power Connector J11 Pinout J11 Pin Signal 1 3 3V 2 GND 3 GND 4 5V 3 2 J6 Power Rail Header Header J6 contains connections for all the power rails and reference voltages used by the MSP432E411Y device Figure 4 shows header J6 and Table 3 lists the pinout Figure 4 External Power Connector J6 Table 3 External Power Connector J6 Pinout J6 Pin Signal Description 1 VREFA Reference voltage for AD...

Page 6: ...ernal Peripheral Interface EPI The EPI can be connected to an onboard IS42S16320F 7TL 512 megabit SDRAM U2 buy shorting all the header pins on J7 horizontally as shown in Figure 5 Alternatively the EPI pins can be used to connect to an external device by removing the headers on J7 and connecting to the outside pins of J7 as shown in Figure 6 Figure 5 Header J7 With All Jumpers to Connect Onboard S...

Page 7: ...S15 41 42 DQ15 EP0S14 43 44 BA1 DQ14 EP0S13 45 46 BA0 DQ13 EP0S12 47 48 A12 DQ12 EP0S11 49 50 A11 DQ11 EP0S10 51 52 A10 DQ10 EP0S09 53 54 A9 DQ9 EP0S08 55 56 A8 DQ8 EP0S07 57 58 A7 DQ7 EP0S06 59 60 A6 DQ6 EP0S05 61 62 A5 DQ5 EP0S04 63 64 A4 DQ4 EP0S03 65 66 A3 DQ3 EP0S02 67 68 A2 DQ2 EP0S01 69 70 A1 DQ1 EP0S00 71 72 A0 DQ0 3 4 LCD Interface Header Header J9 contains all of the signals for the inte...

Page 8: ...DDATA21 30 29 LCDDATA20 PS0 PT3 LCDDATA19 28 27 LCDDATA18 PT2 PJ5 LCDDATA17 26 25 LCDDATA16 PJ4 PJ3 LCDDATA15 24 23 LCDDATA14 PJ2 PN6 LCDDATA13 22 21 LCDDATA12 PN7 PT1 LCDDATA11 20 19 LCDDATA10 PT0 PS7 LCDDATA09 18 17 LCDDATA08 PS6 PS5 LCDDATA07 16 15 LCDDATA06 PS4 PR7 LCDDATA05 14 13 LCDDATA04 PR6 PR3 LCDDATA03 12 11 LCDDATA02 PF7 PR5 LCDDATA01 10 9 LCDDATA00 PR4 PJ6 LCDAC 8 7 GND GND PR2 LCDLP 6...

Page 9: ...11Y BGAEVM User s Guide 3 5 J1 J2 J3 J4 BoosterPack Interface Headers Headers J1 J2 J3 and J4 are aligned correctly and follow the pinout requirements to comply with the BoosterPack plug in module pinout standard as shown on www ti com byob Figure 8 shows the pinouts for the J1 J2 J3 and J4 headers Figure 8 BoosterPack Plug in Module Header Pinout ...

Page 10: ...available for use Figure 9 shows the location for J5 and Table 6 lists the pinout Figure 9 Header J5 Location Table 6 Header J5 Pinout MSP432E411Y Pin J5 Pin J5 Pin MSP432E411Y Pin VDD 3 3 V 40 39 GND PD6 38 37 PG6 PQ5 36 35 PM5 PG2 34 33 PA1 PA0 32 31 PF3 PF4 30 29 PF2 PF0 28 27 PF1 PC0 26 25 PQ7 PG7 24 23 PQ6 PN2 22 21 PN1 PQ4 20 19 PS2 PB1 18 17 PB0 PL6 16 15 PC2 PL7 14 13 PC3 PC1 12 11 PN0 PF5...

Page 11: ...an also synchronize events over the network using the IEEE 1588 precision time protocol The existing SimpleLink SDK network stack includes an example of using this feature The Ethernet jack on the EVM contains two LEDs one green and one yellow that are controlled by pins PN0 and PN1 on the MSP432E411Y When configured for Ethernet operation the application should control these pins directly because...

Page 12: ... connectors JA supports the 20 pin Arm standard JTAG programming interface and JB supports the 10 pin Arm standard mini JTAG programming interface Figure 10 shows the two Arm JTAG connectors When using an external emulator if the emulator does not provide power to the board apply power as described in Section 2 Figure 10 Arm JTAG Connectors 5 2 ETM Trace The MSP432E411Y BGAEVM supports ETM Trace c...

Page 13: ... OFF position Figure 12 shows the BSL switches and the BSL connector with the switches in position to enable the SPI BSL interface Table 7 shows which switch bank controls which BSL Interface Switch bank S6 connects 4 7 kΩ resistors to the I2 C BSL lines if I2 C pullups are needed Figure 12 BSL Area on MSP432E411Y BGAEVM Table 7 BSL Switch Bank Interfaces Switch Bank BSL Interface SW3 SPI SW4 UART...

Page 14: ...r Library These applications demonstrate the capabilities of the MSP432E411Y microcontroller and provide a starting point for the development of the final application for use on the MSP432E411Y BGAEVM 6 2 Source Code The source code is provided as part of the SimpleLink MSP432E4 SDK 6 3 Tool Options The source code installation includes directories containing projects makefiles and binaries for th...

Page 15: ... 6 7 8 SW3 78H01T 1 2 3 4 SW4 78F01T 1 2 3 4 SW5 78F01T 1 2 3 4 SW6 78F01T 4 7k R10 4 7k R11 VDD TP3 DNP TP4 DNP TP5 DNP TP6 DNP TP7 DNP TP8 DNP TP9 DNP TP10 DNP BSLTX BSLRX BSLSOMI BSLSIMO BSLCLK BSLSTE BSLSDA BSLSCL PA0 PA1 PA2 PA3 PA5 PA4 PB2 PB3 PB2 PB3 1 2 3 4 5 6 7 8 9 10 BSL GND BSLRX BSLTX BSLSDA BSLSCL BSLCLK BSLSIMO BSLSOMI RSTn BSLSTE 0 R15 0 R7 DNP 4 1 2 3 J11 3V3 5V0 1 2 3 4 5 6 7 8 9...

Page 16: ... VSS VDD PA0 PA1 PA2 PA3 PA4 PA5 PB2 PB3 SW1 10k R4 0 1uF C5 100 R3 VDD VSS RSTn WAKE SW7 VSS 1 0M R5 51 R2 VBAT 0 1uF C4 VSS RSTn RSTn OSC0 OSC1 XOSC0 XOSC1 4 87k R6 VSS RBIAS EN0RXI_P EN0RXI_N EN0TXO_N EN0TXO_P HIBn TARGET_VBUS VSS 33k R31 VSS OTGD_N 0 R29 0 R26 DNP 0 R28 DNP 0 R27 OTGD_P PL6 PL7 PL6_EXT PL7_EXT TARGET_ID 100 R30 PB0 D 1 D 2 ID 3 GND 4 NC 5 VBUS 6 TPD4S012DRYR U4 VSS OTGD_N OTGD...

Page 17: ...S28 EPI0S29 EPI0S30 EPI0S31 EPI0S32 EPI0S33 EPI0S34 EPI0S35 EPI0S01 EPI0S02 EPI0S03 EPI0S04 EPI0S05 EPI0S06 EPI0S07 EPI0S08 EPI0S09 EPI0S10 EPI0S11 EPI0S12 EPI0S13 EPI0S14 EPI0S15 EPI0S16 EPI0S17 EPI0S00 S00 S01 S02 S03 S04 S05 S06 S07 S08 S09 S10 S11 S12 S13 S14 S15 S16 S17 S18 S19 S20 S21 S22 S23 S24 S25 S26 S27 S28 S29 S30 S31 S32 S33 S34 S35 0 1uF C3 0 1uF C2 0 1uF C1 VDD_SD VDD VDD_SD VSS GPI...

Page 18: ... TI Resource NO OTHER LICENSE EXPRESS OR IMPLIED BY ESTOPPEL OR OTHERWISE TO ANY OTHER TI INTELLECTUAL PROPERTY RIGHT AND NO LICENSE TO ANY TECHNOLOGY OR INTELLECTUAL PROPERTY RIGHT OF TI OR ANY THIRD PARTY IS GRANTED HEREIN including but not limited to any patent right copyright mask work right or other intellectual property right relating to any combination machine or process in which TI product...

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