AES_ACCEL Registers
452
SLAU208Q – June 2008 – Revised March 2018
Copyright © 2008–2018, Texas Instruments Incorporated
AES Accelerator
15.3.4 AESADIN Register
AES Accelerator Data In Register
AESADIN is shown in
and described in
.
Figure 15-9. AESADIN Register
15
14
13
12
11
10
9
8
AESDIN1x (DIN Byte n+1)
w-0
w-0
w-0
w-0
w-0
w-0
w-0
w-0
7
6
5
4
3
2
1
0
AESDIN0x (DIN Byte n)
w-0
w-0
w-0
w-0
w-0
w-0
w-0
w-0
Table 15-5. AESADIN Register Description
Bit
Field
Type
Reset
Description
15-8
AESDIN1x
W
0
AES data in byte n+1 when AESADIN is written as word.
Do not use these bits for byte access.
Do not mix word and byte access.
Always reads as zero.
7-0
AESDIN0x
W
0
AES data in byte n when AESADIN is written as word.
AES next data in byte when AESADIN_L is written as byte.
Do not mix word and byte access.
Always reads as zero.
15.3.5 AESADOUT Register
AES Accelerator Data Out Register
AESADOUT is shown in
and described in
.
Figure 15-10. AESADOUT Register
15
14
13
12
11
10
9
8
AESDOUT1x (DOUT Byte n+1)
r-0
r-0
r-0
r-0
r-0
r-0
r-0
r-0
7
6
5
4
3
2
1
0
AESDOUT0x (DOUT Byte n)
r-0
r-0
r-0
r-0
r-0
r-0
r-0
r-0
Table 15-6. AESADOUT Register Description
Bit
Field
Type
Reset
Description
15-8
AESDOUT1x
R
0
AES data out byte n+1 when AESADOUT is read as word.
Do not use these bits for byte access.
Do not mix word and byte access.
7-0
AESDOUT0x
R
0
AES data out byte n when AESADOUT is read as word.
AES next data out byte when AESADOUT_L is read as byte.
Do not mix word and byte access.