Texas Instruments MSP430F67661 Manual Download

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MSP430F67661 Microcontroller

SLAZ506AC – JANUARY 2013 – REVISED MAY 2021

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Summary of Contents for MSP430F67661

Page 1: ...dvisories 3 4 Fixed by Compiler Advisories 3 5 Nomenclature Package Symbolization and Revision Identification 4 5 1 Device Nomenclature 4 5 2 Package Markings 4 5 3 Memory Mapped Hardware Revision TLV Structure 5 6 Advisory Descriptions 6 7 Revision History 26 www ti com Table of Contents SLAZ506AC JANUARY 2013 REVISED MAY 2021 Submit Document Feedback MSP430F67661 Microcontroller 1 Copyright 2021...

Page 2: ...M11 PMM12 PMM14 PMM15 PMM18 PMM20 PMM26 PORT15 PORT19 PORT26 RTC8 SD3 SYS16 UCS11 USCI36 USCI37 USCI41 USCI42 USCI47 USCI50 2 Preprogrammed Software Advisories Advisories that affect factory programmed software The check mark indicates that the issue is present in the specified revision Errata Number Rev A BSL7 Functional Advisories www ti com 2 MSP430F67661 Microcontroller SLAZ506AC JANUARY 2013 ...

Page 3: ...ion Errata Number Rev A CPU21 CPU22 CPU40 Refer to the following MSP430 compiler documentation for more details about the CPU bugs workarounds TI MSP430 Compiler Tools Code Composer Studio IDE MSP430 Optimizing C C Compiler Check the silicon_errata option MSP430 Assembly Language Tools MSP430 GNU Compiler MSP430 GCC MSP430 GCC Options Check msilicon errata and msilicon errata warn options MSP430 G...

Page 4: ...Fully qualified development support product XMS devices and X development support tools are shipped against the following disclaimer Developmental product is intended for internal evaluation purposes MSP devices have been characterized fully and the quality and reliability of the device have been demonstrated fully TI s standard warranty applies Predictions show that prototype devices XMS have a g...

Page 5: ...on how to locate the TLV structure and read out the HW_ID can be found in the device User s Guide www ti com Nomenclature Package Symbolization and Revision Identification SLAZ506AC JANUARY 2013 REVISED MAY 2021 Submit Document Feedback MSP430F67661 Microcontroller 5 Copyright 2021 Texas Instruments Incorporated ...

Page 6: ...el repeat sequence of channels ADC12CTL1 ADC12CONSEQx In addition the timer overflow flag cannot be used to detect an overflow ADC12IFGR2 ADC12TOVIFG Workaround 1 For manual trigger mode ADC12CTL0 ADC12SC ensure each ADC conversion is completed by first checking ADC12CTL1 ADC12BUSY bit before starting a new conversion 2 For timer trigger mode ADC12CTL1 ADC12SHP ensure the timer period is greater t...

Page 7: ...ply could be switched back to DVCC again When the system is running with the AUXVCC2 supply use SVMH to monitor AUXVCC2 voltage When AUXVCC2 is lower than the SVMH setting the program drives the chip into LPMx 5 After DVCC ramps up back again trigger one of the wake up pins The power supply could be switched back to DVCC again AUXPMM2 AUXPMM Module Category Functional Function Latch up in AUXPMM D...

Page 8: ...rio 2 Limit the supply voltage ramp up time through a series resistor e g 10 Ohm in the critical supply path Side effects such as voltage dips due to high current consumption of the device need to be considered BSL7 BSL Module Category Software in ROM Function BSL does not start after waking up from LPMx 5 Description When waking up from LPMx 5 mode the BSL does not start as it does not clear the ...

Page 9: ...may result in device hang up Description When an active interrupt service request is pending and the POPM instruction is used to set the Status Register SR and initiate entry into a low power mode the device may hang up Workaround None It is recommended not to use POPM instruction on the Status Register Refer to the table below for compiler specific fix implementation information IDE Compiler Vers...

Page 10: ...ough flash erase Description When single stepping over code that initiates an INFOD Flash memory erase the program counter is corrupted Workaround None NOTE This erratum applies to debug mode only CPU37 CPU Module Category Functional Function Wrong program trace display in the debugger while using conditional jump instructions Description The state storage window displays an incorrect sequence of ...

Page 11: ...branching to a wrong address location in code and leading to wrong program execution For example a conditional jump instruction followed by data section 0140h 0x8012 Loop DEC W R6 0x8014 DEC W R7 0x8016 JNZ Loop 0x8018 Value1 DW 0140h Workaround In assembly insert a NOP between the jump conditional jump instruction and program code with instruction that contains PC as destination register or the d...

Page 12: ... if POPM W is used OR 2 Use the POPM instruction for all but the last restore operation For the the last restore operation use the POP assembly instruction instead For instance instead of using POPM W 5 R13 Use POPM W 4 R12 POP W R13 Refer to the table below for compiler specific fix implementation information IDE Compiler Version Number Notes IAR Embedded Workbench Not affected C code is not impa...

Page 13: ...ccess interrupts 20 bit wide accesses to the DMA address registers OR 2 When accessing the DMA address registers enable the Read Modify Write disable bit DMARMWDIS 1 or temporarily disable all active DMA channels DMAEN 0 OR 3 Use word access for accessing the DMA address registers Note that this limits the values that can be written to the address registers to 16 bit values lower 64K of Flash DMA7...

Page 14: ...tion If a DMA access to the module occurs while that module is issuing a wait state the module may exhibit undefined behavior Workaround Ensure that DMA accesses to the affected modules occur only when the modules are not in operation For example with the MPY module ensure that the MPY operation is completed before triggering a DMA access to the MPY module EEM17 EEM Module Category Debug Function ...

Page 15: ...ce dependent low or high supply voltage levels if the LPMx 5 debug support feature is enabled To avoid a potentially unreliable debug session or general issues with JTAG device connectivity and the resulting bad customer experience Texas Instruments has chosen to remove the LPMx 5 debug support feature from common MSP430 IDEs including TIs Code Composer Studio 6 1 0 with msp430 emu updated to vers...

Page 16: ...ramming tools purchased from TI MSP FET LaunchPad update to CCS version 6 1 3 later or IAR version 6 30 or later to resolve the issue 2 If using the MSP GANG Production Programmer use v1 2 3 0 or later 3 For custom programming solutions refer to the specification on MSP430 Programming Via the JTAG Interface User s Guide SLAU320 revision V or newer and use MSPDebugStack v3 7 0 12 or later For MSPDe...

Page 17: ...med frequency of operation on exit from LPM3 and LPM4 for up to 6 us The increased frequency has the potential to change the expected timing behavior of peripherals that select SMCLK as the clock source Workaround Use XT2 as the SMCLK oscillator source instead of the DCO or Do not disable the clock request bit for SMCLKREQEN in the Unified Clock System Control 8 Register UCSCTL8 This means that al...

Page 18: ...he SVSMHCTL and SVSMLCTL registers is immediately followed by an LPM2 LPM3 LPM4 entry without waiting the requisite settling time PMMIFG SVSMLDLYIFG 0 and PMMIFG SVSMHDLYIFG 0 or The following two conditions are met The SVSL module is configured for a fast wake up or when the SVSL SVML module is turned off The affected SVSMLCTL register settings are shaded in the following table and The SVSH SVMH ...

Page 19: ...er PMM configuration functions Use the following function PMM15Check void to determine whether or not the existing PMM configuration is affected by the erratum The return value of the function is 1 if the configuration is affected and 0 if the configuration is not affected unsigned char PMM15Check void First check if SVSL SVML is configured for fast wake up if SVSMLCTL SVSLE SVSMLCTL SVSLE SVSMLCT...

Page 20: ...up from LPM2 3 4 the internal VCORE voltage can experience voltage drop below the corresponding SVSL and SVML threshold recommendation according to User s Guide leading to an unexpected SVSL SVML event Depending on PMM configuration this event triggers a POR or an interrupt Note As soon the SVSL or the SVML is enabled in Normal performance mode the device is in slow wakeup mode and this erratum do...

Page 21: ...nal Function In system debugging causes the PMALOCKED bit to be always set Description The port mapping controller registers cannot be modified when single stepping or halting at break points between a valid password write to the PMAPWD register and the expected lock of the port mapping PMAP registers This causes the PMAPLOCKED bit to remain set and not clear as expected Note This erratum only app...

Page 22: ...onal Function Incorrect conversion result in twos complement mode when VFS is applied Description When the SD converter is configured in twos complement mode with left or right alignment and any OSR setting applying the VFS voltage at the input will result in an erroneous output Workaround None SYS16 SYS Module Category Functional Function Fast Vcc ramp after device power up may cause a reset Desc...

Page 23: ...urce I2C clock Workaround Use LFXTCLK via ACLK or HFXTCLK via SMCLK as clock source BRCLK for I2C in master mode with external clock source USCI37 USCI Module Category Functional Function Reading RXBUF during an active I2C communication might result in unintended bus stalls Description The falling edge of SCL bus line is used to set an internal RXBUF written flag register which is used to detect a...

Page 24: ... Workaround None USCI47 USCI Module Category Functional Function eUSCI SPI slave with clock phase UCCKPH 1 Description The eUSCI SPI operates incorrectly under the following conditions 1 The eUSCI_A or eUSCI_B module is configured as a SPI slave with clock phase mode UCCKPH 1 AND 2 The SPI clock pin is not at the appropriate idle level low for UCCKPL 0 high for UCCKPL 1 when the UCSWRST bit in the...

Page 25: ...o UCxTXBUF while the UCxSTE input is in the inactive state may not be transmitted correctly If the eUSCI is used with UCSTEM 1 STE pin used to output an enable signal data is transmitted correctly Workaround When using the STE pin in conflict prevention mode UCSTEM 0 only move data into UCxTXBUF when UCxSTE is in the active state If an active transfer is aborted by UCxSTE transitioning to the mast...

Page 26: ...4 2019 to May 19 2021 Page Changed the document format and structure updated the numbering format for tables figures and cross references throughout the document 6 Revision History www ti com 26 MSP430F67661 Microcontroller SLAZ506AC JANUARY 2013 REVISED MAY 2021 Submit Document Feedback Copyright 2021 Texas Instruments Incorporated ...

Page 27: ...s are subject to change without notice TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource Other reproduction and display of these resources is prohibited No license is granted to any other TI intellectual property right or to any third party intellectual property right TI disclaims responsibility for and you wi...

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