Texas Instruments MSP430F6723 Manual Download

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Revision History

SLAZ340AF – OCTOBER 2012 – REVISED MAY 2021

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MSP430F6723 Microcontroller

Summary of Contents for MSP430F6723

Page 1: ...visories 3 4 Fixed by Compiler Advisories 3 5 Nomenclature Package Symbolization and Revision Identification 4 5 1 Device Nomenclature 4 5 2 Package Markings 4 5 3 Memory Mapped Hardware Revision TLV...

Page 2: ...7 PMM11 PMM12 PMM14 PMM15 PMM18 PMM20 PMM26 PORT15 PORT19 SD3 UCS11 USCI36 USCI37 USCI41 USCI42 USCI47 USCI50 2 Preprogrammed Software Advisories Advisories that affect factory programmed software The...

Page 3: ...Number Rev A CPU21 CPU22 CPU40 Refer to the following MSP430 compiler documentation for more details about the CPU bugs workarounds TI MSP430 Compiler Tools Code Composer Studio IDE MSP430 Optimizing...

Page 4: ...sting null Fully qualified development support product XMS devices and X development support tools are shipped against the following disclaimer Developmental product is intended for internal evaluatio...

Page 5: ...guidance on how to locate the TLV structure and read out the HW_ID can be found in the device User s Guide www ti com Nomenclature Package Symbolization and Revision Identification SLAZ340AF OCTOBER...

Page 6: ...l repeat sequence of channels ADC12CTL1 ADC12CONSEQx In addition the timer overflow flag cannot be used to detect an overflow ADC12IFGR2 ADC12TOVIFG Workaround 1 For manual trigger mode ADC12CTL0 ADC1...

Page 7: ...ply could be switched back to DVCC again When the system is running with the AUXVCC2 supply use SVMH to monitor AUXVCC2 voltage When AUXVCC2 is lower than the SVMH setting the program drives the chip...

Page 8: ...io 2 Limit the supply voltage ramp up time through a series resistor e g 10 Ohm in the critical supply path Side effects such as voltage dips due to high current consumption of the device need to be c...

Page 9: ...pected results Description When using the indirect addressing mode in an instruction with the Program Counter PC as the source operand the instruction that follows immediately does not get executed Fo...

Page 10: ...de with instruction that contains PC as destination register or the data section Refer to the table below for compiler specific fix implementation information IDE Compiler Version Number Notes IAR Emb...

Page 11: ...assembler is required to implement the above workaround manually TI MSP430 Compiler Tools Code Composer Studio Not affected C code is not impacted by this bug User using POPM instruction in assembler...

Page 12: ...lues lower 64K of Flash DMA7 DMA Module Category Functional Function DMA request may cause the loss of interrupts Description If a DMA request starts executing during the time when a module register c...

Page 13: ...e DMA Description In repeated transfer mode the DMA automatically reloads the size counter DMAxSZ once a transfer is complete and immediately continues to execute the next transfer unless the DMA Enab...

Page 14: ...breakpoint is hit or when the debug session is halted Workaround This erratum has been addressed in MSPDebugStack version 3 5 0 1 It is also available in released IDE EW430 IAR version 6 30 3 and CCS...

Page 15: ...as MSP430 DLL v3 4 3 4 OR b Roll back the debug stack by either performing a clean re installation of a previous version of the IDE or by manually replacing the debug stack with a prior version such a...

Page 16: ...1 PMM7 PMM Module Category Functional Function PMMRIE default conditions different than user guide Description The user guide specifies that after a BOR reset condition the SVS will not be configured...

Page 17: ...or SMCLKREQEN in the Unified Clock System Control 8 Register UCSCTL8 This means that all modules that depend on SMCLK to operate successfully should be halted or disabled before entering LPM3 or LPM4...

Page 18: ...ime PMMIFG SVSMLDLYIFG 0 and PMMIFG SVSMHDLYIFG 0 or The following two conditions are met The SVSL module is configured for a fast wake up or when the SVSL SVML module is turned off The affected SVSML...

Page 19: ...L SVMLE SVSMLCTL SVMLE SVSMLCTL SVMLFP Next Check SVSH SVMH settings to see if settings are affected by PMM15 if SVSMHCTL SVSHE SVSMHCTL SVSHFP if SVSMHCTL SVSHMD SVSMHCTL SVSHMD SVSMHCTL SVSMHACE ret...

Page 20: ...chieved if the SVSL or the SVML is configured in Normal performance mode not disabled and not in Full Performance Mode PMM26 PMM Module Category Functional Function Device lock up if RST pin pulled lo...

Page 21: ...5 it is possible that the interrupt is lost Hence this interrupt will not trigger a wakeup from LPMx 5 Workaround None SD3 SD Module Category Functional Function Incorrect conversion result in twos co...

Page 22: ...potential RXBUF overflow If this flag is cleared with a read access from the RXBUF register during a falling edge of SCL the clear condition might be missed This could result in an I2C bus stall at t...

Page 23: ...clock pin is not at the appropriate idle level low for UCCKPL 0 high for UCCKPL 1 when the UCSWRST bit in the UCxxCTLW0 register is cleared If both of the above conditions are satisfied then the foll...

Page 24: ...the eUSCI is used with UCSTEM 1 STE pin used to output an enable signal data is transmitted correctly Workaround When using the STE pin in conflict prevention mode UCSTEM 0 only move data into UCxTXB...

Page 25: ...2019 to May 19 2021 Page Changed the document format and structure updated the numbering format for tables figures and cross references throughout the document 6 www ti com Revision History SLAZ340AF...

Page 26: ...are subject to change without notice TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource Other reproduction and...

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