Texas Instruments MSP430 series Manual Download

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0.5

1.5

VCC

1 ns

VCC(min)

t pw

− Pulse Width − µs

CC(min)

−

3 V

1000

t − Pulse Width − µs

100

t pw

3 V

= t

Rectangular Drop

Triangular Drop

VCC(min)

VCC(start)

AVCC

V(B_IT−)

Brownout

Region

V(SVSstart)

V(SVS_IT−)

Software sets VLD >0:

SVS is active

td(SVSR)

undefined

Vhys(SVS_IT−)

td(BOR)

Brownout

td(SVSon)

td(BOR)

Set POR

Brown-

out

Region

SVS Circuit is Active From VLD > to V

< V(

B_IT−)

SVS out

hys(B_IT−)

MSP430F23x

MSP430F24x(1)

MSP430F2410

www.ti.com

SLAS547I – JUNE 2007 – REVISED DECEMBER 2012

Figure 12. SVS Reset (SVSR) vs Supply Voltage

Figure 13. V

CC(min)

: Square Voltage Drop and Triangle Voltage Drop to Generate an SVS Signal (VLD = 1)

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Summary of Contents for MSP430 series

Page 1: ... Flash Memory Autoscan Feature 4KB RAM 16 Bit Timer_A With Three Capture Compare MSP430F249 MSP430F2491 Registers 60KB 256B Flash Memory 16 Bit Timer_B With Seven Capture Compare 2KB RAM With Shadow Registers MSP430F2410 Four Universal Serial Communication 56KB 256B Flash Memory Interfaces USCI 4KB RAM USCI_A0 and USCI_A1 Available in 64 Pin QFP and 64 Pin QFN Enhanced UART Supporting Auto Baudrat...

Page 2: ...SCI modules and up to 48 I O pins The MSP430F24x1 devices are identical to the MSP430F24x devices with the exception that the ADC12 module is not implemented The MSP430F23x devices are identical to the MSP430F24x devices with the exception that a reduced Timer_B one USCI module and less RAM are integrated Typical applications include sensor systems industrial control applications and hand held met...

Page 3: ...0 P6 6 A6 P4 6 VREF P4 5 XIN P4 1 TB1 P1 0 TACLK CAOUT P4 3 VeREF P4 2 TB2 V Ve REF REF P4 0 TB0 P1 1 TA0 P3 7 P1 2 TA1 P3 5 UCA0RXD UCA0SOMI P1 4 SMCLK P3 6 P1 3 TA2 TMS P2 5 R CA5OSC P1 6 TA1 DVSS P1 5 TA0 AVCC 19 62 20 61 21 60 22 59 23 58 24 57 27 54 26 55 28 53 29 52 30 51 31 50 32 49 40 9 47 2 48 1 46 3 43 6 45 4 44 5 42 7 41 8 37 12 39 10 38 11 36 13 35 14 33 16 34 15 25 56 18 63 17 64 PM O...

Page 4: ...K P6 6 A6 P4 6 TB6 VREF P4 5 TB5 XIN P4 1 TB1 P1 0 TACLK CAOUT P4 3 TB3 VeREF P4 2 TB2 V Ve REF REF P4 0 TB0 P1 1 TA0 P3 7 UCA1RXD UCA1SOMI P1 2 TA1 P3 5 UCA0RXD UCA0SOMI P1 4 SMCLK P3 6 UCA1TXD UCA1SIMO P1 3 TA2 TMS P2 5 R CA5OSC P1 6 TA1 DVSS P1 5 TA0 AVCC 19 62 20 61 21 60 22 59 23 58 24 57 27 54 26 55 28 53 29 52 30 51 31 50 32 49 40 9 47 2 48 1 46 3 43 6 45 4 44 5 42 7 41 8 37 12 39 10 38 11 ...

Page 5: ...E UCA1CLK P6 6 P4 6 TB6 VREF P4 5 TB5 XIN P4 1 TB1 P1 0 TACLK CAOUT P4 3 TB3 DVSS P4 2 TB2 DVSS P4 0 TB0 P1 1 TA0 P3 7 UCA1RXD UCA1SOMI P1 2 TA1 P3 5 UCA0RXD UCA0SOMI P1 4 SMCLK P3 6 UCA1TXD UCA1SIMO P1 3 TA2 TMS P2 5 R CA5OSC P1 6 TA1 DVSS P1 5 TA0 AVCC 19 62 20 61 21 60 22 59 23 58 24 57 27 54 26 55 28 53 29 52 30 51 31 50 32 49 40 9 47 2 48 1 46 3 43 6 45 4 44 5 42 7 41 8 37 12 39 10 38 11 36 1...

Page 6: ... SPI USCI B0 SPI I2C Comp_A Flash 16kB 8kB Timer_B3 3 CC Registers Shadow Reg ADC12 12 Bit 8 Channels Ports P3 P4 P5 P6 4x8 I O AVCC AVSS P1 x P2 x 2x8 P3 x P4 x P5 x P6 x 4x8 XIN XT2IN 2 2 SMCLK ACLK MDB MAB Hardware Multiplier MPY MPYS MAC MACS MSP430F23x MSP430F24x 1 MSP430F2410 SLAS547I JUNE 2007 REVISED DECEMBER 2012 www ti com Functional Block Diagram MSP430F23x 6 Submit Documentation Feedba...

Page 7: ...Flash 60kB 56kB 48kB 32kB Timer_B7 7 CC Registers Shadow Reg ADC12 12 Bit 8 Channels Ports P3 P4 P5 P6 4x8 I O AVCC AVSS P1 x P2 x 2x8 P3 x P4 x P5 x P6 x 4x8 XIN XT2IN 2 2 SMCLK ACLK MDB MAB Hardware Multiplier MPY MPYS MAC MACS USCI A1 UART LIN IrDA SPI USCI B1 SPI I2C MSP430F23x MSP430F24x 1 MSP430F2410 www ti com SLAS547I JUNE 2007 REVISED DECEMBER 2012 Functional Block Diagram MSP430F24x MSP4...

Page 8: ...B0 SPI I2C Comp_A Flash 60kB 48kB 32kB Timer_B7 7 CC Registers Shadow Reg Ports P3 P4 P5 P6 4x8 I O AVCC AVSS P1 x P2 x 2x8 P3 x P4 x P5 x P6 x 4x8 XIN XT2IN 2 2 SMCLK ACLK MDB MAB Hardware Multiplier MPY MPYS MAC MACS USCI A1 UART LIN IrDA SPI USCI B1 SPI I2C MSP430F23x MSP430F24x 1 MSP430F2410 SLAS547I JUNE 2007 REVISED DECEMBER 2012 www ti com Functional Block Diagram MSP430F24x1 8 Submit Docum...

Page 9: ...0CLK 28 I O General purpose digital I O USCI_B0 slave transmit enable USCI A0 clock input output P3 1 UCB0SIMO UCB0SDA 29 I O General purpose digital I O USCI_B0 slave in master out in SPI mode SDA I2 C data in I2 C mode P3 2 UCB0SOMI UCB0SCL 30 I O General purpose digital I O USCI_B0 slave out master in in SPI mode SCL I2 C clock in I2 C mode P3 3 UCB0CLK UCA0STE 31 I O General purpose digital I ...

Page 10: ...AG TCK is the clock input port for device programming test and bootstrap loader start TDI TCLK 55 I Test data input or test clock input The device protection fuse is connected to TDI TCLK TDO TDI 54 I O Test data output TDO TDI data output or programming data input terminal TMS 56 I Test mode select TMS is used as an input port for device programming and test VeREF 10 I Input for an external refer...

Page 11: ...digital I O USCI_B0 slave out master in in SPI mode SCL I2 C clock in I2 C mode P3 3 UCB0CLK UCA0STE 31 I O General purpose digital I O USCI_B0 clock input output USCI A0 slave transmit enable General purpose digital I O USCI_A transmit data output in UART mode slave data in master out in SPI P3 4 UCA0TXD UCA0SIMO 32 I O mode P3 5 UCA0RXD General purpose digital I O USCI_A0 receive data input in U...

Page 12: ...ut or bootstrap loader start in flash devices TCK 57 I Test clock JTAG TCK is the clock input port for device programming test and bootstrap loader start TDI TCLK 55 I Test data input or test clock input The device protection fuse is connected to TDI TCLK TDO TDI 54 I O Test data output TDO TDI data output or programming data input terminal TMS 56 I Test mode select TMS is used as an input port fo...

Page 13: ... O USCI_B0 slave out master in in SPI mode SCL I2 C clock in I2 C mode P3 3 UCB0CLK UCA0STE 31 I O General purpose digital I O USCI_B0 clock input output USCI A0 slave transmit enable General purpose digital I O USCI_A0 transmit data output in UART mode slave data in master out in SPI P3 4 UCA0TXD UCA0SIMO 32 I O mode P3 5 UCA0RXD General purpose digital I O USCI_A0 receive data input in UART mode...

Page 14: ...start in flash devices TCK 57 I Test clock JTAG TCK is the clock input for device programming test and bootstrap loader start TDI TCLK 55 I Test data input or test clock input The device protection fuse is connected to TDI TCLK TDO TDI 54 I O Test data output TDO TDI data output or programming data input terminal TMS 56 I Test mode select TMS is used as an input port for device programming and tes...

Page 15: ...gram counter stack pointer status register and constant generator respectively The remaining registers are general purpose registers Peripherals are connected to the CPU using data address and control buses and can be handled with all instructions Instruction Set The instruction set consists of 51 instructions with three formats and seven address modes Each instruction can operate on word and byte...

Page 16: ...r mode 0 LPM0 CPU is disabled ACLK and SMCLK remain active MCLK is disabled Low power mode 1 LPM1 CPU is disabled ACLK and SMCLK remain active MCLK is disabled DCO dc generator is disabled if DCO not used in active mode Low power mode 2 LPM2 CPU is disabled MCLK and SMCLK are disabled DCO dc generator remains enabled ACLK remains active Low power mode 3 LPM3 CPU is disabled MCLK and SMCLK are disa...

Page 17: ...FG 7 2 5 Maskable 0xFFE6 19 I O port P1 eight flags P1IFG 0 to P1IFG 7 2 5 Maskable 0xFFE4 18 USCI_A1 USCI_B1 receive UCA1RXIFG UCB1RXIFG 2 6 Maskable 0xFFE2 17 USCI_B1 I2C status USCI_A1 USCI_B1 transmit UCA1TXIFG UCB1TXIFG 2 7 Maskable 0xFFE0 16 USCI_B1 I2C receive transmit Reserved 9 10 Reserved 0xFFDE to 0xFFC0 15 to 0 lowest 1 A reset is generated if the CPU tries to fetch instructions from w...

Page 18: ...ss 7 6 5 4 3 2 1 0 01h UCB0TXIE UCB0RXIE UCA0TXIE UCA0RXIE rw 0 rw 0 rw 0 rw 0 UCA0RXIE USCI_A0 receive interrupt enable UCA0TXIE USCI_A0 transmit interrupt enable UCB0RXIE USCI_B0 receive interrupt enable UCB0TXIE USCI_B0 transmit interrupt enable Table 10 Interrupt Flag Register 1 Address 7 6 5 4 3 2 1 0 02h NMIIFG RSTIFG PORIFG OFIFG WDTIFG rw 0 rw 0 rw 1 rw 1 rw 0 WDTIFG Set on watchdog timer ...

Page 19: ...0x20FF to 0x1900 0x20FF to 0x1900 Mirrored Size 2KB 2KB 2KB 0x18FF to 0x1100 0x18FF to 0x1100 0x18FF to 0x1100 Information memory Size 256 Byte 256 Byte 256 Byte Flash 0x10FF to 0x1000 0x10FF to 0x1000 0x10FF to 0x1000 Boot memory Size 1KB 1KB 1KB ROM 0x0FFF to 0x0C00 0x0FFF to 0x0C00 0x0FFF to 0x0C00 RAM mirrored at Size 2KB 2KB 2KB 0x18FF to 0x1100 0x09FF to 0x0200 0x09FF to 0x0200 0x09FF to 0x0...

Page 20: ...Segments A to D can be erased individually or as a group with segments 0 to n Segments A to D are also called information memory Segment A contains calibration data After reset segment A is protected against programming and erasing It can be unlocked but care should be taken not to erase this segment if the device specific calibration data is required 20 Submit Documentation Feedback Copyright 200...

Page 21: ...calibration tag TAG_EMPTY 0xFE Identifier for empty memory areas Table 15 Labels Used by the ADC Calibration Tags LABEL CONDITION AT CALIBRATION DESCRIPTION SIZE ADDRESS OFFSET CAL_ADC_25T85 INCHx 0x1010 REF2_5 1 TA 85 C word 0x000E CAL_ADC_25T30 INCHx 0x1010 REF2_5 1 TA 30 C word 0x000C CAL_ADC_25VREF_FACTOR REF2_5 1 TA 30 C IVREF 1 0 mA word 0x000A CAL_ADC_15T85 INCHx 0x1010 REF2_5 0 TA 85 C wor...

Page 22: ...module is capable of supporting signed and unsigned multiplication as well as signed and unsigned multiply and accumulate operations The result of an operation can be accessed immediately after the operands have been loaded into the peripheral registers No additional clock cycles are required Timer_A3 Timer_A3 is a 16 bit timer counter with three capture compare registers Timer_A3 can support mult...

Page 23: ...GNAL NUMBER 43 P4 7 TBCLK TBCLK ACLK ACLK Timer NA SMCLK SMCLK 43 P4 7 TBCLK INCLK 36 P4 0 TB0 CCI0A 36 P4 0 36 P4 0 TB0 CCI0B ADC12 1 internal CCR0 TB0 DVSS GND DVCC VCC 37 P4 1 TB1 CCI1A 37 P4 1 37 P4 1 TB1 CCI1B ADC12 2 internal CCR1 TB1 DVSS GND DVCC VCC 38 P4 2 TB2 CCI2A 38 P4 2 38 P4 2 TB2 CCI2B CCR2 TB2 DVSS GND DVCC VCC 39 P4 3 TB3 CCI3A 39 P4 3 39 P4 3 TB3 CCI3B CCR3 TB3 DVSS GND DVCC VCC...

Page 24: ...rsal Serial Communications Interface USCI The USCI modules are used for serial data communication The USCI module supports synchronous communication protocols such as SPI 3 or 4 pin or I2 C and asynchronous combination protocols such as UART enhanced UART with automatic baudrate detection LIN and IrDA The USCI A module provides support for SPI 3 or 4 pin UART enhanced UART and IrDA The USCI B modu...

Page 25: ...14A Conversion memory 4 ADC12MEM4 0x0148 Conversion memory 3 ADC12MEM3 0x0146 Conversion memory 2 ADC12MEM2 0x0144 Conversion memory 1 ADC12MEM1 0x0142 Conversion memory 0 ADC12MEM0 0x0140 ADC memory control register15 ADC12MCTL15 0x008F ADC memory control register14 ADC12MCTL14 0x008E ADC memory control register13 ADC12MCTL13 0x008D ADC memory control register12 ADC12MCTL12 0x008C ADC memory cont...

Page 26: ...BCCR2 0x0196 MSP430F23x Capture compare register 1 TBCCR1 0x0194 Capture compare register 0 TBCCR0 0x0192 Timer_B register TBR 0x0190 Capture compare control 2 TBCCTL2 0x0186 Capture compare control 1 TBCCTL1 0x0184 Capture compare control 0 TBCCTL0 0x0182 Timer_B control TBCTL 0x0180 Timer_B interrupt vector TBIV 0x011E Timer_A3 Capture compare register 2 TACCR2 0x0176 Capture compare register 1 ...

Page 27: ...CA0MCTL 0x0064 USCI A0 baud rate control 1 UCA0BR1 0x0063 USCI A0 baud rate control 0 UCA0BR0 0x0062 USCI A0 control 1 UCA0CTL1 0x0061 USCI A0 control 0 UCA0CTL0 0x0060 USCI A0 IrDA receive control UCA0IRRCTL 0x005F USCI A0 IrDA transmit control UCA0IRTCLT 0x005E USCI B0 transmit buffer UCB0TXBUF 0x006F USCI B0 receive buffer UCB0RXBUF 0x006E USCI B0 status UCB0STAT 0x006D USCI B0 I2C Interrupt en...

Page 28: ...SCI B1 control 0 UCB1CTL0 0x00D8 USCI B1 I2C slave address UCB1SA 0x017E USCI B1 I2C own address UCB1OA 0x017C USCI A1 B1 interrupt enable UC1IE 0x0006 USCI A1 B1 interrupt flag UC1IFG 0x0007 Comparator_A Comparator_A port disable CAPD 0x005B Comparator_A control2 CACTL2 0x005A Comparator_A control1 CACTL1 0x0059 Basic Clock Basic clock system control3 BCSCTL3 0x0053 Basic clock system control2 BC...

Page 29: ...pt edge select P2IES 0x002C Port P2 interrupt flag P2IFG 0x002B Port P2 direction P2DIR 0x002A Port P2 output P2OUT 0x0029 Port P2 input P2IN 0x0028 Port P1 Port P1 resistor enable P1REN 0x0027 Port P1 selection P1SEL 0x0026 Port P1 interrupt enable P1IE 0x0025 Port P1 interrupt edge select P1IES 0x0024 Port P1 interrupt flag P1IFG 0x0023 Port P1 direction P1DIR 0x0022 Port P1 output P1OUT 0x0021 ...

Page 30: ...process according to the current JEDEC J STD 020 specification with peak reflow temperatures not higher than classified on the device label on the shipping boxes or reels Recommended Operating Conditions 1 2 Typical values are specified at VCC 3 3 V and TA 25 C unless otherwise noted MIN NOM MAX UNIT During program 1 8 3 6 V execution VCC Supply voltage 3 AVCC DVCC VCC During program or erase 2 2 ...

Page 31: ...HZ µA current 1 MHz DCOCTL CALDCO_1MHZ 3 3 V CPUOFF 0 SCG0 0 SCG1 0 105 C 344 370 OSCOFF 0 fMCLK fSMCLK fACLK 40 C to 85 C 1 5 3 8 2 2 V 32768 Hz 8 4096 Hz 105 C 6 10 5 fDCO 0 Hz 40 C to 85 C 2 4 7 Active mode AM Program executes in flash IAM 4kHz µA current 4 kHz SELMx 11 SELS 1 3 V DIVMx DIVSx DIVAx 11 105 C 7 12 2 CPUOFF 0 SCG0 1 SCG1 0 OSCOFF 0 40 C to 85 C 55 72 fMCLK fSMCLK fDCO 0 0 100 kHz ...

Page 32: ...Hz Active Mode Current mA TA 25 C TA 85 C VCC 2 2 V VCC 3 V TA 25 C TA 85 C MSP430F23x MSP430F24x 1 MSP430F2410 SLAS547I JUNE 2007 REVISED DECEMBER 2012 www ti com Typical Characteristics Active Mode Supply Current Into DVCC and AVCC ACTIVE MODE CURRENT vs ACTIVE MODE CURRENT SUPPLY VOLTAGE vs TA 25 C DCO FREQUENCY Figure 2 Figure 3 32 Submit Documentation Feedback Copyright 2007 2012 Texas Instru...

Page 33: ...OSCOFF 0 40 C 0 8 1 2 25 C 0 9 1 3 2 2 V 85 C 2 4 3 fDCO fMCLK fSMCLK 0 MHz 105 C 6 13 Low power mode 3 fACLK 32768 Hz ILPM3 LFXT1 µA LPM3 current 4 CPUOFF 1 SCG0 1 SCG1 1 40 C 0 9 1 3 OSCOFF 0 25 C 1 1 4 3 V 85 C 3 9 4 3 105 C 10 15 40 C 0 3 0 9 25 C 0 3 0 9 2 2 V 85 C 1 8 2 4 fDCO fMCLK fSMCLK 0 MHz fACLK from internal LF oscillator 105 C 5 5 13 Low power mode 3 ILPM3 VLO VLO µA current LPM3 4 4...

Page 34: ... 3 6 V I Low power mode current µA LPM4 Vcc 1 8 V VCC 3 V Vcc 2 2V MSP430F23x MSP430F24x 1 MSP430F2410 SLAS547I JUNE 2007 REVISED DECEMBER 2012 www ti com Typical Characteristics LPM4 Current LPM4 CURRENT vs TEMPERATURE Figure 4 34 Submit Documentation Feedback Copyright 2007 2012 Texas Instruments Incorporated ...

Page 35: ...4 TB5 TB6 3 V 50 2 2 V 8 fTAext Timer_A Timer_B clock frequency TACLK TBCLK INCLK t H t L MHz fTBext externally applied to pin 3 V 10 2 2 V 8 fTAint Timer_A Timer_B clock frequency SMCLK or ACLK signal selected MHz fTBint 3 V 10 1 An external signal sets the interrupt flag every time the minimum interrupt pulse width t int is met It may be set even with trigger signals shorter than t int Leakage C...

Page 36: ...A to hold the maximum voltage drop specified Output Frequency Ports P1 P2 P3 P4 P5 P6 over recommended ranges of supply voltage and operating free air temperature unless otherwise noted PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT Port output 2 2 V DC 10 fPx y frequency with P1 4 SMCLK CL 20 pF RL 1 kΩ 1 2 MHz 3 V DC 12 load 2 2 V DC 12 Clock output fPort CLK P2 0 ACLK CA2 P1 4 SMCLK CL 20 pF 2 ...

Page 37: ...VOL Low Level Output Voltage V 0 0 10 0 20 0 30 0 40 0 50 0 0 0 0 5 1 0 1 5 2 0 2 5 3 0 3 5 VCC 3 V P4 5 TA 25 C TA 85 C OL I Typical Low Level Output Current mA MSP430F23x MSP430F24x 1 MSP430F2410 www ti com SLAS547I JUNE 2007 REVISED DECEMBER 2012 Typical Characteristics Outputs One output loaded at a time TYPICAL LOW LEVEL OUTPUT CURRENT TYPICAL LOW LEVEL OUTPUT CURRENT vs vs LOW LEVEL OUTPUT V...

Page 38: ...t 3 V s 70 130 210 mV td BOR BOR reset release delay time 2000 µs Pulse duration needed at RST NMI pin to t reset 2 2 V 3 V 2 µs accepted reset internally 1 The current consumption of the brownout module is already included in the ICC current consumption data The voltage level V B_IT Vhys B_IT is 1 8 V 2 During power up the CPU begins code execution following a period of td BOR after VCC V B_IT Vh...

Page 39: ...µs V CC drop V tpw Pulse Width µs VCC 3 V MSP430F23x MSP430F24x 1 MSP430F2410 www ti com SLAS547I JUNE 2007 REVISED DECEMBER 2012 Typical Characteristics POR Brownout Reset BOR Figure 10 VCC drop Level With a Square Voltage Drop to Generate a POR Brownout Signal Figure 11 VCC drop Level With a Triangle Voltage Drop to Generate a POR Brownout Signal Copyright 2007 2012 Texas Instruments Incorporate...

Page 40: ...4 2 1 2 25 VLD 3 2 05 2 2 2 37 VLD 4 2 14 2 3 2 48 VLD 5 2 24 2 4 2 6 VLD 6 2 33 2 5 2 71 VLD 7 2 46 2 65 2 86 VCC dt 3V s see Figure 12 and Figure 13 VLD 8 2 58 2 8 3 V VLD 9 2 69 2 9 3 13 VLD 10 2 83 3 05 3 29 VLD 11 2 94 3 2 3 42 VLD 12 3 11 3 35 3 61 2 VLD 13 3 24 3 5 3 76 2 VLD 14 3 43 3 7 2 3 99 2 VCC dt 3 V s see Figure 12 and Figure 13 VLD 15 1 1 1 2 1 3 external voltage applied on A7 ICC ...

Page 41: ...VSR undefined Vhys SVS_IT 0 1 td BOR Brownout 0 1 td SVSon td BOR 0 1 Set POR Brown out Region SVS Circuit is Active From VLD to V CC V B_IT SVS out Vhys B_IT MSP430F23x MSP430F24x 1 MSP430F2410 www ti com SLAS547I JUNE 2007 REVISED DECEMBER 2012 Figure 12 SVS Reset SVSR vs Supply Voltage Figure 13 VCC min Square Voltage Drop and Triangle Voltage Drop to Generate an SVS Signal VLD 1 Copyright 2007...

Page 42: ... 3 MODx 0 2 2 V 3 V 0 20 0 40 MHz fDCO 4 3 DCO frequency 4 3 RSELx 4 DCOx 3 MODx 0 2 2 V 3 V 0 28 0 54 MHz fDCO 5 3 DCO frequency 5 3 RSELx 5 DCOx 3 MODx 0 2 2 V 3 V 0 39 0 77 MHz fDCO 6 3 DCO frequency 6 3 RSELx 6 DCOx 3 MODx 0 2 2 V 3 V 0 54 1 06 MHz fDCO 7 3 DCO frequency 7 3 RSELx 7 DCOx 3 MODx 0 2 2 V 3 V 0 80 1 50 MHz fDCO 8 3 DCO frequency 8 3 RSELx 8 DCOx 3 MODx 0 2 2 V 3 V 1 10 2 10 MHz f...

Page 43: ...mended ranges of supply voltage and operating free air temperature unless otherwise noted PARAMETER TEST CONDITIONS TA VCC MIN TYP MAX UNIT 1 MHz tolerance over 0 C to 85 C 3 V 2 5 0 5 2 5 temperature 8 MHz tolerance over 0 C to 85 C 3 V 2 5 1 0 2 5 temperature 12 MHz tolerance over 0 C to 85 C 3 V 2 5 1 0 2 5 temperature 16 MHz tolerance over 0 C to 85 C 3 V 3 2 0 3 temperature 2 2 V 0 97 1 1 03 ...

Page 44: ...ion value DCOCTL CALDCO_16MHZ 25 C 3 V to 3 6 V 15 16 16 48 MHz Gating time 2 ms Calibrated DCO Frequencies Overall Tolerance over recommended ranges of supply voltage and operating free air temperature unless otherwise noted PARAMETER TEST CONDITIONS TA VCC MIN TYP MAX UNIT 1 MHz tolerance 40 C to 105 C 1 8 V to 3 6 V 5 2 5 overall 8 MHz tolerance 40 C to 105 C 1 8 V to 3 6 V 5 2 5 overall 12 MHz...

Page 45: ... Supply Voltage V 7 80 7 85 7 90 7 95 8 00 8 05 8 10 8 15 8 20 1 5 2 0 2 5 3 0 3 5 4 0 Frequency MHz TA 40 C TA 25 C TA 85 C TA 105 C MSP430F23x MSP430F24x 1 MSP430F2410 www ti com SLAS547I JUNE 2007 REVISED DECEMBER 2012 Typical Characteristics Calibrated DCO Frequency CALIBRATED 1 MHz FREQUENCY CALIBRATED 8 MHz FREQUENCY vs vs SUPPLY VOLTAGE SUPPLY VOLTAGE Figure 14 Figure 15 CALIBRATED 12 MHz F...

Page 46: ...CO_8MHZ DCO clock wake up time tDCO LPM3 4 µs from LPM3 4 1 BCSCTL1 CALBC1_12MHZ 1 DCOCTL CALDCO_12MHZ BCSCTL1 CALBC1_16MHZ 3 V 1 DCOCTL CALDCO_16MHZ CPU wake up time from 1 fMCLK tCPU LPM3 4 LPM3 4 2 tClock LPM3 4 1 The DCO clock wake up time is measured from the edge of an external wake up signal for example a port interrupt to the first clock edge observable externally on a clock pin MCLK or SM...

Page 47: ...nal Resistor ROSC 1 over recommended ranges of supply voltage and operating free air temperature unless otherwise noted PARAMETER TEST CONDITIONS VCC TYP UNIT DCOR 1 2 2 V 1 8 fDCO ROSC DCO output frequency with ROSC RSELx 4 DCOx 3 MODx 0 MHz 3 V 1 95 TA 25 C DCOR 1 DT Temperature drift 2 2 V 3 V 0 1 C RSELx 4 DCOx 3 MODx 0 DCOR 1 DV Drift with VCC 2 2 V 3 V 10 V RSELx 4 DCOx 3 MODx 0 1 ROSC 100 k...

Page 48: ...n the oscillator XIN and XOUT pins f If conformal coating is used ensure that it does not induce capacitive or resistive leakage between the oscillator pins g Do not route the XOUT line to the JTAG header to support the serial programming adapter as shown in other documentation This signal is no longer required for the serial programming adapter 2 Includes parasitic bond and package capacitance ap...

Page 49: ...illator the following guidelines should be observed a Keep the trace between the device and the crystal as short as possible b Design a good ground plane around the oscillator pins c Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT d Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins e Use assembly materials and praxis to avoid any parasitic ...

Page 50: ...0 100000 00 0 10 1 00 10 00 100 00 Oscillation Allowance W LFXT1Sx 0 LFXT1Sx 2 LFXT1Sx 1 MSP430F23x MSP430F24x 1 MSP430F2410 SLAS547I JUNE 2007 REVISED DECEMBER 2012 www ti com Typical Characteristics LFXT1 Oscillator in HF Mode XTS 1 OSCILLATION ALLOWANCE vs CRYSTAL FREQUENCY CL eff 15 pF TA 25 C Figure 23 OSCILLATOR SUPPLY CURRENT vs CRYSTAL FREQUENCY CL eff 15 pF TA 25 C Figure 24 50 Submit Doc...

Page 51: ...a Keep the trace between the device and the crystal as short as possible b Design a good ground plane around the oscillator pins c Prevent crosstalk from other clock or data lines into oscillator pins XT2IN and XT2OUT d Avoid running PCB traces underneath or adjacent to the XT2IN and XT2OUT pins e Use assembly materials and praxis to avoid any parasitic load on the oscillator XT2IN and XT2OUT pins...

Page 52: ...0 10000 00 100000 00 0 10 1 00 10 00 100 00 Oscillation Allowance W XT2Sx 0 XT2Sx 2 XT2Sx 1 MSP430F23x MSP430F24x 1 MSP430F2410 SLAS547I JUNE 2007 REVISED DECEMBER 2012 www ti com Typical Characteristics XT2 Oscillator OSCILLATION ALLOWANCE vs CRYSTAL FREQUENCY CL eff 15 pF TA 25 C Figure 25 OSCILLATOR SUPPLY CURRENT vs CRYSTAL FREQUENCY CL eff 15 pF TA 25 C Figure 26 52 Submit Documentation Feedb...

Page 53: ...nal TACLK INCLK MHz 3 V 16 Duty cycle 50 10 tTA cap Timer_A capture timing TA0 TA1 TA2 2 2 V 3 V 20 ns Timer_B over recommended ranges of supply voltage and operating free air temperature unless otherwise noted PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT Internal SMCLK ACLK 2 2 V 10 fTB Timer_B clock frequency External TACLK INCLK MHz 3 V 16 Duty cycle 50 10 tTB cap Timer_B capture timing TB0 T...

Page 54: ...2 2 V 30 UCLK edge to SIMO valid tVALID MO SIMO output data valid time ns CL 20 pF 3 V 20 1 fUCxCLK 1 2tLO HI with tLO HI max tVALID MO USCI tSU SI Slave tSU MI USCI tVALID SO Slave For the slave s parameters tSU SI Slave and tVALID SO Slave see the SPI parameters of the attached slave USCI SPI Slave Mode 1 over recommended ranges of supply voltage and operating free air temperature unless otherwi...

Page 55: ... SIMO 1 fUCxCLK tLO HI tLO HI SOMI tSU MI tHD MI tVALID MO MSP430F23x MSP430F24x 1 MSP430F2410 www ti com SLAS547I JUNE 2007 REVISED DECEMBER 2012 Figure 27 SPI Master Mode CKPH 0 Figure 28 SPI Master Mode CKPH 1 Copyright 2007 2012 Texas Instruments Incorporated Submit Documentation Feedback 55 ...

Page 56: ...KPL 1 SOMI tSTE ACC tSTE DIS 1 fUCxCLK tLO HI tLO HI SIMO tSU SI tHD SI tVALID SO tSTE LEAD tSTE LAG MSP430F23x MSP430F24x 1 MSP430F2410 SLAS547I JUNE 2007 REVISED DECEMBER 2012 www ti com Figure 29 SPI Slave Mode CKPH 0 Figure 30 SPI Slave Mode CKPH 1 56 Submit Documentation Feedback Copyright 2007 2012 Texas Instruments Incorporated ...

Page 57: ...uency External UCLK fSYSTEM MHz Duty cycle 50 10 fSCL SCL clock frequency 2 2 V 3 V 0 400 kHz fSCL 100 kHz 4 tHD STA Hold time repeated START 2 2 V 3 V µs fSCL 100 kHz 0 6 fSCL 100 kHz 4 7 tSU STA Setup time for a repeated START 2 2 V 3 V µs fSCL 100 kHz 0 6 tHD DAT Data hold time 2 2 V 3 V 0 ns tSU DAT Data setup time 2 2 V 3 V 250 ns tSU STO Setup time for STOP 2 2 V 3 V 4 µs 2 2 V 50 150 600 tS...

Page 58: ...1 and P2 4 CA1 TA2 mV Figure 37 3 V 400 490 550 TA 85 C V offset Offset voltage 2 2 2 V 3 V 30 30 mV Vhys Input hysteresis CAON 1 2 2 V 3 V 0 0 7 1 4 mV TA 25 C Overdrive 10 mV 2 2 V 80 165 300 Without filter CAF 0 3 ns Response time 3 V 70 120 240 see Figure 32 and Figure 33 t response low to high and high to TA 25 C Overdrive 10 mV 2 2 V 1 4 1 9 2 8 low Without filter CAF 1 3 µs 3 V 0 9 1 5 2 2 ...

Page 59: ...UT V VCC 1 0 V 0 MSP430F23x MSP430F24x 1 MSP430F2410 www ti com SLAS547I JUNE 2007 REVISED DECEMBER 2012 Figure 32 Comparator_A Block Diagram Figure 33 Comparator_A Overdrive Definition Figure 34 Comparator_A Short Resistance Test Condition Figure 35 Comparator_A Short Resistance Test Condition Copyright 2007 2012 Texas Instruments Incorporated Submit Documentation Feedback 59 ...

Page 60: ...rence Volts mV Typical TA Free Air Temperature C 400 450 500 550 600 650 45 25 5 15 35 55 75 95 VCC 2 2 V V REFVT Reference Volts mV Typical MSP430F23x MSP430F24x 1 MSP430F2410 SLAS547I JUNE 2007 REVISED DECEMBER 2012 www ti com Typical Characteristics Comparator_A V RefVT V RefVT vs vs TEMPERATURE TEMPERATURE VCC 3 V VCC 2 2 V Figure 36 Figure 37 SHORT RESISTANCE vs VIN VCC Figure 38 60 Submit Do...

Page 61: ...he ADC12ON control bit unless a conversion is active The REFON bit enables settling of the built in reference before starting an A D conversion 5 Not production tested limits verified by design 12 Bit ADC External Reference 1 over recommended operating free air temperature range unless otherwise noted PARAMETER TEST CONDITIONS VCC MIN MAX UNIT VeREF Positive external reference voltage input VeREF ...

Page 62: ...al 1 Analog input voltage 1 25 V 3 V 2 LSB REF2_5V 1 Load current IVREF 100 µA 900 µA IDL VREF regulation VREF CVREF 5 µF ax 0 5 VREF 3 V 20 ns terminal 2 Error of conversion result 1 LSB Capacitance at pin REFON 1 CVREF 2 2 V 3 V 5 10 µF VREF 3 0 mA IVREF IVREF max Temperature IVREF is a constant in the range of TREF coefficient of built in 2 2 V 3 V 100 ppm C 0 mA IVREF 1 mA reference 2 Settle t...

Page 63: ...CC From Power Supply Apply External Reference Apply External Reference V or Use Internal Reference V eREF REF VREF or VeREF VREF VeREF MSP430F23x MSP430F24x 1 MSP430F2410 www ti com SLAS547I JUNE 2007 REVISED DECEMBER 2012 Figure 40 Supply Voltage and Reference Voltage Design VREF VeREF External Supply Figure 41 Supply Voltage and Reference Voltage Design VREF VeREF AVSS Internally Connected Copyr...

Page 64: ...SB The reference and input signal are already settled 3 Approximately ten Tau τ are needed to get an error of less than 0 5 LSB tSample ln 2n 1 RS RI CI 800 ns where n ADC resolution 12 RS external source resistance 12 Bit ADC Linearity Parameters over recommended operating free air temperature range unless otherwise noted PARAMETER TEST CONDITIONS VCC MIN NOM MAX UNIT 1 4 V VeREF VREF VeREF min 1...

Page 65: ...ON 1 INCH 0Bh VMID V channel 11 VMID is 0 5 VAVCC 3V 1 5 1 5 0 04 Sample time 2 2 V 1400 ADC12ON 1 INCH 0Bh tVMID sample required if channel ns Error of conversion result 1 LSB 3 V 1220 11 is selected 6 1 The sensor current ISENSOR is consumed if ADC12ON 1 and REFON 1 or ADC12ON 1 AND INCH 0Ah and sample signal is high Therefore it includes the constant current through the sensor and the reference...

Page 66: ... flash controller s state machine tFTG 1 fFTG RAM over recommended ranges of supply voltage and operating free air temperature unless otherwise noted PARAMETER TEST CONDITIONS MIN MAX UNIT V RAMh RAM retention supply voltage 1 CPU halted 1 6 V 1 This parameter defines the minimum supply voltage VCC when the data in RAM remains unchanged No program execution should happen during this supply voltage...

Page 67: ...P1 1 TA0 P1 2 TA1 P1 3 TA2 P1 4 SMCLK P1 5 TA0 P1 6 TA1 P1 7 TA2 DVSS DVCC Pad Logic 1 1 0 1 0 1 0 P1REN x MSP430F23x MSP430F24x 1 MSP430F2410 www ti com SLAS547I JUNE 2007 REVISED DECEMBER 2012 APPLICATION INFORMATION Port P1 Pin Schematic P1 0 to P1 7 Input Output With Schmitt Trigger Copyright 2007 2012 Texas Instruments Incorporated Submit Documentation Feedback 67 ...

Page 68: ...I O I 0 O 1 0 P1 1 TA0 1 Timer_A3 CCI0A 0 1 Timer_A3 TA0 1 1 P1 2 I O I 0 O 1 0 P1 2 TA1 2 Timer_A3 CCI1A 0 1 Timer_A3 TA1 1 1 P1 3 I O I 0 O 1 0 P1 3 TA2 3 Timer_A3 CCI2A 0 1 Timer_A3 TA2 1 1 P1 4 I O I 0 O 1 0 P1 4 SMCLK 4 SMCLK 1 1 P1 5 I O I 0 O 1 0 P1 5 TA0 5 Timer_A3 TA0 1 1 P1 6 I O I 0 O 1 0 P1 6 TA1 6 Timer_A3 TA1 1 1 P1 7 I O I 0 O 1 0 P1 7 TA2 7 Timer_A3 TA2 1 1 68 Submit Documentation ...

Page 69: ...rrupt Edge Select Q EN Set P2SEL x P2IES x P2IFG x P2IE x DVSS DVCC P2REN x Pad Logic 1 1 0 1 0 1 0 Bus Keeper EN CAPD x From Comparator_A To Comparator_A MSP430F23x MSP430F24x 1 MSP430F2410 www ti com SLAS547I JUNE 2007 REVISED DECEMBER 2012 Port P2 Pin Schematic P2 0 to P2 4 P2 6 and P2 7 Input Output With Schmitt Trigger Copyright 2007 2012 Texas Instruments Incorporated Submit Documentation Fe...

Page 70: ... P2 1 TAINCLK CA3 DVSS 0 1 1 CA3 1 X X 2 P2 2 I O 0 I 0 O 1 0 CAOUT 0 1 1 P2 2 CAOUT TA0 CA4 TA0 0 0 1 CA4 1 X X 3 P2 3 I O 0 I 0 O 1 0 P2 3 CA0 TA1 Timer_A3 TA1 0 1 1 CA0 1 X X 4 P2 4 I O 0 I 0 O 1 0 P2 4 CA1 TA2 Timer_A3 TA2 0 1 X CA1 1 X 1 6 P2 6 I O 0 I 0 O 1 0 P2 6 ADC12CLK 2 CA6 ADC12CLK 2 0 1 1 CA6 1 X X 7 P2 7 I O 0 I 0 O 1 0 P2 7 TA0 CA7 Timer_A3 TA0 0 1 1 CA7 1 X X 1 X Don t care 2 MSP43...

Page 71: ...APD 5 in DCO P2REN 5 MSP430F23x MSP430F24x 1 MSP430F2410 www ti com SLAS547I JUNE 2007 REVISED DECEMBER 2012 Port P2 Pin Schematic P2 5 Input Output With Schmitt Trigger Table 22 Port P2 5 Pin Functions CONTROL BITS SIGNALS 1 PIN NAME P2 x x FUNCTION CAPD DCOR P2DIR 5 P2SEL 5 P2 5 I O 0 0 I 0 O 1 0 ROSC 0 1 X X P2 5 ROSC CA5 5 DVSS 0 0 1 1 CA5 1 or selected 0 X X 1 X Don t care Copyright 2007 2012...

Page 72: ...UCB0SIMO UCB0SDA 2 4 X 1 P3 2 I O I 0 O 1 0 P3 2 UCB0SOMI UCB0SCL 2 UCB0SOMI UCB0SCL 2 4 X 1 P3 3 I O I 0 O 1 0 P3 3 UCB0CLK UCA0STE 3 UCB0CLK UCA0STE 2 X 1 P3 4 I O I 0 O 1 0 P3 4 UCA0TXD UCA0SIMO 4 UCA0TXD UCA0SIMO 2 X 1 P3 5 I O I 0 O 1 0 P3 5 UCA0RXD UCA0SOMI 5 UCA0RXD UCA0SOMI 2 X 1 P3 6 I O I 0 O 1 0 P3 6 UCA1TXD 5 UCA1SIMO 5 6 UCA1TXD 5 UCA1SIMO 5 2 X 1 P3 7 I O I 0 O 1 0 P3 7 UCA1RXD 5 UCA...

Page 73: ... 1 Timer_B7 TB0 1 1 P4 1 I O I 0 O 1 0 P4 1 TB1 1 Timer_B7 CCI1A and Timer_B7 CCI1B 0 1 Timer_B7 TB1 1 1 P4 2 I O I 0 O 1 0 P4 2 TB2 2 Timer_B7 CCI2A and Timer_B7 CCI2B 0 1 Timer_B7 TB2 1 1 P4 3 I O I 0 O 1 0 P4 3 TB3 1 3 Timer_B7 CCI3A and Timer_B7 CCI3B 1 0 1 Timer_B7 TB3 1 1 1 P4 4 I O I 0 O 1 0 P4 4 TB4 1 4 Timer_B7 CCI4A and Timer_B7 CCI4B 1 0 1 Timer_B7 TB4 1 1 1 P4 5 I O I 0 O 1 0 P4 5 TB5 ...

Page 74: ...1STE 2 UCA1CLK 2 UCB1STE 2 UCA1CLK 2 3 4 X 1 1 P5 1 I O I 0 O 1 0 P5 1 UCB1SIMO 2 UCB1SDA 2 UCB1SIMO 2 UCB1SDA 2 3 5 X 1 2 P5 2 I O I 0 O 1 0 P5 2 UCB1SOMI 2 UCB1SCL 2 UCB1SOMI 2 UCB1SCL 2 3 5 X 1 3 P5 3 I O I 0 O 1 0 P5 3 UCB1CLK 2 UCA1STE 2 UCB1CLK 2 UCA1STE 2 3 X 1 1 X Don t care 2 MSP430F24x and MSP430F24x1 devices only 3 The pin direction is controlled by the USCI module 4 UCA0CLK function ta...

Page 75: ...EMBER 2012 Port P5 Pin Schematic P5 4 to P5 7 Input Output With Schmitt Trigger Table 26 Port P5 4 to P5 7 Pin Functions CONTROL BITS SIGNALS PIN NAME P5 x x FUNCTION P5DIR x P5SEL x P5 4 I O I 0 O 1 0 P5 4 MCLK 4 MCLK 1 1 P5 5 I O I 0 O 1 0 P5 5 SMCLK 5 SMCLK 1 1 P5 6 I O I 0 O 1 0 P5 6 ACLK 6 ACLK 1 1 P5 7 I O I 0 O 1 0 P5 7 TBOUTH SVSOUT 7 Timer_B7 TBOUTH 0 1 SVSOUT 1 1 Copyright 2007 2012 Texa...

Page 76: ...utput With Schmitt Trigger Table 27 Port P6 0 to P6 6 Pin Functions CONTROL BITS SIGNALS 1 PIN NAME P6 x x FUNCTION P6DIR x P6SEL x P5 0 I O I 0 O 1 0 P6 0 A0 2 0 A0 2 X 1 P5 1 I O I 0 O 1 0 P6 1 A1 2 1 A1 2 X 1 P5 2 I O I 0 O 1 0 P6 2 A2 2 2 A2 2 X 1 P5 3 I O I 0 O 1 0 P6 3 A3 2 3 A3 2 X 1 P5 4 I O I 0 O 1 0 P6 4 A4 2 4 A4 2 X 1 P5 5 I O I 0 O 1 0 P6 5 A5 2 5 A5 2 X 1 P6 6 I O I 0 O 1 0 P6 6 A6 2...

Page 77: ...w ti com SLAS547I JUNE 2007 REVISED DECEMBER 2012 Port P6 Pin Schematic P6 7 Input Output With Schmitt Trigger Table 28 Port P6 7 Pin Functions CONTROL BITS SIGNALS 1 PIN NAME P6 x x FUNCTION P6DIR x P6SEL x INCHy P6 7 I O I 0 O 1 0 0 DVSS 1 1 0 P6 7 A7 SVSIN 7 A7 2 X X 1 y 7 SVSIN VLD 15 X X 1 1 X Don t care 2 MSP430F24x and MSP430F23x devices only Copyright 2007 2012 Texas Instruments Incorporat...

Page 78: ...uring Blowing of the Fuse Pin TDO TDI Is Used to Apply the Test Input Data for JTAG Circuitry TDO TDI TDI TCLK TMS TCK Fuse DVCC MSP430F23x MSP430F24x 1 MSP430F2410 SLAS547I JUNE 2007 REVISED DECEMBER 2012 www ti com JTAG Pins TMS TCK TDI TCLK TDO TDI Input Output With Schmitt Trigger 78 Submit Documentation Feedback Copyright 2007 2012 Texas Instruments Incorporated ...

Page 79: ...nts are terminated Activation of the fuse check mode occurs with the first negative edge on the TMS pin after power up or if TMS is being held low during power up The second positive edge on the TMS pin deactivates the fuse check mode After deactivation the fuse check mode remains inactive until another POR occurs After each POR the fuse check mode has the potential to be activated The fuse check ...

Page 80: ...80 Added Development Tool Support section page 2 SLAS547C Updated parametric values in low power mode supply current into VCC excluding external current table page 34 SLAS547D Updated notes and tCMErase MIN value flash memory table page 34 SLAS547E Changed limits on td SVSon parameter page 41 Changed Port 6 0 to 6 6 Pin Functions table page 77 SLAS547F Changed Port 6 7 Pin Functions table page 78 ...

Page 81: ...SOLETE VQFN RGC 64 TBD Call TI Call TI 40 to 105 MSP430F235TRGCR ACTIVE VQFN RGC 64 2500 Green RoHS no Sb Br CU NIPDAU Level 3 260C 168 HR 40 to 105 M430F235T MSP430F235TRGCT ACTIVE VQFN RGC 64 250 Green RoHS no Sb Br CU NIPDAU Level 3 260C 168 HR 40 to 105 M430F235T MSP430F2410TPM ACTIVE LQFP PM 64 160 Green RoHS no Sb Br NIPDAU CU NIPDAU Level 3 260C 168 HR 40 to 105 M430F2410T REV MSP430F2410TP...

Page 82: ...68 HR 40 to 105 M430F2481T REV MSP430F2481TRGC OBSOLETE VQFN RGC 64 TBD Call TI Call TI 40 to 105 MSP430F2481TRGCR ACTIVE VQFN RGC 64 2500 Green RoHS no Sb Br CU NIPDAU Level 3 260C 168 HR 40 to 105 M430F2481T MSP430F2481TRGCT ACTIVE VQFN RGC 64 250 Green RoHS no Sb Br CU NIPDAU Level 3 260C 168 HR 40 to 105 M430F2481T MSP430F248TPM ACTIVE LQFP PM 64 160 Green RoHS no Sb Br NIPDAU CU NIPDAU Level ...

Page 83: ... information and additional product content details TBD The Pb Free Green conversion plan has not been defined Pb Free RoHS TI s terms Lead Free or Pb Free mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances including the requirement that lead not exceed 0 1 by weight in homogeneous materials Where designed to be soldered at high temperatures TI ...

Page 84: ...sonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals TI and TI suppliers consider certain information to be proprietary and thus CAS numbers and other limited information may not be available for release In no event shall TI s liability arising out of such information exceed the tota...

Page 85: ...16 0 24 0 Q2 MSP430F2471TRGCT VQFN RGC 64 250 180 0 16 4 9 3 9 3 1 5 12 0 16 0 Q2 MSP430F247TPMR LQFP PM 64 1000 330 0 24 4 13 0 13 0 2 1 16 0 24 0 Q2 MSP430F247TPMR LQFP PM 64 1000 330 0 24 4 13 0 13 0 2 1 16 0 24 0 Q2 MSP430F2481TPMR LQFP PM 64 1000 330 0 24 4 13 0 13 0 2 1 16 0 24 0 Q2 MSP430F248TPMR LQFP PM 64 1000 330 0 24 4 13 0 13 0 2 1 16 0 24 0 Q2 MSP430F2491TPMR LQFP PM 64 1000 330 0 24 ...

Page 86: ... 336 6 336 6 41 3 MSP430F2471TRGCT VQFN RGC 64 250 210 0 185 0 35 0 MSP430F247TPMR LQFP PM 64 1000 336 6 336 6 41 3 MSP430F247TPMR LQFP PM 64 1000 367 0 367 0 45 0 MSP430F2481TPMR LQFP PM 64 1000 336 6 336 6 41 3 MSP430F248TPMR LQFP PM 64 1000 336 6 336 6 41 3 MSP430F2491TPMR LQFP PM 64 1000 367 0 367 0 45 0 MSP430F2491TPMR LQFP PM 64 1000 336 6 336 6 41 3 MSP430F249TPMR LQFP PM 64 1000 367 0 367 ...

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Page 90: ...13 NOM 0 25 0 45 0 75 Seating Plane 0 05 MIN Gage Plane 0 27 33 16 48 1 0 17 49 64 SQ SQ 10 20 11 80 12 20 9 80 7 50 TYP 1 60 MAX 1 45 1 35 0 08 0 50 M 0 08 0 7 NOTES A All linear dimensions are in millimeters B This drawing is subject to change without notice C Falls within JEDEC MS 026 D May also be thermally enhanced plastic with leads connected to the die pads ...

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Page 92: ...esponsible for compliance with all legal regulatory and safety related requirements concerning its products and any use of TI components in its applications notwithstanding any applications related information or support that may be provided by TI Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which anticipate dangerous consequences of failur...

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