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Texas Instruments MSC1210, User Manual

The Texas Instruments MSC1210 is a versatile and high-performance device. To ensure seamless operation and optimal utilization, we have provided a comprehensive User Manual. Detailed instructions, troubleshooting guides, and valuable insights are available for free download at manualshive.com. Unlock the full potential of your MSC1210 with our user-friendly manual.

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Bit Addressable SFRs (alphabetical)

F-9

Bit-Addressable SFRs (alphabetical)

Timer Control (TCON)

SFR Name:

TCON

SFR Address:

88

H

Bit−Addressable: Yes

Bit−Definitions:

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

Name

TF1

TR1

TF0

TR0

IE1

IT1

IE0

IT0

Bit Address

8FH

8EH

8DH

8CH

8BH

8AH

89H

88H

TF1—Timer 1 Overflow Flag. This bit is set by the MCU when Timer 1
overflows from FFFF

H

 back to 0000

H

. Cleared by software, or cleared

automatically by hardware if a Timer 1 interrupt is triggered.

TR1—Timer 1 Run Control. When this bit is set, Timer 1 counts depending
on its configuration in TMOD. When this bit is clear, Timer 1 is stopped.

TF0—Timer 0 Overflow Flag.  This bit is set by the MCU when Timer 0
overflows from FFFF

H

 back to 0000

H

. Cleared by software, or cleared

automatically by hardware if a Timer 0 interrupt is triggered.

TR0—Timer 1 Run Control. When this bit is set, Timer 0 counts depending
on its configuration in TMOD. When this bit is clear, Timer 0 is stopped.

IE1—External 1 Interrupt Flag. This bit is set by the MCU when an external
1 interrupt is detected on the INT1 line. Cleared by software, or cleared auto-
matically by hardware if an external 1 interrupt is triggered.

IT1—External 1 Interrupt Type Flag. This bit controls whether or not external
1 interrupt is edge-triggered or low-level-triggered. If this bit is set, external 1
interrupt is triggered when a 1-0 transition is detected on the INT1 line. If this
bit is clear, external 1 interrupt is triggered continuously when INT1 is at a low
state.

IE0—External 0 Interrupt Flag. This bit is set by the MCU when an external
0 interrupt is detected on the INT0 line. Cleared by software, or cleared auto-
matically by hardware if an external 1 interrupt is triggered.

IT0—External 0 Interrupt Type Flag. This bit controls whether or not external
0 interrupt is edge-triggered or low-level-triggered. If this bit is set, external 1
interrupt is triggered when a 1-0 transition is detected on the INT0 line. If this
bit is clear, external 0 interrupt is triggered continuously when INT0 is at a low
state.

Summary of Contents for MSC1210

Page 1: ... December 2002 User s Guide SBAU077 ...

Page 2: ...nt that any license either express or implied is granted under any TI patent right copyright mask work right or other TI intellectual property right relating to any combination machine or process in which TI products or services are used Information published by TI regarding third party products or services does not constitute a license from TI to use such products or services or a warranty or end...

Page 3: ... Organization 2 1 2 1 Description 2 2 2 2 Program Memory 2 2 2 3 Data Memory 2 4 2 3 1 On Chip Extended Static RAM SRAM 2 4 2 3 2 On Chip Flash Data Memory 2 5 2 3 3 External Data Memory 2 5 2 4 Internal RAM 2 6 2 4 1 The Stack 2 7 2 4 2 Register Banks 2 7 2 4 3 Bit Memory 2 8 2 4 4 Special Function Register SFR Memory 2 10 3 Special Function Registers SFRs 3 1 3 1 Description 3 2 3 2 Referencing ...

Page 4: ...on 8 2 8 2 How Does a Timer Count 8 2 8 3 Using Timers to Measure Time 8 2 8 3 1 How Long Does a Timer Take to Count 8 2 8 3 2 Timer SFRs 8 4 8 3 3 TMOD SFR 8 5 8 3 4 TCON SFR 8 8 8 3 5 Initializing a Timer 8 9 8 3 6 Reading the Timer 8 9 8 3 7 Timing the Length of Events 8 11 8 4 Using Timers as Event Counters 8 12 8 5 Using Timer 2 8 13 8 5 1 T2CON SFR 8 13 8 5 2 Timer 2 in Auto Reload Mode 8 14...

Page 5: ...nerator 11 5 11 3 1 Example of PWM Tone Generation 11 8 11 3 2 Example of PWM Tone Generation Idling 11 9 11 3 3 Example of Updating PWM 11 11 12 Analog to Digital Converter 12 1 12 1 Description 12 2 12 2 Input Multiplexer 12 3 12 3 Temperature Sensor 12 5 12 4 Burnout Current Sources 12 7 12 5 Input Buffer 12 8 12 6 Analog Input 12 8 12 7 Programmable Gain Amplifier PGA 12 9 12 8 Offset DAC 12 1...

Page 6: ... 14 3 3 Resetting the Watchdog Timer 14 7 14 3 4 Disabling Watchdog Timer 14 8 14 3 5 Watchdog Timeout Activation 14 8 15 Advanced Topics 15 1 15 1 Hardware Configuration 15 2 15 1 1 Hardware Configuration Registers 15 2 15 1 2 Hardware Configuration Memory 15 5 15 1 3 Accessing Configuration Memory in a User Program 15 5 15 2 Advanced Flash Memory 15 6 15 2 1 Write Protecting Flash Program Memory...

Page 7: ...ng Register Values XCH 16 26 16 24 Swapping Accumulator Nibbles SWAP 16 26 16 25 Exchanging Nibbles Between Accumulator and Internal RAM XCHD 16 26 16 26 Adjusting Accumulator for BCD Addition DA 16 27 16 27 Using the Stack PUSH POP 16 28 16 28 Setting the Data Pointer DPTR MOV DPTR 16 30 16 29 Reading and Writing External RAM Data Memory MOVX 16 31 16 30 Reading Code Memory Tables MOVC 16 32 16 3...

Page 8: ...Routines C 1 C 1 Description C 2 C 1 1 Note Regarding the put_string Function C 3 D 8052 Instruction Set Quick Reference Guide D 1 D 1 8052 Instruction Set Quick Reference Guide D 2 E 8052 Instruction Set E 1 E 1 Description E 2 E 2 8052 Instruction Set E 3 F Bit Addressable SFRs alphabetical F 1 F 1 Bit Addressable SFRs alphabetical F 2 G SFRs Address Cross Reference Guide alphabetical G 1 G 1 SF...

Page 9: ... 1 Transmit Timing 9 7 9 4 Serial Port 0 Mode 1 Receive Timing 9 7 9 5 Serial Port 0 Mode 2 Transmit Timing 9 9 9 6 Serial Port 0 Mode 2 Receive Timing 9 10 9 7 Serial Port 0 Mode 3 Transmit Timing 9 11 9 8 Serial Port 0 Mode 3 Receive Timing 9 11 11 1 Block Diagram 11 2 11 2 Tone Generator Circuit 11 3 11 3 Timing Diagram of Tone Generator in Staircase Mode 11 4 11 4 Timing Diagram of Tone Genera...

Page 10: ...Message 17 19 17 10 Accumulator Shifter Peripheral 17 20 17 11 summation Shifter Peripheral 17 28 17 12 The ADC Peripheral Mid Stride a Typical 8 Sample Averaging Block 17 28 17 13 List Box for the Interrupt Peripheral 17 30 17 14 Parallel Port 0 Contents Display Window 17 31 17 15 Error Message 17 31 17 16 SPI Peripheral Window 17 32 17 17 Keil Debugger 17 39 17 18 Serial Channel 0 Communication ...

Page 11: ... Baud Rate Settings for Timer 2 9 15 10 1 Interrupt Sources 10 3 10 2 IE A8h SFR 10 5 10 3 EICON D8h SFR 10 5 10 4 EIE E8h SFR 10 5 10 5 IP B8h SFR 10 7 10 6 EIP F8h SFR 10 7 10 7 EXIF 91h SFR 10 10 10 8 Clearing Auxiliary Interrupts 10 12 10 9 AIE A6h SFR 10 12 10 10 AISTAT A7h SFR 10 13 10 11 PAI A5h SFR 10 13 10 12 PPI Bits of PAI SFR 10 14 10 13 EWU C6h SFR 10 15 11 1 PWM Polarity Conditions 1...

Page 12: ...4 2 Comparator Specification 14 3 14 3 Band Gap Parameters 14 3 16 1 Order of Precedence for Mathematical Operators 16 5 16 2 Results of ANL 16 24 16 3 Results of ORL 16 24 16 4 Results of XRL 16 24 17 1 Timer Counter 2 Control Bits 17 11 C 1 Boot ROM Routines C 2 ...

Page 13: ...f the MSC1210 analog to digital converter ADC Topic Page 1 1 MSC1210 Description 1 2 1 2 MSC1210 Pin Out 1 3 1 3 Enhanced 8051 Core 1 12 1 4 Family Device Compatibility 1 13 1 5 Flash Memory 1 13 1 6 High Performance Analog 1 13 1 7 High Performance Peripherals 1 14 Chapter 1 ...

Page 14: ...ability but also in tegrates high performance peripherals to offer a unique system solution The main components of a MicroSystem product include Enhanced 8051 microcontroller core FLASH memory High performance analog functions High performance peripherals The enhanced 8052 microcontroller core includes dual data pointers and exe cutes instructions three times faster than the standard 8052 core Thi...

Page 15: ...atures greatly simplify achieving high end analog performance The on chip high performance peripherals not only reduce the cost design time and board space required for external circuitry but also blend analog and digital functions that simplify the system design The high performance periph erals are designed from a system perspective thereby decreasing the proc essing requirements on the CPU and ...

Page 16: ...rrupt 1 TONE PWM Out put P3 4 T0 Timer 0 External Input P3 5 T1 Timer 1 External Input P3 6 WR External Data Memory Write Strobe P3 7 RD External Data Memory Read Strobe 11 14 15 42 58 DVDD Digital Power Supply 12 41 57 DGND Digital Ground 13 RST A HIGH on the reset input for two instruction clock cycles will reset the device 16 32 33 NC No Connection 17 27 AGND Analog Ground 28 AVDD Analog Power ...

Page 17: ...Oscillator clock Modulator clock HIGH or LOW ALE PSEN Program Mode Selection NC NC Normal Operation 0 1 Parallel Programming 1 0 Serial Programming 0 0 Reserved 45 ALE Address Latch Enable Used for latching the low byte of the address during an access to external memory ALE is emitted at a constant rate of 1 2 the oscillator frequency and can be used for external timing or clocking One ALE pulse i...

Page 18: ...corre sponding bits of the SFRs All of the ports have optional pull up resistors that are enabled when the port is in 8051 mode as configured by the PxDDRL H SFRs The pull up resistors are disabled when the port is configured in any other mode or when accessing external memory 1 2 1 1 Port 0 Port 0 is dual function in some designs port 0 I O lines are available to the de veloper to access external...

Page 19: ...g to be set which may cause an interrupt if so enabled P1 2 RxD1 If the secondary USART is being used P1 2 RxD1 is the pin that receives serial data Data received via this pin is read using the SBUF1 SFR P1 3 TxD1 If the secondary USART is being used P1 3 TxD1 is the pin that transmits serial data Data written to the SBUF1 SFR is sent via this pin P1 4 INT2 SS This pin has two dual functions It ma...

Page 20: ...of dual function I O lines While you can access all these lines from the software by reading writing to the P3 SFR each pin has a predefined function that the microcontroller handles automatically when con figured to do so and or when necessary P3 0 RxD0 The primary USART serial port uses P3 0 as the receive line For in circuit designs that are using the microcontroller internal serial port this i...

Page 21: ...0 transition on this line depending on how the timer is configured see Chapter 8 Timers for details You can assign any function to this pin as long as the circuit has no need to control timer 1 externally P3 6 WR This is the external memory write strobe line when bit EGP23 is set in hardware configuration Register 1 This line is asserted low by the micro controller whenever a MOVX instruction writ...

Page 22: ...e low byte of the address into a latch IC such as the 74HC573 and then placing the 8 data bits on port 0 In this way the MSC1210 is able to output a 16 bit address and an 8 bit data word with 16 I O lines instead of 24 The ALE line is used in this fashion both to access external RAM with MOVX DPTR as well as to accessi instructions in external code memory When the pro gram is executed from externa...

Page 23: ...llel flash programming modes Note Even when EA is tied high indicating that the microcontroller should execute from internal code memory the microcontroller will attempt to execute from external code memory if the program counter references an address not available for the chip you are using or if you are accessing program memory in excess of the amount of flash memory that you have partitioned fo...

Page 24: ... clock cycles per instruction as shown in Figure 1 3 This allows you to run the de vice at slower external clock speeds which reduces system noise and power consumption but provides greater throughput Figure 1 3 MSC1210 Timing Compared to Standard 8051 Timing The timing of software loops is faster with the MSC1210 than with the standard 8052 However the timer counter operation of the MSC1210 may b...

Page 25: ...program and non volatile data memory maps to meet the needs of the application The flash memory is programmable over the entire operating voltage range and temperature range using both serial and parallel program ming methods 1 6 High Performance Analog Functions The analog functionality is state of the art The ADC is extremely low noise which enables you to meet even the most stringent analog req...

Page 26: ...gurable I O a 16 bit pulse width modulator PWM a watchdog timer and three timer counters For instance the SPI interface uses a FIFO buffer which allows for the serial transmission and reception of data with virtually no CPU overhead The FIFO buffer function allows for the transfer of large amounts of data at faster transfer rates than more conventional methods Additionally the 32 bit accumulator s...

Page 27: ...2 1 MSC1210 Memory Organization This chapter defines the Memory Organization of MSC1210 ADC Topic Page 2 1 Description 2 2 2 2 Program Memory 2 2 2 3 Data Memory 2 4 2 4 Internal RAM 2 6 Chapter 2 ...

Page 28: ... types of data memory J On chip extended SRAM J Off chip external SRAM J On chip Flash Data memory J Internal RAM 2 2 Program Memory Program memory holds the actual program that is to be run This memory in cludes the on chip flash memory designated as program memory and or ex ternal memory The MSC1210 family offers a maximum of 32k of on chip flash program memory The exact amount of on chip progra...

Page 29: ...ed program execution is external For example setting the DFSEL bits to 110 with a MSC1210Y5 would cause 31kb of on chip flash memory to be partitioned as program memory and 1kb of flash memory to be partitioned as data memory Table 2 2 indicates where the assigned memory will be located in address space This table provides essentially the same information as Table 2 1 but also indicates where the ...

Page 30: ...al compilers and hardware pro grams are limited to 64k The MSC1210 includes 2k of boot ROM code that controls operation during serial or parallel programming In program mode the boot ROM is located in the first 2kB of program memory The boot ROM is available to your program as long as EBR hardware configu ration register 0 bit 4 is set which is the default When enabled the boot ROM routines will b...

Page 31: ... through 0BFFH will access on chip flash data memory Any attempts to read data memory with addresses 0C00H and higher will result in the part attempting to fetch that data off chip from external data memory see the next section except when the internal 1kB SRAM is configured as Von Neu mann type which occupies from 8400H 87FFH 2 3 3 External Data Memory The MSC1210 is capable of addressing up to 6...

Page 32: ...t to know that they reside in and are part of inter nal RAM Bit memory also resides in and is part of internal RAM Bit memory will be de scribed more in section 2 4 3 but for now just keep in mind that bit memory actually resides in internal RAM at addresses 20H through 2FH The 208 bytes remaining of internal RAM from addresses 30H through FFH may be used by user variables that need to be accessed...

Page 33: ...ve the highest register bank being used Otherwise the stack will overwrite the alternate register banks Similarly if using bit variables it is usually a good idea to initialize the stack pointer to some value greater than 2FH to ensure that the bit variables are protected from the stack Following is more information about the register banks and bit memory 2 4 2 Register Banks The MSC1210 uses eigh...

Page 34: ... program for its own use If register banks 1 2 or 3 are to be used be very careful about using addresses below 20H to avoid overwriting the value of R registers from other register banks 2 4 3 Bit Memory The MSC1210 being a communications and control oriented microcontroller that often has to deal with on and off situations gives you the ability to access a number of bit variables directly with si...

Page 35: ...being used Otherwise the stack will overwrite the alternate register banks Similarly if using bit variables it is usually a good idea to initialize SP to some value greater than 2FH to ensure that the bit variables are protected from the stack Bit memory 00H through 7FH is for user defined functions in their programs Bit memory 80H and above are used to access certain SFRs see section 2 4 4 on a b...

Page 36: ...xecute the instruction MOV 99h 01h As shown it appears as if the SFR is part of internal memory This is not the case When using this method of memory access it is called direct address ing more on that soon any instruction that has an address of 00H through 7FH refers to an internal RAM memory address any instruction with an ad dress of 80H through FFH refers to an SFR control register Note SFRs a...

Page 37: ... Special Function Registers SFRs Chapter 3 defines the MSC1210 SFRs Topic Page 3 1 Description 3 2 3 2 Referencing SFRs 3 3 3 3 Bit Addressable SFRs 3 4 3 4 SFR Types 3 4 3 5 SFR Definitions 3 5 Chapter 3 ...

Page 38: ...there are 24 addresses that are not assigned to an SFR as shown in Table 3 1 Note Reading an unassigned SFR will get 00H and writing to an unassigned SFR is ignored Table 3 1 SFR Names and Addresses 80 P0 SP DPL0 DPH0 DPL1 DPH1 DPS PCON 87 88 TCON TMOD TL0 TL1 TH0 TH1 CKCON MWS 8F 90 P1 EXIF MPAGE CADDR CDATA MCON 97 98 SCON0 SBUF0 SPICON SPIDATA SPIRCON SPITCON SPISTART SPIEND 9F A0 P2 PWMCON PWM...

Page 39: ...us the SBUF0 SFR is being accessed The assembler will automatically convert this to its numeric address at assemble time Note Many of the SFRs that the MSC1210 uses are MSC1210 specific only 26 are recognized by the original 8052 It is usually necessary to include a head er file or an include file in your program to define the additional SFRs sup ported by the MSC1210 Failing to do so may result i...

Page 40: ...the SFRs are related to the I O ports The MSC1210 has four I O ports of eight bits for a total of 32 I O lines Whether a given I O line is high or low and the value read from the line is controlled by these SFRs Refer to Section 15 1 for the detailed control of the port usages SFRs control the operation or the configuration of the MSC1210 For example TCON controls the timers and SCON controls the ...

Page 41: ...tailed control of the port usages Thus if external RAM or code memory is being used only ports P1 and P3 except P3 6 and P3 7 may be used by the application SP Stack Pointer Address 81H This is the stack pointer of the microcontroller This SFR indicates where the next value to be taken from the stack will be read from Internal RAM If a value is pushed onto the stack the value will be written to th...

Page 42: ...ce of two distinct data point ers allows a program to quickly copy data from one area of memory to another DPS Data Pointer Select Address 86H Bit 0 of this SFR determines whether instructions that refer to DPTR will use Data Pointer 0 or Data Pointer 1 If bit 0 is clear Data Pointer 0 will be used DPH0 DPL0 If bit 1 is set Data Pointer 1 will be used DPH1 DPL1 PCON Power Control Address 87H This ...

Page 43: ...ystal frequency such that the clocks will be incremented once every in struction cycle Additionally the CKCON SFR allows you to modify how long the MSC1210 takes to access external data memory MWS Memory Write Select Address 8FH This SFR contains a single bit bit 0 that enables writing to program flash memory If this bit is clear MOVX DPTR or MOVX Ri write to data flash memory or data SRAM memory ...

Page 44: ... behavior of the MSC1210 primary onboard serial port This SFR controls the baud rate of the serial port whether the serial port is acti vated to receive data and also contains flags that are set when a byte is suc cessfully sent or received Note To use the MSC1210 onboard serial port it is generally necessary to initialize the following SFRs SCON0 TCON and TMOD This is because SCON0 controls the s...

Page 45: ...FR will set a high level on the corresponding I O pin whereas a value of 0 will bring it to a low level Note Even though the MSC1210 has four I O ports P0 P1 P2 and P3 if the hardware uses external RAM or external code memory i e the program is stored in an external ROM or EPROM chip or if external RAM chips are being used P0 P2 P3 6 or P3 7 may not used This is because the MSC1210 uses ports P0 a...

Page 46: ... These two SFRs together configure the state of each port 1 pin standard 8051 pull up CMOS output open drain output or input P3 Port 3 Address B0H Bit Addressable This is input output port 3 Each bit of this SFR corresponds to one of the pins on the microcontroller For exam ple bit 0 of port 3 is pin P3 0 bit 7 is pin P3 7 Writing a value of 1 to a bit of this SFR will set a high level on the corr...

Page 47: ...rry flag the over flow flag and the parity flag Additionally the PSW SFR contains the register bank select flags that are used to select which of the R register banks are cur rently selected Note When writing an interrupt handler routine it is a very good idea to always save the PSW SFR on the stack and restore it when the interrupt is complete Many instructions modify the bits of the PSW If the i...

Page 48: ...byte SUMR0 will cause the values in the other three summation registers to be added to the summation result ODAC Offset DAC Register Address E6H This SFR allows the MSC1210 to shift the input by up to half of the ADC input range LVDCON Low Voltage Detection Control Address E7H The LVDCON SFR configures the low voltage detection on both the analog and digital sup plies In both cases the LVDCON allo...

Page 49: ...anner PSEN and ALE may be used as two additional output lines if they are not needed for their normal functions Note When these two lines are used as output lines they should only drive light capacitive loads to avoid triggering serial or parallel flash programming modes ACLK Analog Clock Address F6H This SFR is used to determine the ana log clock for the ADC The value of ACLK plus 1 multiplied by...

Page 50: ...flash write operations MSECL MSECH Millisecond Low High Registers Addresses FCH FDH These two SFRs together are used by the system to determine how long a millisecond is This value is used for erasing flash memory millisecond interrupt second interrupt and watchdog time Although it is named Millisecond Low High the clock speed and the value placed in these registers will determine the exact length...

Page 51: ...ibes the basic register functions of the MSC1210 ADC Topic Page 4 1 Description 4 2 4 2 Accumulator 4 2 4 3 R Registers 4 2 4 4 B Register 4 3 4 5 Program Counter PC 4 3 4 6 Data Pointer DPTR0 DPTR1 4 4 4 7 Stack Pointer SP 4 4 Chapter 4 ...

Page 52: ...re named R0 through R7 These registers are used as auxiliary registers in many operations To contin ue with the previous example of adding 10 and 20 the original number 10 may be stored in the accumulator whereas the value 20 may be stored in say reg ister R4 To process the addition the following command would be executed ADD A R4 After executing this instruction the accumulator will contain the v...

Page 53: ...sense that it may hold an 8 bit 1 byte value The B register is only used by two MSC1210 instructions MUL AB and DIV AB Therefore to quickly and easily multiply or divide A by another number the oth er number may be stored in B Aside from the MUL and DIV instructions the B register is often used as anoth er temporary storage register much like a 9th R register 4 5 Program Counter PC The program cou...

Page 54: ...nter SP like all registers except DPTR and PC may hold an 8 bit 1 byte value The SP is used to indicate where the next value to be re moved from the stack should be taken from When a value is pushed onto the stack the MSC1210 first increments the val ue of the SP and then stores the value at the resulting memory location When a value is popped off the stack the MSC1210 returns the value from the m...

Page 55: ...s the various addressing modes of the MSC1210 Topic Page 5 1 Description 5 2 5 2 Immediate Addressing 5 2 5 3 Direct Addressing 5 3 5 4 Indirect Addressing 5 4 5 5 External Direct 5 5 5 6 External Indirect 5 6 5 7 Code Indirect 5 6 Chapter 5 ...

Page 56: ... A DPTR Each of these addressing modes provides important flexibility to the programmer 5 2 Immediate Addressing Immediate addressing is so named because the value to be stored in memory immediately follows the opcode in memory That is to say the instruction itself dictates what value will be stored in memory For example MOV A 20h This instruction uses immediate addressing because the accumulator ...

Page 57: ...er is found at the given address which may change Additionally it is important to note that when using direct addressing any in struction that refers to an address between 00H and 7FH is referring to internal RAM Any instruction that refers to an address between 80H and FFH is refer ring to the SFR control registers that control the MSC1210 itself The obvious question that may arise is if direct a...

Page 58: ...e value 67H When the above instruction is executed the 8052 checks the value of R0 The MSC1210 gets the value out of internal RAM address 40H which holds 67H and stores it in the accumulator because R0 holds 40H Thus the accumulator ends up holding 67H Indirect addressing always refers to internal RAM it never refers to an SFR In a prior example it was mentioned that SFR 99H can be used to write a...

Page 59: ...mory address the first com mand moves the contents of that external memory address into the accumula tor For example if you want to read the contents of external RAM address 1516H execute the instructions MOV DPTR 1516h Select the external address to read MOVX A DPTR Move the contents of external RAM into accumulator The second command does the opposite it allows you to write the value of the accu...

Page 60: ...st addressing mode is called code indirect and offers two additional 8052 instructions that allow you to access the program code itself This is useful for accessing data tables strings etc The two instructions are MOVC A A DPTR MOVC A A PC For example if you want to access the data stored in code memory at address 2021H execute the instructions MOV DPTR 2021h Set DPTR to 2021h CLRA Clear the accum...

Page 61: ... Chapter 6 describes the program flow of the MSC1210 ADC Topic Page 6 1 Description 6 2 6 2 Conditional Branching 6 2 6 3 Direct Jumps 6 2 6 4 Direct Calls 6 4 6 5 Returns From Routines 6 4 6 6 Interrupts 6 4 Chapter 6 ...

Page 62: ...O skipping the NOP instruction If the bit is not set the conditional branch fails and program execu tion continues as usual with the NOP instruction that follows Conditional branching is really the fundamental building block of program logic because all decisions are accomplished by using conditional branching Con ditional branching can be thought of as the IF THEN structure of assembly language N...

Page 63: ...he SJMP command like the conditional branching instructions can only jump to an address within 128 127 bytes of the address following the SJMP command The AJMP command can only jump to an address that is in the same 2k block of memory as the byte following the AJMP command That is to say if the AJMP command is at code memory location 650H it can only do a jump to ad dresses 0000H through 07FFH 0 t...

Page 64: ...ndition but is variable in the sense that where program flow continues can be different each time the RET instruction is executed de pending on where the subroutine was originally called from 6 6 Interrupts An interrupt is a special feature that allows the MSC1210 to break from its nor mal program flow to execute an immediate task providing the illusion of multi tasking The word interrupt can ofte...

Page 65: ...7 1 System Timing Chapter 7 describes the system timing of the MSC1210 ADC Topic Page 7 1 Description 7 2 7 2 System Timers 7 4 7 3 Startup Timing 7 9 Chapter 7 ...

Page 66: ...eration The MSC1210 operates using what are called instruction cycles A single instruction cycle is the minimum amount of time in which a single MSC1210 instruction can be executed al though many instructions take multiple cycles Note A standard 8052 executes an instruction in 12 clock cycles rather than 4 as shown in Figure 7 1 This means that with no program changes an MSC1210 will execute code ...

Page 67: ...ute 8 250 000 single cycle instructions per second It is important to emphasize that not all instructions execute in the same amount of time The fastest instructions require one instruction cycle four clock cycles many others require two instruction cycles eight clock cycles and the two slow math operations require four instruction cycles 16 clock cycles Due to all the instructions requiring diffe...

Page 68: ...d MSECL FCH SFRs and is used as a base to configure the flash erase timing as well as the millisec onds interrupt and also as a base for the seconds interrupt and the watchdog timer The MSC1210 timers are illustrated in Figure 7 2 The SYS Clock is the signal that comes from the oscillator or other timing input This signal is used as the input for all of the part s timing logic including the follow...

Page 69: ...System Timers 7 5 System Timing Figure 7 2 MSC1210 Timing Chain and Clock Control Figure 7 3 SPI PWM Flash Write Timing ...

Page 70: ...the PWM module as suming the microseconds timer is correctly configured to produce a 1µs clock In this case the microseconds clock is further divided by the value contained in the PWMHI PWMLOW SFRs 7 2 1 2 Flash Write Timing The microseconds clock is further used to establish the flash memory write timing The flash write timing uses the microsecond clock as an input clock and then fur ther divides...

Page 71: ...y setting EMSEC AIE 4 and enabling auxiliary interrupts via the EAI EICON 5 bit The frequency at which the milliseconds interrupt will be triggered is controlled by the value written to the MSINT FAH SFR When enabled a millisecond auxiliary interrupt will be triggered after MSINT 1ms assuming that MSECH MSECL have been configured to produce a correct milliseconds clock The value written to the MSI...

Page 72: ...pt will be triggered is controlled by the value written to the SECINT F9H SFR When enabled a seconds auxiliary interrupt will be triggered after SECINT 100ms assuming the MSECH MSECL and HMSEC SFRs have been configured to produce a correct 100ms clock The value written to the SECINT SFR is between 0 and 127 meaning that the milliseconds interrupt may be triggered every 100ms to 12 8 seconds assumi...

Page 73: ...S 10 6 0 131071s 7 3 1 Normal Mode Power On Reset Timing EA is sampled during power on reset for code security purposes PSEN and ALE are internally pulled up during reset for serial and parallel flash program ming mode detection After the reset sequence PSEN and ALE signals are driven by the CPU and the internal pull up resistors are removed for saving power 7 3 2 Flash Programming Mode Power On R...

Page 74: ...ming Diagrams Symbol Parameter Min Max Unit trw RST Width 10 tCLK 1 ns trrd RST rise to PSEN ALE internal pull high 5 µs trfd RST falling to PSEN and ALE start 217 512 tCLK 1 ns trs Input signal to RST falling setup time tCLK 1 ns trh RST falling to input signal hold time 217 512 tCLK 1 ns Notes 1 tCLK is the Xtal clock period ...

Page 75: ...ter 8 describes the timers of the MSC1210 ADC Topic Page 8 1 Description 8 2 8 2 How Does a Timer Count 8 2 8 3 Using Timers to Measure Time 8 2 8 4 Using Timers as Event Counters 8 12 8 5 Using Timer 2 8 13 Chapter 8 ...

Page 76: ...scuss this use of timers first and will subsequently discuss the use of timers to count events When a timer is used to measure time it is also called an interval timer because it is measuring the time of the interval between two events 8 3 1 How Long Does a Timer Take to Count Before continuing it is worth mentioning that when a timer is in interval timer mode as opposed to event counter mode and ...

Page 77: ...lock that drives Timer 0 Clearing this bit to 0 maintains 8051 compatibility This bit has no effect on instruction cycle timing 0 Timer 0 uses a divide by 12 of the crystal frequency 1 Timer 0 uses a divide by 4 of the crystal frequency MD2 MD1 MD0 bits 2 0 Stretch MOVX Select 2 0 These bits select the time by which external MOVX cycles are to be stretched This allows slower memory or peripherals ...

Page 78: ...he timers and each timer also has two SFRs dedicated solely to maintaining the value of the timer itself TH0 TL0 and TH1 TL1 The third timer Timer 2 functions somewhat differently and will be explained separately The SFRs used to control and manipulate the first two timers are presented in the Table 8 1 Table 8 1 Timer Conrol SFRs SFR Name Description SFR Address Bit Addressable TH0 Timer 0 high b...

Page 79: ...NT1 1 Timer 1 will clock only when TR1 1 and pin INT1 1 C T bit 6 Timer 1 Counter Timer Select 0 Timer is incremented by internal clocks 1 Timer is incremented by pulses on pin T1 when TR1 TCON 6 SFR 88H is 1 M1 M0 bits 5 4 Timer 1 Mode Select These bits select the operating mode of Timer 1 M1 M0 Mode 0 0 Mode 0 8 bit counter with 5 bit prescale 0 1 Mode 1 16 bits 1 0 Mode 2 8 bit counter with aut...

Page 80: ...for pulse width mea surements The TMOD CT bit selects counter or timer operation If TMOD CT is cleared the timer counter register is incremented on either fosc 4 or fosc 12 based on the state of CKCON TxM If TMOD CT is set the timer counter register is in cremented by the Tx pin 8 3 3 1 13 Bit Time Mode mode 0 Timer mode 0 is a 13 bit timer This is a relic that was kept around in the 8052 and subs...

Page 81: ...FH the timer counter interrupt flag is set TCON TFx Timer mode 1 is a 16 bit timer This is a very commonly used mode It functions just like 13 bit mode except that all 16 bits are used TLx is incremented from 0 to 255 When TLx is incremented from 255 it resets to 0 and causes THx to be incremented by 1 The timer may contain up to 65 536 distinct values because this is a full 16 bit timer If a 16 b...

Page 82: ... 0 to 255 and overflow back to 0 All the bits that are related to Timer 1 will now be tied to TH0 and all the bits related to Timer 0 will be tied to TL0 While Timer 0 is in split mode the real Timer 1 i e TH1 and TL1 can be put into modes 0 1 or 2 normally However the real Timer 1 may not be started or stopped because the bits that do that are now linked to TH0 The real Timer 1 in this case will ...

Page 83: ...used that is to say it is not dependent on any external pins We must first initialize the TMOD SFR When working with Timer 0 the low four bits of TMOD will be used The first two bits GATE0 and CT0 are both 0 be cause the timer needs to be independent of the external pins 16 bit mode is timer mode 1 so T0M1 must be cleared and T0M0 must be set Effectively bit 0 of TMOD is the only bit that should b...

Page 84: ...t of Timer 0 which is now stored in the accumulator is checked to see if it is the same as the current Timer 0 high byte If it is not that means it just rolled over and the timer value must be reread which is done by going back to REPEAT When the loop exits the low byte of the timer is in R0 and the high byte is in the accu mulator Another much simpler alternative is to simply turn off the timer r...

Page 85: ...t overflowed and the TF0 bit has not been set the program will keep executing this same instruction After 1 20th of a second Timer 0 overflows sets the TF0 bit and program execution then breaks out of the loop 8 3 7 Timing the Length of Events The MSC1210 provides another useful method to time the length of events For example in order to save electricity in the office a light switch is measured to...

Page 86: ...re the program checks the line status this would result in the car not being counted Of course there are ways to get around even this limitation but the code quickly becomes big complex and ugly Luckily the MSC1210 provides a way to use the timers to count events It is painfully easy Only one additional bit has to be configured Timer 0 can be used to count the number of cars that pass In the bit t...

Page 87: ...leared by software TF2 will only be set if RCLK and TCLK are both cleared to 0 Writing a 1 to TF2 forces a Timer 2 interrupt if enabled EXF2 bit 6 Timer 2 External Flag A negative transition on the T2EX pin P1 1 will cause this flag to be set based on the EXEN2 T2CON 3 bit If set by a negative transition this flag must be cleared to 0 by software Setting this bit in software will force a timer int...

Page 88: ... Timer 2 in Auto Reload Mode The first mode in which Timer 2 may be used is auto reload The auto reload mode functions just like Timer 0 and Timer 1 in auto reload mode except that the Timer 2 auto reload mode performs a full 16 bit reload recall that Timer 0 and Timer 1 only have 8 bit reload values When a reload occurs the value of TH2 is reloaded with the value contained in RCAP2H and the value...

Page 89: ...s set which triggers an inter rupt if Timer 2 interrupt is enabled Note Even in capture mode an overflow of Timer 2 results in TF2 being set and an interrupt being triggered Note Capture mode is an efficient way to measure the time between events At the moment that an event occurs the current value of Timer 2 is copied into RCAP2H L However Timer 2 will not stop and an interrupt will be triggered ...

Page 90: ...or example if RCLK is set and TCLK is cleared seri al data is received at the baud rate determined by Timer 2 whereas the baud rate of transmitted data is determined by Timer 1 Determining the auto reload values for a specific baud rate is discussed in Chapter 9 Serial Communication The only difference is that in the case of Timer 2 the auto reload value is placed in RCAP2H and RCAP2L and the val ...

Page 91: ...cribes serial communication using the MSC1210 ADC Topic Page 9 1 Description 9 2 9 2 Setting the Serial Port Mode 9 3 9 3 Setting the Serial Port Baud Rate 9 13 9 4 Writing to the Serial Port 9 15 9 5 Reading the Serial Port 9 16 Chapter 9 ...

Page 92: ...al port The MSC1210 automatically lets you know when it has finished sending the written character and also lets you know whenever it has received a byte so that it can be processed There is no need to worry about transmis sion at the bit level which saves quite a bit of coding and processing time The UART serial port is asynchronous full duplex transmit and receive simul taneously or synchronous ...

Page 93: ...2 pCLK 1 0 0 0 1 Synchronous 8 bits 4 pCLK 1 1 0 1 x Asynchronous 10 bits Timer 1 or 2 baud rate equation 2 1 0 0 Asynchronous 11 bits 64 pCLK 1 SMOD 0 32 pCLK 1 SMOD 1 2 1 0 1 Asynchronous with multiprocessor communication 11 bits 64 pCLK 1 SMOD 0 32 pCLK 1 SMOD 1 3 1 1 0 Asynchronous 11 bits Timer 1 or 2 baud rate equation 3 1 1 1 Asynchronous with multiprocessor communication 11 bits Timer 1 or...

Page 94: ...ollowed by a set ninth bit If TB8 is clear the ninth bit will be clear The RB8bit also operates in modes 2 and 3 and functions essentially the same way as TB8 but on the reception side When a byte is received in modes 2 or 3 a total of nine bits are received In this case the first eight bits received are the data of the serial byte received and the value of the ninth bit received will be placed in...

Page 95: ...safe to say that this bit should almost always be clear so that the flag is set upon reception of any character Bits SM0 and SM1 let the serial mode be set to a value between 0 and 3 inclusive The four modes are defined in Table 9 1 As shown selecting the serial mode selects the mode of operation 8 bit 9 bit UART or shift register and also determines how the baud rate will be calculated 9 2 1 Seri...

Page 96: ...data LSB first then a stop bit On receive the stop bit is shifted into the RB8 bit in the SCON register The baud rate is set by Timer 1 UART 0 or 1 or Timer 2 UART 0 RXD is used for receiving data and TXD is used for transmitting data LSB first On reception the stop bit goes into RB8 in the SCON register Transmission is initiated by any instruction that writes to SBUF The transmission begins after...

Page 97: ...the counter rollover with the bit boundaries The state of each bit is de termined by a majority detect decision on three consecutive samples in the middle of the bit this provides an amount of noise rejection At the middle of the stop bit time the serial port verifies that the status of SCONx RI_x 0 and SCON0 SM2_x 1 if SCON0 SM2_x 0 the stop bit is a don t care If these conditions are true then t...

Page 98: ...ow TH1 256 2SMOD fOSC 384 BaudRate You can also achieve very low baud rates from Timer 1 by enabling T1CON TF1 configuring the timer for mode 1 and using the timer interrupt to initiate a 16 bit software reload as shown in Table 9 2 Table 9 2 Common Baud Rates Using Timer 1 Baud Rate SMODx C T Timer 1 Mode TH1 Value for an 11 0592MHz fOSC 57 6k 1 0 2 0FFH 19 2k 1 0 2 0FDH 9 6k 1 0 2 0FAH 4 8k 1 0 ...

Page 99: ... Asynchronous Full Duplex In mode 2 serial data transfers are 11 bits long full duplex and asynchronous The transfer begins with a start bit followed by eight bits of data LSB first an additional bit of data ninth bit then a stop bit On transmit the ninth data bit is set by TB8 On receive the ninth bit is shifted into the RB8 bit in the SCON register and the stop bit is ignored The baud rate is ei...

Page 100: ...us of SCONx RI_x 0 and SCON0 SM2_x 1 if SCON0 SM2_x 0 the stop bit is a don t care If these conditions are true then the serial port writes the received byte to the SBUFx register loads the stop bit into SCONx RB8_x and sets the SCONx RI_x flag If the conditions are not met the data are ignored After the middle of the stop bit the serial waits for another start bit detection The state of SCON0 SMO...

Page 101: ...ter and the stop bit ignored The baud rate is set by Timer 1 USART0 or 1 or Timer 2 USART0 RXD is used for receiving data TXD is used for transmitting data LSB first On transmission SCON TB8 is used for the ninth bit On reception the ninth bit goes into RB8 in the SCON register The baud rate is adjustable and is based on either Timer 1 or Timer 2 Transmission is initiated by any instruction that w...

Page 102: ... byte to the SBUFx register loads the stop bit into SCONx RB8_x and sets the SCONx RI_x flag If the conditions are not met the data are ignored After the middle of the stop bit the serial waits for another start bit detection Baud rate calculation for mode 3 is identical to that of mode 1 which is fully explained in section 9 2 2 Mode 3 has a special provision for multiprocessor communications Thi...

Page 103: ...rial Port 1 uses Timer 1 Each time the timer increments from its maximum count FFH for Timer 1 or FFFFH for Timer 2 a clock is sent to the baud rate circuit The clock is then divided by 16 to generate the baud rate When using Timer 1 the SMOD0 or SMOD1 bit selects whether or not to divide the Timer 1 rollover rate by two In modes 1 and 3 the baud rate is determined by how frequently Timer 1 or Tim...

Page 104: ...11 059 000 192 19 200 TH1 256 57 699 19 200 TH1 256 3 253 Here a nice even TH1 value is calculated Therefore to obtain 19 200 baud with an 11 059MHz crystal 1 Configure Serial Port mode 1 or 3 for 8 bit or 9 bit serial mode 2 Configure Timer 1 to timer mode 2 8 bit auto reload 3 Set TH1 to 253 to reflect the correct frequency for 19 200 baud 4 Set PCON 7 SMOD to double the baud rate Table 9 5 show...

Page 105: ...ter via the serial port Obviously transmission is not instanta neous it takes a measurable amount of time to transmit the eight data bits that make up the byte along with its start and stop bits and because the MSC1210 does not have a serial output buffer you need to be sure that a char acter is completely transmitted before trying to transmit the next character The MSC1210 lets you know when it i...

Page 106: ...de segment can be used JNB RI Wait for the MSC1210 to set the RI flag MOV A SBUF Read the character from the serial port The first line of the above code segment waits for the MSC1210 to set the RI flag again the MSC1210 sets the RI flag automatically when it receives a character via the serial port So as long as the bit is not set the program re peats the JNB instruction continuously Once a chara...

Page 107: ... Trigger Interrupts 10 3 10 3 Enabling Interrupts 10 5 10 4 Polling Sequence 10 6 10 5 Interrupt Priorities 10 7 10 6 Interrupt Triggering 10 8 10 7 Exiting Interrupts 10 8 10 8 Types of Interrupts 10 9 10 9 Waking Up from Idle Mode 10 15 10 10 Register Protection 10 16 10 11 Common Problems with Interrupts 10 18 Chapter 10 ...

Page 108: ...mers have overflowed whether the serial port has received another character or if some external event has occurred Besides making the main program ugly and hard to read such a situation makes the program inefficient because precious instruction cycles are wasted checking for events that happen infrequently For example say a large 16k program is executing many subroutines and per forming many tasks...

Page 109: ... ESPIT AIE 3 1 N A Milliseconds Timer 33H 0 EMSEC AIE 4 1 EMSEC AIE 4 1 N A ADC 33H 0 EADC AIE 5 1 EADC AIE 5 1 N A Summation Register 33H 0 ESUM AIE 6 1 ESUM AIE 6 1 N A Seconds timer 33H 0 ESEC AIE 7 1 ESEC AIE 7 1 N A External Interrupt 0 03H 1 IE0 TCON 1 2 EX0 IE 0 4 PX0 IP 0 Timer 0 Overflow 0BH 2 TF0 TCON 5 3 ET0 IE 1 4 PT0 IP 1 External Interrupt 1 13H 3 IE1 TCON 3 2 EX1 IE 2 4 PX1 IP 2 Tim...

Page 110: ...hird column indicates the natural priority of the interrupt This is the order in which interrupts will be checked If two or more interrupts occur simultaneously the interrupt with a higher interrupt priority i e that appears first in the list will be serviced first Flag The fourth column indicates the flag that when set will trigger the spe cified interrupt These flags are normally set by the MSC1...

Page 111: ...erial Port 0 interrupt 3 ET1 ABH Enable Timer 1 interrupt 2 EX1 AAH Enable external interrupt 1 1 ET0 A9H Enable Timer 0 interrupt 0 EX0 A8H Enable external interrupt 0 Table 10 3 EICON D8H SFR Bit Name Bit Address Explanation of Function 7 SMOD1 DFH Serial Port 1 double baud rate 6 DEH Undefined set to 1 5 EAI DDH Enable auxiliary interrupt 4 AI DCH Auxiliary interrupt flag 3 WDTI DBH Watchdog in...

Page 112: ...hree SFRs This is useful in program execu tion if there is time critical code that needs to be executed In this case the code may need to be executed from start to finish without any interrupts getting in the way To accomplish this simply clear bit 7 of IE and CLR EA bit 5 of EICON CLR EAI and then set them after the time critical code is done To sum up what has been stated in this section to enab...

Page 113: ... the serial in terrupt must interrupt the Timer 1 interrupt When the serial interrupt is com plete control passes back to the Timer 1 interrupt and finally back to the main program This may be accomplished by assigning a high priority to the serial interrupt and a low priority to the Timer 1 interrupt Interrupt priorities are controlled by the IP B8H or EIP F8H SFRs These SFRs have the following f...

Page 114: ...e second 2 Interrupts of the same and lower priority are blocked 3 In the case of timer and external interrupts the corresponding interrupt flag is cleared 4 Program execution transfers to the corresponding interrupt handler vector address 5 The interrupt handler routine written by the developer is executed Take special note of the third step If the interrupt being handled is a timer or external i...

Page 115: ...nd next character MOV SBUF A Send another character to the serial port EXIT_INT RETI Exit interrupt handler As shown the code checks the status of both interrupts flags If both flags were set both sections of code will be executed Also note that each section of code clears its corresponding interrupt flag If the interrupt bits are not cleared the serial interrupt will be executed over and over unt...

Page 116: ...upt condition not the logic state of the input pin The flags that trigger external interrupts 2 through 5 are found in the EXIF 91H SFR as shown in Table 10 7 When the appropriate condition falling edge or rising edge is detected the corresponding flag is set and the interrupt is triggered if enabled Note The bits in EXIF are set to 1 to indicate that the condition is true the bits do not represen...

Page 117: ... and priorities for Timers 0 1 and 2 reside in the IE and IP registers respectively 10 8 4 Watchdog Interrupt The watchdog interrupt usually has a different connotation than the timer inter rupts Unless the watchdog is being used as a very long timer the completion of the watchdog count means the software has failed to reset the counter and may be lost Like other sources the watchdog timer has a f...

Page 118: ...scribed in the previous paragraph and the specific auxiliary in terrupt is enabled in AIE that condition will set the EICON 4 AI flag to indicate an auxiliary interrupt and vector through 0033H The ISR must clear the AI flag before returning or the auxiliary interrupt will be triggered again Table 10 9 AIE A6H SFR Bit Name Explanation of Function 7 ESEC Enable Seconds Auxiliary Interrupt 6 ESUM En...

Page 119: ...ad SPIDATA 1 ALVD Detect analog low voltage auxiliary interrupt Voltage above threshold 0 DLVD Detect digital low voltage or breakpoint auxil iary interrupt Write BP 1 Note AISTAT is read only A value may not be written to this SFR with the expecta tion of triggering the specific auxiliary interrupt An auxiliary interrupt may be triggered by setting the EICON 4 AI flag but which auxiliary interrup...

Page 120: ...nterrupts one for AVDD and one for DVDD In addition to these a voltage level can be selected during programming that will cause a reset The voltage level used for the interrupts is selected by the Low Voltage Detect control register LVDCON E7H If VDD drops below the level se lected an interrupt will result if enabled The breakpoint and these two interrupts have priority for encoding in the PAI SFR...

Page 121: ...read the new result from these SFRs The interrupt is cleared by reading the LSB of the sample data ADRESL 10 8 5 5 Summation Register Interrupt When the summation mode is set to modes 1 sum values from the ADC or 3 sum for SCNT times then shift SHFT times an interrupt will occur at the end of the process Note that an interrupt will not occur in modes 0 and 2 The interrupt is cleared by reading the...

Page 122: ...xecution In this case the main program has seemingly calculated the wrong answer How can 25H 10H yield 51H as a result It does not make sense A developer that was unfamiliar with interrupts would be convinced that the microcontroller was damaged in some way provoking problems with mathematical calculations What has happened in reality is the interrupt did not protect the registers it used Restated...

Page 123: ...re set by vari ous instructions Unless you are absolutely sure and have a complete under standing of what instructions set what bits it is generally a good idea to always protect the PSW by PUSHing and POPing it off the stack at the beginning and end of the interrupts Also note that most assemblers will not allow the execution of the instruction PUSH R0 Error Invalid instruction This is due to the...

Page 124: ...efore exiting but forget to restore the value of B you leave an extra value on the stack When executing the RETI instruction the 8051 will use that value as the return address instead of the correct value In this case the program will almost certainly crash Always make sure to pop the same number of values off the stack as were pushed onto it Using RET instead of RETI Remember that interrupts are ...

Page 125: ...lse Width Modulator Tone Generator Chapter 11 describes the pulse width modulator tone generator of the MSC1210 ADC Topic Page 11 1 Description 11 2 11 2 Tone Generator 11 3 11 3 PWM Generator 11 5 Chapter 11 ...

Page 126: ...s 7 6 5 4 3 2 1 0 Reset Value SFR A1H PPOL PWMSEL SPDSEL TPCNTL 2 TPCNTL 1 TPCNTL 0 00H PPOL bit 5 Period Polarity Specifies the level of the PWM pulse 0 ON period PWM Duty register programs the ON period 1 OFF period PWM Duty register programs the OFF period PWMSEL bit 4 PWM Register Select Select which 16 bit register is ac cessed by PWMLOW PWMHIGH 0 Period 1 Duty SPDSEL bit 3 Speed Select 0 1MH...

Page 127: ...ock acts as a tone generator which may generate either a staircase or square waveform depending on further configuration In either case the frequency range is 60Hz to 16MHz 11 2 Tone Generator When TPCNTL 1 0 11 the block functions as a tone generator with either a square or staircase waveform that has two or three levels of 0V high impedance and VDD volts respectively The widths of each step in t...

Page 128: ...levels DGND and VDD volts 11 2 1 1 Staircase Mode When TPCNTL 2 is 1 i e TPCNTL 2 0 111 a staircase waveform is gener ated as shown in Figure 11 3 In this figure the value of PWM Period 18FH which is equal to 399 Therefore the total time period is equal to 800 TBASE 11 2 1 2 Square Mode When TPCNTL 2 is 0 i e TPCNTL 2 0 011 a square waveform is gen erated An example with PWM Period 2 is shown in F...

Page 129: ...he OFF duty depending on the bit PPOL PWMCOM 5 If PPOL is set then OFF duty period is pro grammed and if it cleared then ON duty period is programmed The duty cycle is periodic with respect to the period of PWM irrespective of the duty register The duty cycle of the PWM wave for different configurations is shown in the following equations and in Table 11 1 WhenPPOL PWMCON 5 0 PWM Frequency 1 TBASE...

Page 130: ...6 bit register because they are adjacent SFRs Thus the general process for configuring the PWM generator is as follows 1 Configure PWMCON so that PWM mode is selected PWMCON 2 0 001 2 Set PWMCON 4 to select the PWM Duty register 3 Write the PWM Duty 1 value to PWMLOW and PWMHI In the above example PWMLOW HI is written with the value 1 because the off period is 2 ticks long and the value written to...

Page 131: ... PWM Duty Register PWM 128 1 PWM toggle at a count of 128 PWMCON 0x09 Sel PWM Period access SysClk rate PWM mode PWM 5 12 1 11 0592MHz 512 21 6KHz PWM Freq Period 512 counts Note The port pin used for PWM P3 3 must be configured as either standard 8051 or CMOS output for the tone generator PWM to function ...

Page 132: ...SJMP 16 Table 11 3 Statement Explanations Statement Explanation 7 ANDing PDCON with EDH effectively turns off bits 1 PDST and 4 PDPWM Clearing the PDST Power Down System Timer bit turns the system timer on while clearing the PDPWM Power Down PWM module bit turns the PWM module on 8 Sets the USEC SFR to define 1µs which will be used for determining the PWM timing 9 P3 3 must be set to 1 prior to us...

Page 133: ...can be used to initialize P3 3 to low Note If idle low on Tone PWM is achieved by writing 0 to P3 3 which will suppress PWM output subsequently writing a 1 to P3 3 will enable PWM output at any position of the PWM cycle The following program shown in Table 11 4 is very similar to the one provided in the previous section PWM Duty is initially set to zero which idles the PWM It is then reset to 4 at...

Page 134: ...13 PWM 0 Set PWMDuty MOV PWMHI 00h MOV PWMLOW 04h 14 PWMCON 0x09 Enable PWM MOV PWMCON 09h 15 for i 0 i 10 i MOV R7 00h Loop INC R7 CJNE R7 0Ah Loop 16 PWMCON 0x10 select PWMDuty MOV PWMCON 10h 17 PWM 4 Set PWMDuty MOV PWMHI 00h MOV PWMLOW 04h 18 PWMCON 0x09 Enable PWM MOV PWMCON 09h 19 while 1 SJMP 20 Table 11 5 Statement Explanations Statement Explanation 1 12 Same as previous program in section...

Page 135: ...MLOW It is possible that while you are updating one of these two SFRs at the transition of two PWM cycles PWM Period and PWM Duty are loaded to the counter PWMTemp As a result only a partial PWM Period or PWM Duty is updated For those applications that need to avoid incomplete updates the microcon troller could busy poll the P3 3 line to detect the transition of two PWM cycles and update the PWM S...

Page 136: ...rrupt EX1 CLEAR void setpwm period duty p14 p14 debug p period d duty IE1 CLEAR Clear any pending interrupt EX1 SET Enable INT1 pin interrupt void main void char i Setup External INT1 IT1 SET Config INT1 pin for falling edge trigger EA SET Global Int Enable PDCON 0x0ed turn on tone gen sys timer USEC OneUsConst p33 1 turn on P3 3 PWMCON 0 select PWMPeriod PWM 500 Set PWMPeriod PWMCON 0x10 select P...

Page 137: ...s 12 7 12 5 Input Buffer 12 8 12 6 Analog Input 12 8 12 7 Programmable Gain Amplifier PGA 12 9 12 8 PGA DAC 12 10 12 9 Modulator 12 10 12 10 Calibration 12 11 12 11 Digital Filter 12 12 12 12 Voltage References 12 15 12 13 Summation Shifter Register 12 16 12 14 Interrupt Driven ADC Sampling 12 20 12 15 Synchronizing Multiple MSC1210 Devices 12 22 12 16 Ratiometric Measurements 12 24 Chapter 12 ...

Page 138: ...0 includes an ADC with 24 bit resolution The ADC consists of an input multiplexer MUX an optional buffer a programmable gain amplifier PGA and a digital filter The architecture is described diagram in Figure 12 1 Figure 12 1 MSC1210 Architecture ...

Page 139: ...given input pin may serve as the negative input in one measurement and serve as the positive input in the next Further any combination of pins can be used there are no prede fined input pairs that restrict The input multiplexer provides for any combination of differential inputs to be selected on any of the input channels as shown in Figure 12 2 For example if channel 1 is selected as the positive...

Page 140: ...lt 0 0 0 1 AIN1 0 0 1 0 AIN2 0 0 1 1 AIN3 0 1 0 0 AIN4 0 1 0 1 AIN5 0 1 1 0 AIN6 0 1 1 1 AIN7 1 0 0 0 AINCOM 1 1 1 1 Temperature Sensor requires ADMUX FFH INN3 0 bits 3 0 Input Multiplexer Negative Channel This bit selects the negative signal input INN3 INN2 INN1 INN0 Negative Input 0 0 0 0 AIN0 0 0 0 1 AIN1 default 0 0 1 0 AIN2 0 0 1 1 AIN3 0 1 0 0 AIN4 0 1 0 1 AIN5 0 1 1 0 AIN6 0 1 1 1 AIN7 1 0 ...

Page 141: ...nheit or Kelvin using stan dard conversion formulas One value of α that gives good results is 2664 7 The value of α can vary from part to part and is determined from experimental data The following program is a simple example that returns the current tempera ture as detected by the MSC1210 include REG1210 H include stdio h include stdlib h include math h define LSB 298 0232e 9 LSB 5 0 2 24 define ...

Page 142: ...o clear ADCIRQ samples 10 The number of voltage samples we will average while 1 ave 0 for i 0 i samples i while AIE 0x20 Wait for new next result ave bipolar LSB This read clears ADCIRQ volts ave samples temp ALPHA volts 282 14 printf V f resistance f Temp f degrees C n volts resistance temp while main This program first configures the ADC allows the ADC to self calibrate and then enters a loop wh...

Page 143: ... 298 0232e 9 extern void autobaud void extern long bipolar void void main void float sample decimation 1728 CKCON 0 0 MOVX cycle stretch autobaud printf Brown Out Detection n Timer Setup USEC 10 11MHz Clock ACLK 9 ACLK 11 0592 000 10 1 105 920 Hz modclock 1 105 920 64 17 280 Hz Setup ADC PDCON 0x0f7 turn on adc ADMUX 0x01 ADCON0 0x70 Vref On Vref Hi Buff off BOD on PGA 1 ADCON2 decimation 0xFF LSB...

Page 144: ... than 1 5V below the positive rail voltage The input impedance of the MSC1210 without the buffer is 5MΩ PGA With the buffer enabled the impedance is typically 10GΩ the input voltage range is re duced and the analog power supply current is higher The buffer is controlled by the BUF bit in the ADC control register ADCON0 3 setting BUF enables the input buffer while clearing it disables the input buf...

Page 145: ... component of the sample thus reducing the benefit of the improved resolution from the lower reference voltage The PGA setting is set by modifying the three LSBs of the ADCON0 SFR These three bits allow the software to set the PGA to any of the eight possible PGA settings listed in Table 12 1 Table 12 1 PGA Settings PGA2 PGA1 PGA0 GAIN 0 0 0 1 default 0 0 1 2 0 1 0 4 0 1 1 8 1 0 0 16 1 0 1 32 1 1 ...

Page 146: ...ed by 313mV i e 5 000V 256 19 53mV S 16 312 5mV 12 9 Modulator The modulator is a single loop second order delta sigma system The modu lator clock speed is derived from the oscillator frequency divided by the ACLK register plus one divided by 64 This can be summarized by the formula Analog Sample Rate Oscillator Frequencyń ACLK 1 64 Thus given an oscillator frequency of 11 0592MHz if ACLK 8 the an...

Page 147: ...tare weight Then the measurements that follow would only have the new weight in the output of the ADC Calibration should be performed after power on a change in temperature or a change of the PGA For operation with a reference voltage greater than AVDD 1 5V the buffer must also be turned off during calibration Calibration will remove the effects of the ODAC therefore changes to the ODAC register m...

Page 148: ...PGA is changed When switching to a new channel it will use the fast settling filter for the next two conversions the first of which should be discarded It will then use the sinc2 followed by the sinc3 filter to improve noise performance This combines the low noise advan tage of the sinc3 filter with the quick response of the fast settling time filter The frequency response of each filter is shown ...

Page 149: ...Digital Filter 12 13 Analog to Digital Converter Figure 12 5 Filter Frequency Responses ...

Page 150: ...n Auto mode selects each of the different filter outputs after the input channel has changed This means that the output uses the fast settling filter for 2 cycles then sinc2 for the next cycle and finally sinc3 for all remaining cycles until the channel is changed again When switching channels the settling time must be factored in to determine the total throughput For example if the data rate is 2...

Page 151: ...xternal selection and 4 1 25V 2 5V internal reference voltage Internal voltage reference is enabled by setting ADCON0 5 EVREF SFR ad dress 0xDC which is the default condition When internal voltage reference is enabled it may be selected as either 1 25V or 2 5V depending on the setting of ADCON0 4 VREFH Setting this bit sets the internal reference voltage to 2 5V while clearing it sets the internal...

Page 152: ...e summed to the current sum then divided by a specified number mode 3 The operation of the summation registers is controlled and configured with the SSCON E1H SFR In addition to controlling the four modes of operation SSCON also is used to control how many samples will be taken from the ADC and by what value the final sum should be divided by if any The individual bits of SSCON have the following ...

Page 153: ...1 0 128 1 1 1 256 When the requested number of samples have been obtained and summed a summation auxiliary interrupt will be triggered if enabled SHF2 SHF1 and SHF0 SSCON 0 through SSCON 2 are used to indicate by what value the final summation value should be divided Specifically the value indicates how many bits to the right the final summation value will be shifted less one Thus a shift count of...

Page 154: ...ions for each summation whereas the simple addition approach which does not take advantage of the MSC1210 summation register takes at least 8 MOV instructions and 4 ADD instructions 12 13 2 ADC Summation Mode The ADC summation mode functions very similarly to the manual summation mode but instead of your program writing values to the SUMRx registers the ADC writes values to the SUMRx registers In ...

Page 155: ... summation with shift divide mode is a combination of ADC summa tion mode and manual shift mode This mode will sum the number of ADC sam ples indicated by the CNT bits of SSCON and then shift the final result to the right divide by the number of bits indicated by the SHF bits This mode is use ful when calculating the average of a number of ADC samples For example to calculate the average of 16 ADC...

Page 156: ...execution include REG1210 H include stdio h include stdlib h include math h define LSB 298 0232e 9 LSB 5 0 2 24 extern void autobaud void extern long bipolar void long sample Hold the samples retrieved from A D converter void auxiliary_isr void interrupt 6 AuxInt sample bipolar LSB Read sample clear ADCIRQ AI CLEAR Clear Aux Int right before Aux ISR exit void main void float volts temp resistance ...

Page 157: ...n for k 0 k 4 k Wait for Four conversions for filter to settle after calibration We go to sleep When we wake up the interrupt will have read the sample PCON 0x02 Go to power down until sample ready samples 10 The number of voltage samples we will average while 1 ave 0 for i 0 i samples i PCON 0x02 Go to power down until sample ready ave bipolar LSB This read clears ADCIRQ printf Average sample f n...

Page 158: ...on to be completed The ADC interrupt can be used as described in the previous section After the ADC interrupt the PDAD bit in the PDCON F1H register is set to 1 to power down the ADC The MSC1210 continues to monitor the sync input and when it goes low the PDAD bit is set back to zero thereby activating the ADC In summary synchronizing the MSC1210 can be achieved with the following steps 1 Start AD...

Page 159: ...1 0592 000 10 1 105 920 Hz modclock 1 105 920 64 17 280 Hz Setup ADC PDCON 0x0f7 turn on adc ADMUX 0x01 Select AIN0 AIN1 ADCON0 0x30 Vref On Vref Hi Buff off BOD off PGA 1 ADCON2 decimation 0xFF LSB of decimation ADCON3 decimation 8 0x07 MSB of decimation ADCON1 0x01 bipolar auto self calibration offset gain while sync 0 As long as sync is low wait Now that sync is low shut down ADC PDCON 0x08 whi...

Page 160: ...IN Figure 12 6 Circuit Drawing The voltage measured is a ratio of the resistances RREF and PT100 because the same current flows through the sense element PT100 and the reference resistor RREF Any errors in IOUT1 do not enter into the accuracy of the measurment be cause as shown in the following equations IOUT is effectively cancelled out VIN PT100 IOUT VREF RREF IOUT ADC Result VIN VREF ADC Result...

Page 161: ... than 0 3V that does not work In such a case you will need to connect the reference resistor from the power supply to the sensor and then connect the sensor to GND2 Now you can still use the reference resistor to set the reference voltage even though the voltages are between 2 5V to 4 5V The differential reference inputs however can be used for both grounded and non grounded applications For examp...

Page 162: ...12 26 ...

Page 163: ...l interface SPI of the MSC1210 ADC Topic Page 13 1 Description 13 2 13 2 Functional Description 13 2 13 3 Clock Phase and Polarity Controls 13 4 13 4 SPI Signals 13 5 13 5 SPI System Errors 13 6 13 6 Data Transfers 13 7 13 7 FIFO Operation 13 9 13 8 Code Examples 13 10 Chapter 13 ...

Page 164: ...containing the shift register and the read data buffer SPI data is transmitted and received simultaneously For every byte that is sent a byte is also received The system is double buffered in the transmit direction and double buffered in the receive direction This means that new data for transmission can be written to the SPIDATA register before the previous transfer is complete Additionally recei...

Page 165: ...data lines A slave select line allows individual selection of a slave SPI device slave de vices that are not selected do not interfere with SPI bus activities On a master SPI device the select line can optionally be used to indicate a multiple master bus contention refer to Figure 13 2 A section of internal RAM from 80H to FFH can be used as a FIFO to extend the buffering for receive and transmit ...

Page 166: ...ts one of two different transfer for mats The clock phase and polarity should be identical for the master SPI de vice and the communicating slave device In some cases the phase and polar ity are changed between transfers to allow a master device to communicate with peripheral slaves having different requirements When CPHA 0 the SPI standard defines that the SS line must be negated and reasserted b...

Page 167: ...ng a byte of informa tion during a sequence of eight clock cycles There are four possible timing relationships that can be chosen by using con trol bits CPOL and CPHA in the SPI control register SPICON Both master and slave devices must operate with the same timing The SPI clock rate select bits CLK 2 0 in the SPICON of the master device select the clock rate In a slave device CLK 2 0 have no effe...

Page 168: ... not written to the SPIDATA register before the previous bytes have been transferred With the FIFO operation when the FIFO is filled the next writes to the SPIDATA register are ignored When the SPI system is configured as a master and the SS input line goes to active low a mode fault error has occurred usually because two devices have at tempted to act as master at the same time In cases where mor...

Page 169: ...The most significant bit is forced to a one There is no signal that switches the SPI interface on or off It can be powered down using the PDCON F1H register However if it is powered up then it is operational For the master all that is necessary to transmit a byte is to write the value to SPIDATA 9BH The SS pin is not used in master mode It can be used to drive an SS signal For slave operation the ...

Page 170: ...sed in the AI interrupt rou tine to determine the source of the interrupt The SPI receive interrupt can be monitored in the AISTAT register The SPI Transmit control register SPITCON 9DH controls the data transmit operation The transmit buffer can be flushed with the write only TXFLUSH bit A flush operation changes the SPI transmit pointer so that it points to the same address as the FIFO OUT point...

Page 171: ...e of the FIFO can be adjusted from 2 to 128 bytes depending on the allowable inter rupt latency For example assume that the application has time critical opera tions that cannot be interrupted for 10µs Using an 11 0592MHz crystal and if SPI clock is fOSC 2 one byte can be shifted out in 1 46µs or 69 bytes in 100µs By setting the transmit IRQ level for 8 it would require that the FIFO be at least 7...

Page 172: ...nd P1 4 SS is configured as output whereas pin P1 6 MISO is configured as input because we are going to use the device as mas ter When configured as a slave line 10 is commented out and line 11 is un commented line 11 is commented out in Example 13 1 In line 12 the SPI is powered up by writing to PDCON In line 13 the SPICON register is set to put the SPI in master mode double buffer mode with orde...

Page 173: ...or a simple SPI master in FIFO mode using interrupts In line 4 the the port direction is set for the pins that are used by the SPI Pins P1 7 SCLK pin P1 5 MOSI and P1 4 SS are configured as outputs and pin P1 6 MISO is configured as input because the device will be used in master mode In line 5 the SPI module is powered up by writing to the PDCON In line 6 the Rxlevel is set to 4 and the RXBuffer ...

Page 174: ...configured to be triggered when the number of bytes to transmit is 4 or fewer The number to bytes to transmit are 4 so the interrupt is triggered and 4 additional bytes are subsequently written to the buffer Thus the buffer is completely filled with bytes to be transmitted As one byte is transmitted an additional byte is written Once 4 bytes are transmitted 4 by tes will be received at which point...

Page 175: ...14 1 Additional MSC1210 Hardware Chapter 14 describes addtional hardware on the MSC1210 ADC Topic Page 14 1 Description 14 2 14 2 Low Voltage Detect 14 2 14 3 Watchdog Timer 14 4 Chapter 14 ...

Page 176: ...nd beyond those of a typical MCS 51 part 14 2 Low Voltage Detect The MSC1210 includes low voltage and brownout detection circuits for both the analog and digital supply voltages The voltage levels at which these cir cuits are tripped is programmable Figure 14 1 Brownout Reset and Low Voltage Detection ...

Page 177: ...arators VSPA powers the analog section resistor string and the bandgap voltage Level shifters where needed are included inside the block Table 14 1 Typical Sub Circuit Current Consumption Sub Ckt Current Consumption Band Gap 20µA Compartors 2µA Resistor String 6µA Total 40µA Table 14 2 Comparator Specification Comparator Parameters 50mV 2mV Hysteresis at 2 5V 100mV 8mV Hysteresis at 4 7V 26mV Hyst...

Page 178: ...alfunction or programming error Figure 14 2 System Timing Interrupt Control 14 3 1 Watchdog Timer Hardware Configuration The watchdog is first configured when code is downloaded to the MSC1210 Bit 3 of hardware configuration register 0 HCR0 is the Enable Watchdog Reset EWDR bit If this bit is set the watchdog will trigger a reset if the watchdog is enabled by software and not reset at appropriate ...

Page 179: ...imer then begins a countdown that unless reset by your pro gram will trigger a watchdog reset or interrupt depending on the configuration of HCR0 described previously The time after which the watchdog will be trig gered is also configured by the low five bits of the WDTCON SFR These bits which may represent a value from 1 to 32 0 to 31 plus 1 multiplied by the time represented by HMSEC defines the...

Page 180: ...tchdog times out or the next time the watchdog is reset see next section For example WDTCON 0x80 Set EWDT WDTCON 0x07 Clear EWDT set timeout 7 800ms WDTCON 0x06 Set timeout 6 700ms In this example the watchdog will initially be enabled with a timeout of 800ms The very next instruction sets the timeout to 700ms In this case the watchdog will time out after 800ms unless it is reset as described in t...

Page 181: ...should be reset The following code will reset the watchdog timer and notify the MSC1210 that your program is still executing correctly WDTCON 0x20 Set RWDT other bits unaffected WDTCON 0x20 Clear RWDT watchdog reset Note It is generally a good idea to place the watchdog reset code in the main sec tion of your program that is within a rapidly executing control loop It is not advisable to place the ...

Page 182: ...MSC1210 or trigger a watchdog interrupt depending on the setting of the HCR0 hardware configuration register 14 3 5 1 Watchdog Reset In the case of a watchdog reset the MSC1210 is reset SFRs will assume their default values the stack is reset and the program starts executing again at address 0000H The contents of RAM is not affected 14 3 5 2 Watchdog Interrupt If the HCR0 register is configured to...

Page 183: ...ociated with the MSC1210 ADC Topic Page 15 1 Hardware Configuration 15 2 15 2 Advanced Flash Memory 15 6 15 3 Breakpoint Generator 15 7 15 4 Power Optimization 15 9 15 5 Flash Memory as Data Memory 15 10 15 6 Advanced Topics and Other Information 15 12 Chapter 15 ...

Page 184: ... configuration data can only be set at program time They cannot be modified by your program at run time once the firmware has been downloaded to the MSC1210 15 1 1 Hardware Configuration Registers The MSC1210 has two hardware configuration registers HCR0 and HCR1 These registers are set at the moment the MSC1210 is programmed be it in parallel or serial mode and are used to set various operating p...

Page 185: ...to flashmemory RSL bit 5 Reset Sector Lock When clear your program may write to the reset sector the first 4k of flash program memory When it is set default your program may not write to this area of flash memory This bit functions the same as the PML bit but applies to only the first 4k of flash program memory If the MSC1210 is configured such that only 4k is assigned to flash program memory this...

Page 186: ... voltage level that triggers an analog brownout situation 00 4 5V 01 4 2V 10 2 7V 11 2 5V default DAB bit 3 Disable Analog Power Supply Brownout Detection When this bit is set brownout detection on the analog power supply is disabled When clear brownout detection operates normally DDB bit 2 Disable Digital Power Supply Brownout Detection When this bit is set brownout detection on the digital power...

Page 187: ...ram The 128 bytes of flash configuration memory which include the 116 bytes of user defined configuration data and two bytes of hardware configuration regis ters can be read by your program in normal operation However the configu ration data is not obtained by reading the code address to which they were pro grammed That is to say although flash configuration memory is set at pro gram time by placi...

Page 188: ...ML and RSL bits your program must first set the MXWS bit of MWS 8FH prior to writing to flash program memory If this bit is not set writes to flash program memory are not effective 15 2 2 Updating Interrupts with Reset Sector Lock If the Reset Sector Lock RSL bit in HCR0 has been set the user program will not be able to modify the contents of the first 4k of flash program memory Set ting RSL makes...

Page 189: ...AAh BPH ABH and MCON 95H SFRs The Breakpoint Control SFR BPCON controls the con figuration of the breakpoint BPL and BPH together form a 16 bit breakpoint address BPSEL MCON 7 selects which of the two breakpoints is to be con figured The BPCON SFR has the following structure 7 6 5 4 3 2 1 0 Reset Value SFR A9H BP 0 0 0 0 0 PMSEL EBP 00H BP bit 7 Breakpoint Interrupt This bit indicates that a break...

Page 190: ...rupt If BPSEL is set Breakpoint 1 triggered the interrupt When using breakpoints notice that the actual breakpoint occurs after the se lected address That is because of interrupt latency on the MSC1210 It takes a few cycles for the interrupt to be recognized and serviced During that time the processor continues for two or three more instructions which means that the program counter will be offset ...

Page 191: ...tedly waiting for an interrupt condition to occur the part may be made to go to sleep until the condition is triggered during that time power consumption is minimized External interrupts the watchdog interrupt or the auxiliary interrupts can be made to wake up an idling MSC1210 To enter idle mode bit 0 of PCON must be set This can be accomplished with the instruction PCON 0x01 When this instructio...

Page 192: ...tly by reading XRAM memory This is accomplished in this C program by using the pFlashPage pointer it is accomplished in assembly language using the MOVX instruction After reading flash memory it increments the value of the first byte of the memory block read by one The call to page_erase is a call to the routine in boot ROM that erases the requested block of memory Thereafter it makes re peated ca...

Page 193: ... write the modified contents back into flash for i 0 i PAGE_SIZE i Result write_flash_chk PAGE_START i Buffer i DATA_FLASH re read the counter pFlashPage char xdata PAGE_START printf flash write returned d Reset counter is now d press any key n int Result int pFlashPage while RI 0 RI 0 Note Your program must use the boot ROM routines such as write_flash_chk in order to modify flash data memory if ...

Page 194: ...flash memory can also be used to control a debugging session This is described in http www s ti com sc psheets sbaa079 sbaa079 pdf 15 6 3 Using MSC1210 with Raisonance Development Tools In addition to the Keil toolset which is included with he MSC1210 EVM kit Raiso nance provides a development toolset that may be used to develop software for the MSC1210 Further details on using the Raisonance tool...

Page 195: ...n CJNE 16 16 16 15 Less Than and Greater Than Comparison CJNE 16 17 16 16 Zero and Nonzero Decisions JZ JNZ 16 18 16 17 Performing Additions ADD ADDC 16 18 16 18 Performing Subtractions SUBB 16 20 16 19 Performing Multiplication MUL 16 21 16 20 Performing Division DIV 16 22 16 21 Shifting Bits RR RRC RL RLC 16 23 16 22 Bit Wise Logical Intructions ANL ORL XRL 16 24 16 23 Exchanging Register Values...

Page 196: ...uction sets different forms of addressing In fact only general concepts may work from one processor to another The low level nature of assembly language programming requires an under standing of the underlying architecture of the processor for which one is devel oping This is why we explained the 8052 architecture fully before attempting to introduce the reader to assembly language programming in ...

Page 197: ...ship between the assembly language instruction and the machine language code that is generated by the assembler Finally the instruction above includes the optional comment This is just a sample comment The comment must always start with a semicolon The semicolon tells the assembler that the rest of the line is a comment that should be ignored by the assembler All fields are optional and the follow...

Page 198: ...g zero allows the assembler to differentiate the hex number from a symbol because a symbol never starts with a number Binary To express a binary number enter the binary number followed by a trailing B to indicate binary For example the binary number 100010 is ex pressed as 100010B Octal To express an octal number enter the octal number itself followed by a trailing Q to indicate octal For example ...

Page 199: ...e quotes and are con verted to their numeric equivalent at assemble time For example the follow ing two instructions are the same MOV A C MOV A 43H The two instructions are the same because the assembler will see the C se quence convert the character contained in quotes to its ASCII equivalent 43H and use that value Thus the second instruction is the same as the first Strings of characters are som...

Page 200: ...JMP always works You can always use LJMP to jump to any address in your program SJMP requires two bytes of memory but has the restriction that it can only jump to an instruction or label within 128 bytes before or 127 bytes after the instruction This is useful if you are branching to an address that is very close to the jump itself You save 1 byte of memory by using SJMP instead of AJMP AJMP also ...

Page 201: ...utine code here RET Return from subroutine SUBROUTINE2 subroutine code Insert subroutine code here RET Return from subroutine The code starts by calling SUBROUTINE1 Execution transfers to SUBROUTINE1 and executes whatever code is found there When the MCU hits the RET instruction it automatically returns to the next instruction which is LCALL SUBROUTINE2 SUBROUTINE2 is then called executes its code...

Page 202: ...tinationRegister SourceValue DestinationRegister always indicates the register or address in which Source Value will be stored whereas SourceValue indicates the register the value will be taken from or the value itself if it is preceded by a pound sign For example MOV A 25h Moves contents of Internal RAM address 25h to accumulator MOV 25h A Move contents of accumulator into Internal RAM address 25...

Page 203: ... to R register instruction That is to say the following instruction is invalid MOV R2 R1 INVALID This is a logical type of operation for a programmer to implement but the in struction is invalid Instead it must be programmed as MOV A R1 Move R1 to accumulator MOV R2 A Move accumulator to R2 Another combination that is not supported is MOV indirectly from Internal RAM to another Indirect RAM addres...

Page 204: ...ses 20H through 2FH this example will later be improved upon to require less code MOV 20h 00h Clear Internal RAM address 20h MOV 21h 00h Clear Internal RAM address 20h MOV 22h 00h Clear Internal RAM address 20h MOV 23h 00h Clear Internal RAM address 20h MOV 24h 00h Clear Internal RAM address 20h MOV 25h 00h Clear Internal RAM address 20h MOV 26h 00h Clear Internal RAM address 20h MOV 27h 00h Clear...

Page 205: ...NC R1 Increment R1 by 1 INC 40h Increment Internal RAM address 40h by 1 The DEC instruction will subtract 1 from the current value of the specified regis ter If the current value is 0 it will underflow back to 255 For example if the accumulator holds the value 240 and the DEC A instruction is executed the accumulator will be decremented to 239 DEC A Decrement the accumulator by 1 DEC R1 Decrement ...

Page 206: ... of the loop This could con tain any instruction or instructions you wishe to execute repeatedly In this case the accumulator is incremented with the INC A instruction The interesting part is the third line with the DJNZ instruction This instruction says to decrement the R0 Register and if it is not now zero jump back to LOOP This instruction decrements the R0 register then checks to see if the ne...

Page 207: ...use these 128 user bits reside in internal RAM at the addresses of 20H through 2FH Each byte of Internal RAM by definition holds 8 individual bits so bit 20H would be the lowest bit of Internal RAM 24H Note It is very important to understand that bit memory is a part of internal RAM In the case of SETB 20h we concluded that bit 20H is actually the low bit of internal RAM address 24H That is becaus...

Page 208: ...ram memory whereas the MOV A 00h solution requires two bytes An additional instruction CPL A also exists This instruction flips each bit in the accumulator Therefore if the accumulator holds 255 11111111 binary it will hold 0 00000000 binary after the CPL A instruction is executed Finally the MOV instruction can be used to move bit values between any given bit user or SFR bits and the carry bit Th...

Page 209: ... address if the bit is not set JC means jump if carry set This is the same as the JB instruction but it only tests the carry bit An additional instruction was included in the instruction set to test for this common condition because many operations and decisions are based on whether or not the carry flag is set Thus instead of using the instruc tion JB C label which takes 3 bytes of program memory...

Page 210: ...K_LCD subroutine if the accumulator equals 42H and call the DEBOUNCE_KEY subroutine if the accumulator equals 50H This could be im plemented using CJNE as follows CJNE A 30h CHECK2 If A is not 30h jump to CHECK2 label LCALL PROC_A If A is 30h call the PROC_A subroutine SJMP CONTINUE When we get back we jump to CONTINUE label CHECK2 CJNE A 42h CHECK3 If A is not 42h jump to CHECK3 label LCALL CHECK...

Page 211: ...e if the accumulator holds some number and we want to know if it is less than or greater than 40H the following code could be used CJNE A 40h CHECK_LESS If A is not 40h check if or 40h LJMP A_IS_EQUAL If A is 40h jump to A_IS_EQUAL code CHECK_LESS JC A_IS_LESS If carry is set A is less than 40h A_IS_GREATER Code Otherwise it means A is greater than 40h The code above first compares the accumulator...

Page 212: ...ther non 8052 architectures have a zero flag that is set by instructions and the zero test instruction tests that flag not the accumulator The 8052 how ever has no zero flag and JZ and JNZ both test the value of the accumulator not the status of any flag 16 17 Performing Additions ADD ADDC The ADD and ADDC instructions provide a way to perform 8 bit addition All addition involves adding some numbe...

Page 213: ...lds the result of 10H and the carry bit is set The fact that the carry bit is set can subsequently be used with the ADDC to add the carry bit into the next addition instruction The auxiliary carry AC bit is set if there is a carry from bit 3 and cleared other wise For example if the accumulator holds the value 2EH and the value 05H is added to it the accumulator then equals 33H as expected but the...

Page 214: ...ry bit in its operation it is necessary to always clear the carry bit CLR C before executing the first SUBB in a sub traction operation so that the prior status of the carry flag does not affect the instruction SUBB sets and clears the carry auxiliary carry and overflow bits in much the same way as the ADD and ADDC instructions SUBB sets the carry bit if the number being subtracted from the accumu...

Page 215: ...ator with 20h MOV B 75h Load B with 75h MUL AB Multiply A by B The result of 20H S 75H is 0EA0H Therefore after the above MUL instruction the accumulator holds the low byte of the answer A0H and B holds the high byte of the answer 0EH The original values of the accumulator and B are overwritten If the result is greater than 255 OV is set otherwise it is cleared The carry bit is always cleared and ...

Page 216: ...3h MOV B 13h Load B with 13h DIV AB Divide A by B The result of F3H 13H is 0CH with remainder 0FH Thus after this DIV instruc tion the accumulator holds the value 0CH and B holds the value 0FH The carry bit and the overflow bit are both cleared by DIV unless a division by zero is attempted in which case the overflow bit is set In the case of division by zero the results in the accumulator and B af...

Page 217: ...7 is rotated into carry carry into bit 0 Figure 16 1 shows how each of the instructions manipulates the eight bits of the accumulator and the carry bit Using the shift instructions is obviously useful for bit manipulations However they can also be used to quickly multiply or divide by multiples of two For example there are two ways to multiply the accumulator by two MOV B 02h Load B with 2 MUL AB ...

Page 218: ...t remains set other wise the bit is cleared The result is left in parameter1 ORL logical OR looks at each bit of parameter1 and compares it to the same bit in parameter2 If the bit is set in either parameter the bit remains set other wise the bit is cleared The result is left in parameter1 XRL logical exclusive OR looks at each bit of parameter1 and compares it to the same bit in parameter2 If the...

Page 219: ...ent of the specified bit That means if the specified bit is set the carry bit is ANDed as if it were clear If the specified bit is clear it is ANDed with the carry bit as if it were set ORL C bit This instruction will perform a logical OR between the carry bit and the specified bit If either the carry bit or the specified bit is set the carry bit is set If neither bit is set the carry bit is clear...

Page 220: ...herefore there are two nibbles in the accumulator The high nibble consists of bits 4 through 7 whereas the low nibble consists of bits 0 through 3 The SWAP A instruction will swap the two nibbles of the accumulator For ex ample if the accumulator holds the value 56H the SWAP instruction converts it to 65H Likewise F7H is converted into 7FH Note The SWAP A instruction is identical to executing four...

Page 221: ... used Thus 09H jumps to 10H This is all fine and good but what happens when adding two BCD numbers together For example what happens when adding 38 to 25 Obviously in normal decimal math 38 25 63 Ideally doing the same addition on BCD encoded values would have the same result However 38 encoded as BCD is 38h and 25 encoded as BCD is 25H 38H 25H 5DH Obviously the result no longer looks like a decim...

Page 222: ...r onto stack accumulator still holds 35h ADD A 40h Add 40h to the accumulator accumulator now holds 75h POP ACC Pop the accumulator from stack accumulator holds 35h again The above code is functionally useless However it does illustrate how to use PUSH and POP The code starts by assigning 35H to the accumulator It then PUSHes it onto the stack Then it adds 40H to the accumulator just to change the...

Page 223: ... 2 When using PUSH be sure to always POP that value off the stack even if not in a subroutine 3 Be sure to not jump over the section of code that POPs a value off the stack A common error is to PUSH a value onto the stack and then execute a conditional instruction that jumps over the instruction that POPs that val ue off This results in an unbalanced stack and will probably end up crash ing the pr...

Page 224: ...ted in the follow ing examples MOV DPTR 1234h Sets DPTR to 1234h MOV DPTR 0F123h Sets DPTR to F123h MOV DPH 40h Sets DPTR high byte to 40h DPTR now 4023h MOV DPL 56h Sets DPTR low byte to 56h DPTR now 4056h As shown the first two instructions set DPTR first to 1234H and then to F123H The next example sets DPH to 40H leaving the DPTR low byte unchanged Changing DPH to 40H will result in DPTR being ...

Page 225: ...s move data from external RAM into the accumulator wheras the last two forms move data from the accumulator into external RAM MOVX with DPTR when using the forms of MOVX that use DPTR DPTR is used as a 16 bit memory address The 8052 automatically communicates with the off chip RAM obtains the value of that memory address and stores it in the accumulator MOVX A DPTR or writes the accumulator to the...

Page 226: ...e address contained in the two registers accumulator and DPTR DPTR is initialized to point to the first byte of the table and the accumu lator is used as an offset into the table For example perhaps there is a table of values that resides at 2000H in code memory A subroutine needs to be written that obtains one of those six values based on the value of the accumulator This could be coded as MOV A ...

Page 227: ...is is because the value of PC will be that of the instruction immediately following the MOVC instruction in this case the RET instruction The RET opcode is not needed but the data that follows RET is The accumulator needs to be INCremented by 1 byte to skip over the RET instruction because the RET instruction requires one byte of code memory Note The value that the accumulator must be incremented ...

Page 228: ...14H Consider the following code RL A Rotate accumulator left multiply by 2 MOV DPTR JUMP_TABLE Load DPTR with address of jump table JMP A DPTR Jump to the corresponding address JUMP_TABLE AJMP SUB0 Jump table entry to SUB0 AJMP SUB1 This code first takes the value of the accumulator and multiplies it by two by shift ing the accumulator to the left by one bit The accumulator must first be multiplie...

Page 229: ...7 11 17 4 Watchdog Timer 17 12 17 5 System Timer 17 16 17 6 Control Clock 17 16 17 7 Analog to Digital Converter 17 17 17 8 Summation Shifter 17 20 17 9 Interrupts 17 30 17 10 Ports 17 31 17 11 Serial Peripheral Interface SPI 17 32 17 12 mVision 2Debug Program Example 17 38 17 13 Serial Port I O 17 40 17 14 Additional Resource 17 46 Chapter 17 ...

Page 230: ...og to Digital Converter 7 Summation Shifter 8 Clock Control The use and the applications of these peripherals are discussed in this section The graphical user interface GUI core of the Keil Simulator consists of a collection of individual dialog windows that represent the respective MSC1210 peripheral module that is being simulated These dialogs facilitate interaction between the user developer an...

Page 231: ...imer continues running hence the Run status displayed in the non editable text window labeled Status If the TR0 bit of TCON repre sented by the check box is activated once clearing the state of the TR0 check box the state of the non editable text window labeled Status reverts to Stop implying that Timer 0 has stopped running Note Parameter specification through the various dialog boxes is just an ...

Page 232: ... the TMOD register In the same vein the TL0 and TH0 registers are properly associated with the contents of the TL0 and TH0 windows within the dialog The logical states of the T0 pin P3 4 TF0 Timer Counter 0 interrupt flag the TR0 INT0 and GATE bits of the TCON SFR for instance are reflected in the checked cleared statuses of the T0 pin TF0 TR0 GATE and INT0 check box displays respectively The inte...

Page 233: ... 0 1 Example Due to this sample program setting the interrupt trigger edge type for edge trig ger a transition from cleared to checked on the INT0 line will induce an inter rupt request The contents of the registers TH0 TL0 TH1 and TL1 in Figure 17 2 reflect the snapshot values of the Timer 0 MSB Timer 0 LSB Timer 1 MSB and Timer 1 LSB registers respectively As explained earlier altering the conte...

Page 234: ...Timers 17 6 Figure 17 4 Timer Counter 1 Mode 1 Figure 17 5 Interrupt System ...

Page 235: ... T2 for Serial0 Tx Rx baudgen SCON Async mode 1 8 bit UART enable rcvr TI CLEAR RI CLEAR SCON 0x50 PCON 0x80 Set SMOD0 for 16X baud rate clock interrupt_timer 0 This is a type 1 interrupt which implies that the vector address for this routine is 0x0B If an interrupt request is issued and there is no other interrupt request of higher priority pending and neither is an ISR from an interrupt source o...

Page 236: ... line is raised the timer starts running changing the status display to run It continues running until the INT0 line is dropped This is essentially a pulse width measurement program If the number of calls is odd the TR0 bit for timer 0 is reset which effectively stops the timer regardless of the state of GATE and INT0 The status window now displays stop The global variable end_test is set to a val...

Page 237: ...lapse within the period when the INT0 line was asserted and the Timer 0 TR0 bit was high or the time between the period when TR0 and INT0 were high and TR0 went low This is purely arithmetic It is important to state that TH0 and TL0 nev er start at zero hence the 0x0200 correction time_lapse ǒtimer_0_overflow current_count 0x0200 0x10000 0x0200 Ǔ 12 0x10000 0x0200 24 106 The result of the pulse wi...

Page 238: ...r timer0 TL0 count_start 256 set TLO for timer0 Indefinite Idle loop It breaks when interrupt_external0 ISR is called an even number of times In that instance end_test is set to 1 otherwise it is 0 while end_test compute time elapsed including the residual time in the 16 bit counter with correction for the 0x0200 counter offset current_count TH0 256 TL0 current residual timer0 count time_lapse_res...

Page 239: ...created by toggling the individual bits is displayed in the editable text display T2CON Writing a number into this window will correctly program the states of the respective bit the same way it would program the individual bits of the device s T2CON register By the same token the checked or cleared state of the T2EX T2 Pin TF2 and EXF2 boxes have the same effects on or are affected the same way by...

Page 240: ...atchdog timer must be turned on either by placing a check mark on the PDWDT check box or writing a logic 1 into the PDWDT bit of the PDCON SFR from within the software The appropri ate value must also be written into the watchdog timer register through the WDTIMER editable text window This would properly set the WDCNT counter bits lower five bits of WDTIMER through which watchdog expiration time i...

Page 241: ...In order to be able to access the ISR the watchdog reset must be disabled This is achieved by clearing the watchdog reset enable bit The default state for this bit is logic 1 i e watchdog reset enabled The complete watchdog facility cannot be simulated because the configuration address and data access to the HCR0 is not implemented in this simulator version However an example is provided here to s...

Page 242: ...10 Set Watchdog Timer for 200 ms WDTIMER 0x0E Enable Watchdog Timer WDTIMER 0x80 WDTIMER 0x80 void watchdog_interrupt interrupt 12 using 1 This routine cannot be tested because we cannot get around the watchdog reset on the simulator The watchdog reset cannot be disabled The watchdog interrupt is never activated hence 0x0063 is never vectored into static int j Reset Watchdog This is the sequential...

Page 243: ...t_watchdog start short loop to test RWDT for i 0 i 400 i idle delay j i 13 4000 Reset Watchdog Timer before Watchdog Timer Expires WDTIMER 0x20 WDTIMER 0x20 Infinite loop to test Watchdog Timer Time out with interrupt In the case in which the Watchdog Reset cannot be disabled there will not be any interrupts The watchdog time would eventually run out and a reset procedure will be activated while 1...

Page 244: ...rupt or the millisecond system timer interrupt by toggling either of these check boxes The SYSTEM clock is turned on or turned off by toggling the SYSTON check box Please refer to Chapter 8 Timers for a more compre hensive discussion of the system timer The corresponding time interval for the one microsecond timer the one millisec ond timer and the one hundred milliseconds timer on the bases of th...

Page 245: ...its Writing data values into the ADCON2 and ADCON3 registers respectively sets the ADC decimation filter ratio values The lower three bits of ADCON3 corre spond to the most significant three bits of the converter decimation ratio and the whole ADCON2 byte represents the LSB for the decimation ratio It should be stressed that if the contents of either ADCON2 or ADCON3 are modified the converter mus...

Page 246: ...pecify the desired analog volt ages to be converted The µVision2 simulator also provides an alternate way for entering analog voltage values by writing a script program that runs in paral lel with the program being executed A sample code is appended Please refer to the µVision2 Debug Functions chapter in the Keil s Getting Started and Cre ative Programming document for more information on writing ...

Page 247: ...0 clock cycles from the previous one for i 0 i 0x40 i twatch 900 ain0 0 01 twatch 130100 The reference voltages are also specified through the VREFP and VREFN editable text windows Checks to evaluate the validity of the values placed in these windows are also implemented Should the difference between the val ue in VREFP and VREFN exceed 2 5V the error message in Figure 17 9 is displayed Figure 17 ...

Page 248: ...mation shifter options no source aAccumulate shift and accu mulate shift One of these options must be selected The default is the no source option In the accompanying example as indicated in Figure 17 10 the accumulate shift option was selected Activating the Acc Count window permits the developer to determine the number of 24 bit data samples to be automatically accumulated The count choice optio...

Page 249: ...eripheral is set up with the following features VREF 2 5V Buff is turned on and BOD Burn Out Detect is turned off by assigning a value of 0x20 to ADCON0 This register setting also selects an unity gain amplification for the PGA The bipolar option and the auto filter options are selected through ADCON1 Setting the value of register byte also makes the calibration selec tion In this case the reserve...

Page 250: ...it_accumulator Clearing the SSCON register will always reset the concatenated string of ACCR3 ACCR2 ACCR1 ACCR0 registers This must be performed prior to initiating a fresh set of A D Conversion result accumulation SSCON 0x00 Set Summation Shifter for 8 A D result accumulation and averaging SSCON 0xD2 void setport void P3DDRL 0xf0 P3DDRL 0x07 P30 input P31 output TF2 CLEAR T2 CLEAR CKCON 0x20 Set ...

Page 251: ...th sign extension j ADRESH j 8 j ADRESM j 8 j ADRESL j 0x00ffffff eleminate upper nibble if j 0x00800000 is result negative j 0x0ff000000 return j char init_a_to_d char i j Setup ADC ADCON0 0x30 Vref on 2 5V Buff on BOD off ADCON0 0x20 Vref on 1 25V Buff on BOD off ADCON1 0X00 ADCON2 0xFF decimation ratio ADCON3 0x00 ADCON1 0x05 bipolar Filter auto self calibration offset gain wait for the calibra...

Page 252: ...8 j 1 j 1 return j void a_to_d_accumulate void interrupt 6 using 1 interrupt type 6 vectored to 0x33 Any AI type interrupt would come to this ISR Evaluating the SUM and ADC bits of AISTAT will determine whether the ISR call was due to the A D Converter interrupt or the Summation Shifter interrupt if AISTAT 0x20 A D conversion interrupt converting 0 AISTAT 0x20 clear ADC bit if AISTAT 0x40 Acculula...

Page 253: ... 0 n Enable global interrupt and enable Power Fail Interrupt IE 0x80 EPFI 1 initialize A D converter and extract Accumulation Count accum_count init_a_to_d Wait for conversion to be completed while AISTAT 0x20 Conversion completed then read result of the A D converter l read_a_to_d_result set conversion constants max_range and vref if ADCON1 0x40 is polarity unipolar or bipolar unipolar max_range ...

Page 254: ...t l vref max_range printf nInstantaneous Value ld i e f volts l voltage_value break default Averaged A D conversion results PAI 0x60 for i 0 i 0x40 i averaging 1 averaged conversion idle loop Value of averaging is changed in the a_to_d_accumulate ISR which is called at the end of each completed averaging sequence while averaging Get LONG integer result and convert to a floating point voltage value...

Page 255: ...ll zeroes so it can start the next batch of eight sample averaging with a clean slate This can be most conveniently achieved by assigning a 0x00 value to the SSCON SFR However in this case the contents of this register must be replenished with the previous value of 0xD2 in order to properly set the operating parameters for the summation shifter module This is equivalent to calling the init_accumul...

Page 256: ...Summation Shifter 17 28 Figure 17 11 summation Shifter Peripheral Figure 17 12 The ADC Peripheral Mid Stride a Typical 8 Sample Averaging Block ...

Page 257: ...tly incremented by an incremental value of 0 01V After the AIN0 value has been initialized a delay of 196 000 CPU clock samples is imposed while the main program which started at the same time as this debug program is performing its parameter initialization and book keeping until it is ready for the next data to be sampled Within the For Loop another 900 CPU clock delay is imposed then the value o...

Page 258: ...al Selecting any of the itemized interrupt sources will force its pertinent associated settings and status value to be transferred to the set of check boxes in the lower part of the Interrupt display Clicking on its corresponding check box could alter the status of each piece of information On the Interrupt display shown in Figure 17 13 the set of check boxes in the lower section of the display in...

Page 259: ... clicking once on checked bit pattern toggle switches for bits 7 5 3 and 1 in any se quence This by the way sets the Port 0 pins as inputs for port pins 0 1 2 and 3 and strong driver outputs for pins 4 5 6 and 7 Byte values of 0x55 and 0xFF could just as well have been written into the P0DDRH and P0DDRL registers respectively through the software program for the same effect Until a port read is pe...

Page 260: ...hood of a data overflow is virtually eliminated The snapshot in Figure 17 16 shows the freeze framed picture of the SPI peripheral window in the middle of a typical data communication transmit receive session Figure 17 16 SPI Peripheral Window Like the other peripheral modules pertinent SFRs could be programmed or updated by writing the appropriate data into the associated editable text win dow or...

Page 261: ...at all this window text editing and check box marking are just alternative methods of programming the various SFRs in software The circular buffer can be set or redefined by writing the desired value into the editable transmit pointer window SPISTART and the editable receive buffer window SPIEND You will observe that whatever entry is made into the SPIS TART text window also appears in the non edi...

Page 262: ...s are enabled and the processor is globally interrupt enabled After having properly set up the I O system for the Serial 1 window and initial izing the interrupt enables and the SPI Communication system this program sends out a dummy data byte to start up the communication The processor then enters an infinite loop that is interrupted anytime there is an SPI transmit or receive interrupt The SPIT ...

Page 263: ...2 to clk 4 RCAP2 0xffd9 Set Timer 2 to Generate 57690 bps Initialize TH2 TL2 so that next clock generates first Baud Rate pulse THL2 0xffff T2CON 0x34 Set T2 for Serial0 Tx Rx baud generation SCON Async mode 1 8 bit UART enable rcvr TI CLEAR RI CLEAR SCON 0x50 PCON 0x80 Set SMOD0 for 16X baud rate clock void init_spi enable SPI specify Master SPI and specify clock rate Fosc 32 and CPHA 1 SPICON 0x...

Page 264: ... SPIT bit in the AISTAT SFR is cleared before exiting out of this block if AISTAT 0x08 Transmitter j 2 set up value of j to be transmitted SPIDATA j transmit j This actually goes to the circular buffer AISTAT 0x08 clear SPI transmit interrupt flag The static integer variable i is checked to make sure that the array limits for the received_data array of characters is not exceeded If the limit has b...

Page 265: ...e SPI channel is read at the SPIDATA SFR received_data l SPIDATA keep track of received data void main void setport init_spi test_spi In addition to the main simulation program a µVision 2 debugging program was also written to supply the received data to the test simulation program This µVision program transmits and receives data at periodic intervals from the main program The SPI communication pr...

Page 266: ...in j send byte data twatch 100 idle 100 clock cycles while 1 start infinite loop twatch 50 j increment value of byte data to be transmitted spi_in j transmit another byte of data twatch 97 wait 97 clock cycles data transmitted from main program has been receive in portal SPI_OUT automatically Its value is displayed in the Command Line display area printf nSPI_OUT d spi_out j send another increment...

Page 267: ...plained by the fact that once in a while the two programs become unsynchronized Better twatch delay timing would have resolved this issue but that is not the essence of this example The Serial 1 window shows the results of two 50 byte transfers from the µVersion 2 debug program Note Even though the µVersion 2 debug program and the main SPI program are separate and independent programs they run in ...

Page 268: ...Capture pair RCAP2H RCAP2L RCAP2 required to produce a baud rate of 37 500bps was computed to be 0xFFC4 Presetting the Timer 2 register pair TH2 TL2 THL2 to 0xFFFF ensures that Timer 2 generates an overflow on the first fOSC divide by 4 clock This automatically generates an overflow pulse which is further divided by 16 to drive the Rx and or Tx clocks In addition upon overflow the contents of the ...

Page 269: ...transmit baud rate and the receive baud rate non editable windows respectively Note The transmit baudrate and the receive baudrate do not necessarily have to come from the same timer overflow source You have a choice of two indepen dent sources of the divide by 16 transmit receive counters Setting or clearing the bit fields for RCLK and TCLK of the T2CON SFR respectively determine independently wh...

Page 270: ... clock source for the divide by 16 clock for the Transmit block while Timer 1 is the implied source for the divide by 16 clock for the Receive block TR2 is activated T2CON 0x14 SCON Async mode 1 8 bit UART enable rcvr TI CLEAR RI CLEAR SCON 0x50 PCON 0x80 Set SMOD0 for 16X baud rate clock set Timer 1 up for Rx Baud Rate Generation 37500 bps TH1 0xF6 Make the Timer 1 clocking Gated This implies tha...

Page 271: ...ulas outlined in the timer section of this manual the communication baud rate computes as follows If the TM2 bit of CKCON is 0 then clock divide is fOSC 12 BaudRate fOSC 2 16 0x10000 RCAP2 RCAP2 is a concatenation of the SFR pair RCAP2H RCAP2L In this example it carries a value of 0xFFC4 Hence the generated baud rate works out to be 12 500bps If the faster clocking option of fOSC 4 was selected th...

Page 272: ...ase because SMOD car ries a value of one For the case in which the T1M bit of CKCON is cleared the value of 12 in the denominator is a consequence of the fOSC 12 option se lected whereas the factor of 4 in the denominator of the second expression is a consequence of choosing the fOSC 4 option With the value for TH1 set at 0xFB the first expression results in a baud rate of 12 500bps while the seco...

Page 273: ...Serial Port I O 17 45 Keil Simulator Figure 17 19 Clock Control Peripheral Figure 17 20 USART0 Preipheral ...

Page 274: ...itional Resource 17 46 17 14 Additional Resource It is highly recommended that you review the Keil Compiler tutorial integrated into this package for an animated demonstration of some useful IDE facilities ...

Page 275: ...s in the MSC1210 Compared to the 8052 0 0 0 0 0 0 0 Appendix A deals with additional features found in the MSC1210 as compared to the 8052 Topic Page A 1 Addtional Features in the MSC1210 Compared to the 8052 A 2 Appendix A ...

Page 276: ...cluded in a standard 8052 microcontroller Flash memory up to 32k partitionable as program and or data memory Low voltage brownout detection High speed core 4 clocks per instruction cycle Dual data pointers DPTR 1280 bytes on chip SRAM 256 bytes internal RAM 1024 bytes address able as external RAM 2k boot ROM 32 bit accumulator Watchdog timer Master Slave SPI with DMA 16 bit PWM 24 bit ADC ...

Page 277: ...B 1 Clock Timing Diagram 30 0 Appendix B diagrams the MSC1210 ADC timing chain and clock control Topic Page B 1 MSC1210 Timing Chain and Clock Control Diagram B 2 Appendix B ...

Page 278: ...MSC1210 Timing Chain and Clock Control Diagram B 2 B 1 MSC1210 Timing Chain and Clock Control Diagram Figure B 1 MSC1210 Timing Chain and Clock Control ...

Page 279: ...C 1 Boot ROM Routines 0 0 Appendix C defines the MSC1210 ADC boot ROM routines Topic Page C 1 Description C 2 Appendix C ...

Page 280: ...a_read char faddr Read HW config byte from address FFE1 data_x_c_read char data_x_c_read int faddr char fdm Read xdata or code byte FFE3 tx_byte void tx_byte char Send byte to UART0 FFE5 tx_hex void tx_hex char Send hex value to UART0 FFE7 putok void putok void Send OK to UART0 FFE9 rx_byte char rx_byte void Read byte from UART0 FFEB rx_byte_echo char rx_byte_echo void Read and echo byte on UART0 ...

Page 281: ...ddress of the string The result or error code is returned in R7 and or R6 with the low byte in R7 and the high byte if any in R6 C 1 1 Note Regarding the put_string Function The put_string routine was designed to print strings that are referenced when the boot ROM is located at 0x0000 and also at 0xF800 This means that it forces the location of the string to match the same 2K segment the program i...

Page 282: ...C 4 ...

Page 283: ...D 1 8052 Instruction Set Quick Reference Guide 0 04 3 0 Appendix D gives a list of the 8052 instruction set Topic Page D 1 8052 Instruction Set Quick Reference Guide D 2 Appendix D ...

Page 284: ...BB A R5 DD XCHD A R5 1E DEC R6 5E ANL A R6 9E SUBB A R6 DE XCHD A R6 1F DEC R7 5F ANL A R7 9F SUBB A R7 DF XCHD A R7 20 JB bitAddr relAddr 60 JZ relAddr A0 ORL C bitAddr E0 MOVX A DPTR 21 AJMP pg1Addr 61 AJMP pg3Addr A1 AJMP pg5Addr E1 AJMP pg7Addr 22 RET 62 XRL direct A A2 MOV C bitAddr E2 MOVX A R0 23 RL A 63 XRL direct data8 A3 INC DPTR E3 MOVX A R1 24 ADD A data8 64 XRL A data8 A4 MUL AB E4 CL...

Page 285: ...E 1 8052 Instruction Set 0 0 Appendix E lists the 8052 instruction set Topic Page E 1 Description E 2 E 2 8052 Instruction Set E 3 Appendix E ...

Page 286: ...e code Bytes the total number of bytes including the opcode byte that make up the instruction Cycles the number of machine cycles required to execute the instruc tion Flags the flags that are modified by the instruction if any When listing instruction syntax the following terms will be used bitAddr Bit address value 00 FF pgXAddr Absolute 2k 13 bit Address data8 Immediate 8 bit data value data16 I...

Page 287: ...ows ACALL onto the stack least significant byte first and most significant byte second The program counter is then updated so that program execution continues at the indicated address The new value for the program counter is calculated by replacing the least significant byte of the program counter with the second byte of the ACALL instruction and replacing bits 0 2 of the most significant byte of ...

Page 288: ... ADDC A R0 0x38 1 1 C AC OV ADDC A R1 0x39 1 1 C AC OV ADDC A R2 0x3A 1 1 C AC OV ADDC A R3 0x3B 1 1 C AC OV ADDC A R4 0x3C 1 1 C AC OV ADDC A R5 0x3D 1 1 C AC OV ADDC A R6 0x3E 1 1 C AC OV ADDC A R7 0x3F 1 1 C AC OV ADD and ADDC both add the value operand to the value of the accumulator leaving the resulting value in the accumulator The value operand is not af fected ADD and ADDC function identic...

Page 289: ...EC AJMP Absolute Jump within 2k Block Syntax AJMP codeAddress Instructions OpCode Bytes Cycles Flags AJMP pg0Addr 0x01 2 2 None AJMP pg1Addr 0x21 2 2 None AJMP pg2Addr 0x41 2 2 None AJMP pg3Addr 0x61 2 2 None AJMP pg4Addr 0x81 2 2 None AJMP pg5Addr 0xA1 2 2 None AJMP pg6Addr 0xC1 2 2 None AJMP pg7Addr 0xE1 2 2 None AJMP unconditionally jumps to the indicated codeAddress The new value for the progr...

Page 290: ...1 1 None ANL A R3 0x5B 1 1 None ANL A R4 0x5C 1 1 None ANL A R5 0x5D 1 1 None ANL A R6 0x5E 1 1 None ANL A R7 0x5F 1 1 None ANL C bitAddr 0x82 2 1 C ANL C bitAddr 0xB0 2 1 C ANL does a bitwise AND operation between operand1 and operand2 leaving the resulting value in operand1 The value of operand2 is not affected A logical AND compares the bits of each operand and sets the corresponding bit in the...

Page 291: ... C CJNE R7 data8 reladdr 0xBF 3 2 C CJNE compares the value of operand1 and operand2 and branches to the indicated relative address if the two operands are not equal If the two operands are equal program flow continues with the instruction following the CJNE instruction The carry C bit is set if operand1 is less than operand2 otherwise it is cleared See also DJNZ CLR Clear Register Syntax CLR regi...

Page 292: ...ented is based on the last value written to that bit not the last value read from it See also CLR SETB DA Decimal Adjust Accumulator Syntax DA A Instructions OpCode Bytes Cycles Flags DA A 0xD4 1 1 C DA adjusts the contents of the accumulator to correspond to a BCD binary coded decimal number after two BCD numbers have been added by the ADD or ADDC instruction If the carry bit is set or if the val...

Page 293: ...egister by 1 If the initial value of register is 0 decrementing the value causes it to reset to 255 0xFFH Note The carry flag is not set when the value rolls over from 0 to 255 See also INC SUBB DIV Divide Accumulator by B Syntax DIV AB Instructions OpCode Bytes Cycles Flags DIV AB 0x84 1 1 C OV Divides the unsigned value of the accumulator by the unsigned value of the B register The resulting quo...

Page 294: ...ne DJNZ R4 relAddr 0xDC 2 2 None DJNZ R5 relAddr 0xDD 2 2 None DJNZ R6 relAddr 0xDE 2 2 None DJNZ R7 relAddr 0xDF 2 2 None DJNZ decrements the value of register by 1 If the initial value of register is 0 decrementing the value causes it to reset to 255 0xFFH If the new value of register is not 0 the program branchs to the address indicated by relAddr If the new value of register is 0 program flow ...

Page 295: ...x0E 1 1 None INC R7 0x0F 1 1 None INC DPTR 0xA3 1 2 None INC increments the value of register by 1 If the initial value of register is 255 0xFFH incrementing the value causes it to reset to 0 Note The carry flag is not set when the value rolls over from 255 to 0 In the case of INC DPTR the two byte value of DPTR is incremented as an unsigned integer If the initial value of DPTR is 65 535 0xFFFFH i...

Page 296: ...ags JBC bitAddr reladdr 0x10 3 2 None JBC branches to the address indicated by relAddr if the bit indicated by bitAddr is set Before branching to relAddr the instruction clears the indicated bit If the bit is not set program execution continues with the instruction following the JBC instruction and the value of the bit is not changed See also JB JNB JC Jump if Carry Set Syntax JC relAddr Instructi...

Page 297: ...ructions OpCode Bytes Cycles Flags JNB bitAddr relAddr 0x30 3 2 None JNB branches to the address indicated by relAddr if the indicated bit is not set If the bit is set program execution continues with the instruction following the JNB instruction See also JB JBC JNC Jump if Carry Not Set Syntax JNC reladdr Instructions OpCode Bytes Cycles Flags JNC relAddr 0x50 2 2 None JNC branches to the address...

Page 298: ...e value 0 If the value of the accumulator is not zero program execution con tinues with the instruction following the JNZ instruction See also JNZ LCALL Long Call Syntax LCALL address16 Instructions OpCode Bytes Cycles Flags LCALL address16 0x12 3 2 None LCALL calls a program subroutine LCALL increments the program counter by 3 to point to the instruction following LCALL and pushes that value onto...

Page 299: ...R7 0xEF 1 1 None MOV A direct 0xE5 2 1 None MOV R0 A 0xF8 1 1 None MOV R1 A 0xF9 1 1 None MOV R2 A 0xFA 1 1 None MOV R3 A 0xFB 1 1 None MOV R4 A 0xFC 1 1 None MOV R5 A 0xFD 1 1 None MOV R6 A 0xFE 1 1 None MOV R7 A 0xFF 1 1 None MOV direct A 0xF5 2 1 None MOV copies the value of operand2 into operand1 The value of operand2 is not affected See also MOVC MOVX XCH XCHD PUSH POP MOV Move Into Out of Ca...

Page 300: ... MOV R6 direct 0xAE 2 2 None MOV R7 direct 0xAF 2 2 None MOV direct data8 0x75 3 2 None MOV direct R0 0x86 2 2 None MOV direct R1 0x87 2 2 None MOV direct R0 0x88 2 2 None MOV direct R1 0x89 2 2 None MOV direct R2 0x8A 2 2 None MOV direct R3 0x8B 2 2 None MOV direct R4 0x8C 2 2 None MOV direct R5 0x8D 2 2 None MOV direct R6 0x8E 2 2 None MOV direct R7 0x8F 2 2 None MOV direct1 direct2 0x85 3 2 Non...

Page 301: ... Move Data to from External RAM Syntax MOVX operand1 operand2 Instructions OpCode Bytes Cycles Flags MOVX DPTR A 0xF0 1 2 None MOVX R0 A 0xF2 1 2 None MOVX R1 A 0xF3 1 2 None MOVX A DPTR 0xE0 1 2 None MOVX A R0 0xE2 1 2 None MOVX A R1 0xE3 1 2 None MOVX moves a byte to or from external memory into or from the accumulator If operand1 is DPTR the accumulator is moved to the 16 bit external memory ad...

Page 302: ...r and the most significant byte is placed in the B register The carry C flag is always cleared The overflow OV flag is set if the result is greater than 255 if the most significant byte is not zero Otherwise it is cleared See also DIV NOP No Operation Syntax NOP Instructions OpCode Bytes Cycles Flags NOP 0x00 1 1 None NOP as its name suggests causes no operation to take place for one machine cycle...

Page 303: ...e ORL A R2 0x4A 1 1 None ORL A R3 0x4B 1 1 None ORL A R4 0x4C 1 1 None ORL A R5 0x4D 1 1 None ORL A R6 0x4E 1 1 None ORL A R7 0x4F 1 1 None ORL C bitAddr 0x72 2 2 C ORL C bitAddr 0xA0 2 1 C ORL does a bitwise OR operation between operand1 and operand2 leaving the resulting value in operand1 The value of operand2 is not affected A logical OR compares the bits of each operand and sets the correspond...

Page 304: ...P ACC not POP A The latter is invalid and will result in an error at assemble time See also PUSH PUSH Push Value onto Stack Syntax PUSH register Instructions OpCode Bytes Cycles Flags PUSH direct 0xC0 2 2 None PUSH pushes the value of the specified direct address onto the stack PUSH first increments the value of the stack pointer by 1 then takes the value stored in direct and stores it in internal...

Page 305: ...es Flags RETI 0x32 1 2 None RETI is used to return from an interrupt service routine RETI first enables in terrupts of equal and lower priorities to the interrupt that is terminating Pro gram execution continues at the address that is calculated by POPping the top most 2 bytes off the stack The most significant byte is POPped off the stack first followed by the least significant byte RETI function...

Page 306: ...it bit 0 of the accumulator is loaded into bit 7 See also RL RLC RRC RRC Rotate Accumulator Right Through Carry Syntax RRC A Instructions OpCode Bytes Cycles Flags RRC A 0x13 1 1 C RRC shifts the bits of the accumulator to the right The right most bit bit 0 of the accumulator is loaded into the carry flag and the original carry flag is loaded into bit 7 See also RL RLC RR SETB Set Bit Syntax SETB ...

Page 307: ... 0x9D 1 1 C AC OV SUBB A R6 0x9E 1 1 C AC OV SUBB A R7 0x9F 1 1 C AC OV SUBB subtracts the value of operand from the value of the accumulator leav ing the resulting value in the accumulator The value operand is not affected The carry C bit is set if a borrow was required for bit 7 Otherwise it is cleared In other words if the unsigned value being subtracted is greater than the accu mulator the car...

Page 308: ...1 1 None XCH A R0 0xC8 1 1 None XCH A R1 0xC9 1 1 None XCH A R2 0xCA 1 1 None XCH A R3 0xCB 1 1 None XCH A R4 0xCC 1 1 None XCH A R5 0xCD 1 1 None XCH A R6 0xCE 1 1 None XCH A R7 0xCF 1 1 None XCH A direct 0xC5 2 1 None XCH exchanges the value of the accumulator with the value contained in register See also MOV XCHD Exchange Digit Syntax XCHD A register Instructions OpCode Bytes Cycles Flags XCHD ...

Page 309: ...R1 0x69 1 1 None XRL A R2 0x6A 1 1 None XRL A R3 0x6B 1 1 None XRL A R4 0x6C 1 1 None XRL A R5 0x6D 1 1 None XRL A R6 0x6E 1 1 None XRL A R7 0x6F 1 1 None XRL does a bitwise exclusive OR operation between operand1 and operand2 leaving the resulting value in operand1 The value of operand2 is not affected A logical exclusive OR compares the bits of each operand and sets the corre sponding bit in the...

Page 310: ... is not documented nor defined However based on my research executing this undefined instruction takes one machine cycle and appears to have no effect on the system except that the carry bit always seems to be set Note We received input from an 8052 com user that the undefined instruction real ly has a format of Undefined bit1 bit2 and effectively copies the value of bit2 to bit1 In this case it w...

Page 311: ...1 Bit Addressable SFRs alphabetical 0 0 Appendix F defines the MSC1210 bit addressable special function registers SFRs in alphabetical order Topic Page F 1 Bit Addressable SFRs alphabetical F 2 Appendix F ...

Page 312: ...t pending will trigger inter rupt if EAI bit set WDTI Watchdog Interrupt Flag 1 Watchdog interrupt pending will trig ger interrupt if Watchdog interrupt enabled Extended Interrupt Enable EIE SFR Name EIE SFR Address E8H Bit Addressable Yes Bit Definitions bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Name EWDI EX5 EX4 EX3 EX2 Bit Address EFH EEH EDH ECH EBH EAH E9H E8H EWDI Watchdog Interrupt En...

Page 313: ... level priority PX3 External 3 Interrupt Priority 1 External 3 interrupt high level priority 0 low level priority PX2 External 2 Interrupt Priority 1 External 2 interrupt high level priority 0 low level priority Interrupt Enable IE SFR Name IE SFR Address A8H Bit Addressable Yes Bit Definitions bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Name EA ET2 ES ET1 EX1 ET0 EX0 Bit Address AFH AEH ADH A...

Page 314: ...rrupt 0 low priority interrupt PX0 Priority External 0 Interupt 1 High priority interrupt 0 low priority interrupt Port 0 P0 SFR Name P0 SFR Address 80H Bit Addressable Yes Bit Definitions bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Name AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 Bit Address 87H 86H 85H 84H 83H 82H 81H 80H Note These bit names indicate the function of that I O line on the P0 bus when use...

Page 315: ...Address A0H Bit Addressable Yes Bit Definitions bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Name A15 A14 A13 A12 A11 A10 A9 A8 Bit Address A7H A6H A5H A4H A3H A2H A1H A0H Note These bit names indicate the function of that I O line on the P2 bus when used with external memory code RAM A standard 8052 assembler will not recognize these bits by the given names they will only be recognized as P2 7...

Page 316: ...ter 1 via external source T0 Timer Counter 0 External Input Optionally used to control timer counter 0 via external source INT1 External Interrupt 1 Used to trigger external interrupt 1 INT0 External Interrupt 0 Used to trigger external interrupt 0 TXD Serial Transmit Data 8052 serial transmit line from 8052 to external device RXD Serial Transmit Data 8052 serial receive line to 8052 from external...

Page 317: ... Flag 0 General flag available to developer for user defined purposes RS1 RS0 Register Select Bits These two bits taken together select the register bank used when using R registers R0 through R7 according to the fol lowing table RS1 RS0 Register Bank Register Bank Addresses 0 0 0 00H 07H 0 1 1 08H 0FH 1 0 2 10H 17H 1 1 3 18H 1FH OV Overflow Flag Set or cleared by instructions ADD ADDC SUBB and DI...

Page 318: ... and 3 causing the RI bit to only be set when the ninth bit of a byte received is set In mode 1 RI is only set if a valid stop bit is received SM2 must be cleared in mode 0 REN Received Enable This bit must be set to enable data reception via the serial port No data will be received by the serial port if this bit is clear TB8 Transmit Bit 8 When in modes 2 and 3 this is the ninth bit sent when a b...

Page 319: ...his bit is clear Timer 0 is stopped IE1 External 1 Interrupt Flag This bit is set by the MCU when an external 1 interrupt is detected on the INT1 line Cleared by software or cleared auto matically by hardware if an external 1 interrupt is triggered IT1 External 1 Interrupt Type Flag This bit controls whether or not external 1 interrupt is edge triggered or low level triggered If this bit is set ex...

Page 320: ...ftware RCLK Timer 2 Receive Clock When this bit is set Timer 2 provides the se rial port receive baud rate clock TCLK Timer 2 Transmit Clock When this bit is set Timer 2 provides the serial port transmit baud rate clock EXEN2 Timer 2 External Enable When this bit is set a capture or reload is triggered on a 1 0 transition on the T2EX line TR2 Timer 2 Run Control When this bit is set Timer 2 is act...

Page 321: ...ss Cross Reference Guide alphabetical 0 0 Appendix G lists an alphabetical cross reference of the MSC1210 special function registers SFRs and their addresses Topic Page G 1 SFR Address Cross Reference G 2 Appendix G ...

Page 322: ...Configuration Address 93H CDATA Configuration Data 94H CKCON Clock Control 8EH DPL0 Data Pointer 0 Low 82H DPH0 Data Pointer 0 High 83H DPL1 Data Pointer 1 Low 84H DPH1 Data Pointer 1 High 85H DPS Data Pointer Select 86H EIE Extended Interrupt Enable E8H EIP Extended Interrupt Priority F8H EWU Enable Wake Up from Idle C6H EXIF External Interrupt Flag 91H FMCON Flash Memory Control EEH FTCON Flash ...

Page 323: ...H P1DDRL Port 1 Data Direction Low AEH P2 Port 2 A0H P2DDRH Port 2 Data Direction High B2H P2DDRL Port 2 Data Direction Low B1H P3 Port 3 B0H P3DDRH Port 3 Data Direction High B4H P3DDRL Port 3 Data Direction Low B3H PAI Pending Auxiliary Interrupt A5H PASEL PSEN ALE Select F2H PCON Power Control 87H PDCON Power Down Control F1H PWMCON PWM Control A1H PWMHI PWM High A3H PWMLOW PWM Low A2H RCAP2H R...

Page 324: ...ntrol E1H SSUMR0 Summation Register 0 E2H SSUMR1 Summation Register 1 E3H SSUMR2 Summation Register 2 E4H SSUMR3 Summation Register 3 E5H T2CON Timer 2 Control C8H TCON Timer Control 88H TH0 Timer 0 High 8CH TH1 Timer 1 High 8DH TH2 Timer 2 High CDH TL0 Timer 0 Low 8AH TL1 Timer 1 Low 8BH TL2 Timer 2 Low 8CH TMOD Timer Mode 89H USEC Microseconds FBH WDTCON Watchdog Timer Control FFH ...

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